xref: /netbsd-src/sys/arch/sgimips/include/intr.h (revision 7fa608457b817eca6e0977b37f758ae064f3c99c)
1 /*	$NetBSD: intr.h,v 1.24 2007/10/17 19:57:04 garbled Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *          This product includes software developed for the
18  *          NetBSD Project.  See http://www.NetBSD.org/ for
19  *          information about NetBSD.
20  * 4. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef	_SGIMIPS_INTR_H_
36 #define	_SGIMIPS_INTR_H_
37 
38 #define	IPL_NONE	0	/* Disable only this interrupt. */
39 #define	IPL_SOFT	1	/* generic software interrupts */
40 #define	IPL_SOFTSERIAL	2	/* serial software interrupts */
41 #define	IPL_SOFTNET	3	/* network software interrupts */
42 #define	IPL_SOFTCLOCK	4	/* clock software interrupts */
43 #define	IPL_BIO		5	/* Disable block I/O interrupts. */
44 #define	IPL_NET		6	/* Disable network interrupts. */
45 #define	IPL_TTY		7	/* Disable terminal interrupts. */
46 #define	IPL_SERIAL	IPL_TTY
47 #define	IPL_LPT		IPL_TTY
48 #define	IPL_VM		IPL_TTY
49 #define	IPL_CLOCK	8	/* Disable clock interrupts. */
50 #define	IPL_STATCLOCK	IPL_CLOCK /* Disable profiling interrupts. */
51 #define	IPL_HIGH	9	/* Disable all interrupts. */
52 #define	IPL_SCHED	IPL_HIGH
53 #define	IPL_LOCK	IPL_HIGH
54 #define NIPL		10
55 
56 /* Interrupt sharing types. */
57 #define IST_NONE	0	/* none */
58 #define IST_PULSE	1	/* pulsed */
59 #define IST_EDGE	2	/* edge-triggered */
60 #define IST_LEVEL	3	/* level-triggered */
61 
62 /* Soft interrupt numbers */
63 #define	SI_SOFT		0
64 #define	SI_SOFTCLOCK	1
65 #define	SI_SOFTNET	2
66 #define	SI_SOFTSERIAL	3
67 
68 #define	SI_NQUEUES	4
69 
70 #define	SI_QUEUENAMES {							\
71 	"misc",								\
72 	"clock",							\
73 	"net",								\
74 	"serial",							\
75 }
76 
77 #ifdef _KERNEL
78 #ifndef _LOCORE
79 
80 #include <sys/queue.h>
81 #include <sys/types.h>
82 #include <sys/device.h>
83 #include <mips/cpuregs.h>
84 #include <mips/locore.h>
85 
86 #define NINTR	32
87 
88 struct sgimips_intrhand {
89 	LIST_ENTRY(sgimips_intrhand)
90 		ih_q;
91 	int	(*ih_fun) (void *);
92 	void	 *ih_arg;
93 	struct	sgimips_intr *ih_intrhead;
94 	struct	sgimips_intrhand *ih_next;
95 	int	ih_pending;
96 };
97 
98 struct sgimips_intr {
99 	LIST_HEAD(,sgimips_intrhand)
100 		intr_q;
101 	struct	evcnt ih_evcnt;
102 	unsigned long intr_ipl;
103 };
104 
105 extern struct sgimips_intrhand intrtab[];
106 
107 extern const int *ipl2spl_table;
108 
109 #define splhigh()	_splraise(MIPS_INT_MASK)
110 #define spl0()		(void)_spllower(0)
111 #define splx(s)		(void)_splset(s)
112 #define splbio()	_splraise(ipl2spl_table[IPL_BIO])
113 #define splnet()	_splraise(ipl2spl_table[IPL_NET])
114 #define spltty()	_splraise(ipl2spl_table[IPL_TTY])
115 #define splvm()		spltty()
116 #define splclock()	_splraise(ipl2spl_table[IPL_CLOCK])
117 #define splstatclock()	splclock()
118 
119 #define	splsched()	splhigh()
120 #define	spllock()	splhigh()
121 #define splserial()	spltty()
122 #define spllpt()	spltty()
123 
124 #define splsoft()	_splraise(MIPS_SOFT_INT_MASK_1)
125 #define splsoftclock()	splsoft()
126 #define splsoftnet()	splsoft()
127 #define splsoftserial()	splsoft()
128 
129 extern void *		cpu_intr_establish(int, int, int (*)(void *), void *);
130 
131 typedef int ipl_t;
132 typedef struct {
133 	int _spl;
134 } ipl_cookie_t;
135 
136 ipl_cookie_t makeiplcookie(ipl_t);
137 
138 static inline int
139 splraiseipl(ipl_cookie_t icookie)
140 {
141 
142 	return _splraise(icookie._spl);
143 }
144 
145 #include <mips/softintr.h>
146 
147 #endif /* _LOCORE */
148 #endif /* !_KERNEL */
149 
150 #endif	/* !_SGIMIPS_INTR_H_ */
151