xref: /netbsd-src/sys/arch/sgimips/include/intr.h (revision 481fca6e59249d8ffcf24fef7cfbe7b131bfb080)
1 /*	$NetBSD: intr.h,v 1.2 2000/06/29 15:36:48 soren Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *          This product includes software developed for the
18  *          NetBSD Project.  See http://www.netbsd.org/ for
19  *          information about NetBSD.
20  * 4. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #define	IPL_NONE	0	/* Disable only this interrupt. */
36 #define	IPL_BIO		1	/* Disable block I/O interrupts. */
37 #define	IPL_NET		2	/* Disable network interrupts. */
38 #define	IPL_TTY		3	/* Disable terminal interrupts. */
39 #define	IPL_CLOCK	4	/* Disable clock interrupts. */
40 #define	IPL_STATCLOCK	5	/* Disable profiling interrupts. */
41 #ifndef __NO_SOFT_SERIAL_INTERRUPT
42 #define	IPL_SERIAL	6	/* Disable serial hardware interrupts. */
43 #endif
44 #define	IPL_HIGH	7	/* Disable all interrupts. */
45 #define NIPL		8
46 
47 /* Interrupt sharing types. */
48 #define IST_NONE	0	/* none */
49 #define IST_PULSE	1	/* pulsed */
50 #define IST_EDGE	2	/* edge-triggered */
51 #define IST_LEVEL	3	/* level-triggered */
52 
53 /* Soft interrupt masks. */
54 #define SIR_CLOCK	31
55 #define SIR_NET		30
56 #define SIR_CLOCKMASK	((1 << SIR_CLOCK))
57 #define SIR_NETMASK	((1 << SIR_NET) | SIR_CLOCKMASK)
58 #define SIR_ALLMASK	(SIR_CLOCKMASK | SIR_NETMASK)
59 
60 #ifdef _KERNEL
61 #ifndef _LOCORE
62 
63 #include <mips/cpuregs.h>
64 
65 extern int		_splraise(int);
66 extern int		_spllower(int);
67 extern int		_splset(int);
68 extern int		_splget(void);
69 extern void		_splnone(void);
70 extern void		_setsoftintr(int);
71 extern void		_clrsoftintr(int);
72 
73 #define setsoftclock()	_setsoftintr(MIPS_SOFT_INT_MASK_0)
74 #define setsoftnet()	_setsoftintr(MIPS_SOFT_INT_MASK_1)
75 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
76 #define clearsoftnet()	_clrsoftintr(MIPS_SOFT_INT_MASK_1)
77 
78 extern u_int32_t 	biomask;
79 extern u_int32_t 	netmask;
80 extern u_int32_t 	ttymask;
81 extern u_int32_t 	clockmask;
82 
83 #define splhigh()       _splraise(MIPS_INT_MASK)
84 #define spl0()          (void)_spllower(0)
85 #define splx(s)         (void)_splset(s)
86 #define splbio()        _splraise(biomask)
87 #define splnet()        _splraise(netmask)
88 #define spltty()        _splraise(ttymask)
89 #define splimp()        spltty()
90 #define splclock()      _splraise(clockmask)
91 #define splstatclock()  splclock()
92 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
93 #define splsoftclock()  _splraise(MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1)
94 #define splsoftnet()    _splraise(MIPS_SOFT_INT_MASK_1)
95 
96 #define spllpt()	spltty()
97 
98 extern unsigned int	intrcnt[];
99 #define SOFTCLOCK_INTR	0
100 #define SOFTNET_INTR	1
101 
102 extern void *		cpu_intr_establish(int, int, int (*)(void *), void *);
103 
104 #endif /* _LOCORE */
105 #endif /* _KERNEL */
106