xref: /netbsd-src/sys/arch/sgimips/include/intr.h (revision 3b01aba77a7a698587faaae455bbfe740923c1f5)
1 /*	$NetBSD: intr.h,v 1.9 2001/06/08 00:09:28 rafal Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *          This product includes software developed for the
18  *          NetBSD Project.  See http://www.netbsd.org/ for
19  *          information about NetBSD.
20  * 4. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef	_SGIMIPS_INTR_H_
36 #define	_SGIMIPS_INTR_H_
37 
38 #define	IPL_NONE	0	/* Disable only this interrupt. */
39 #define	IPL_BIO		1	/* Disable block I/O interrupts. */
40 #define	IPL_NET		2	/* Disable network interrupts. */
41 #define	IPL_TTY		3	/* Disable terminal interrupts. */
42 #define	IPL_CLOCK	4	/* Disable clock interrupts. */
43 #define	IPL_STATCLOCK	5	/* Disable profiling interrupts. */
44 #ifndef __NO_SOFT_SERIAL_INTERRUPT
45 #define	IPL_SERIAL	6	/* Disable serial hardware interrupts. */
46 #endif
47 #define	IPL_HIGH	7	/* Disable all interrupts. */
48 #define NIPL		8
49 
50 /* Interrupt sharing types. */
51 #define IST_NONE	0	/* none */
52 #define IST_PULSE	1	/* pulsed */
53 #define IST_EDGE	2	/* edge-triggered */
54 #define IST_LEVEL	3	/* level-triggered */
55 
56 /* Soft interrupt numbers */
57 #ifndef __NO_SOFT_SERIAL_INTERRUPT
58 #define	IPL_SOFTSERIAL	0	/* serial software interrupts */
59 #endif
60 #define	IPL_SOFTNET	1	/* network software interrupts */
61 #define	IPL_SOFTCLOCK	2	/* clock software interrupts */
62 #define	IPL_NSOFT	3
63 
64 #define	IPL_SOFTNAMES {							\
65 	"serial",							\
66 	"net",								\
67 	"clock",							\
68 }
69 
70 #ifdef _KERNEL
71 #ifndef _LOCORE
72 
73 #include <sys/queue.h>
74 #include <sys/types.h>
75 #include <sys/device.h>
76 #include <mips/cpuregs.h>
77 
78 /*
79  * software simulated interrupt
80  */
81 #define setsoft(x)	do {			\
82 	extern u_int ssir;			\
83 	int s;					\
84 						\
85 	s = splhigh();				\
86 	ssir |= 1 << (x);			\
87 	_setsoftintr(MIPS_SOFT_INT_MASK_1);	\
88 	splx(s);				\
89 } while (0)
90 
91 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
92 
93 #define softintr_schedule(arg)						\
94 do {									\
95 	struct sgi_intrhand *__ih = (arg);				\
96 	__ih->ih_pending = 1;						\
97 	setsoft(__ih->ih_intrhead->intr_ipl);				\
98 } while (0)
99 
100 extern struct sgi_intrhand *softnet_intrhand;
101 
102 #define	setsoftnet()	softintr_schedule(softnet_intrhand)
103 
104 #else /* ! __HAVE_GENERIC_SOFT_INTERRUPTS */
105 
106 #define SIR_NET		0x01
107 #define SIR_SERIAL	0x02
108 
109 #define setsoftclock()	_setsoftintr(MIPS_SOFT_INT_MASK_0)
110 #define setsoftnet()	setsoft(SIR_NET)
111 #define setsoftserial()	setsoft(SIR_SERIAL)
112 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */
113 
114 #define NINTR	32
115 
116 struct sgi_intrhand {
117 	LIST_ENTRY(sgi_intrhand)
118 		ih_q;
119 	int	(*ih_fun) __P((void *));
120 	void	 *ih_arg;
121 	struct	sgi_intr *ih_intrhead;
122 	int	ih_pending;
123 };
124 
125 struct sgi_intr {
126 	LIST_HEAD(,sgi_intrhand)
127 		intr_q;
128 	struct	evcnt ih_evcnt;
129 	unsigned long intr_ipl;
130 };
131 
132 extern struct sgi_intrhand intrtab[];
133 
134 extern int		_splraise(int);
135 extern int		_spllower(int);
136 extern int		_splset(int);
137 extern int		_splget(void);
138 extern void		_splnone(void);
139 extern void		_setsoftintr(int);
140 extern void		_clrsoftintr(int);
141 
142 extern u_int32_t 	biomask;
143 extern u_int32_t 	netmask;
144 extern u_int32_t 	ttymask;
145 extern u_int32_t 	clockmask;
146 
147 #define splhigh()       _splraise(MIPS_INT_MASK)
148 #define spl0()          (void)_spllower(0)
149 #define splx(s)         (void)_splset(s)
150 #define splbio()        _splraise(biomask)
151 #define splnet()        _splraise(netmask)
152 #define spltty()        _splraise(ttymask)
153 #define	splserial()	spltty()
154 #define splvm()         spltty()
155 #define splclock()      _splraise(clockmask)
156 #define splstatclock()  splclock()
157 
158 #define	splsched()	splhigh()
159 #define	spllock()	splhigh()
160 #define spllpt()	spltty()
161 
162 #define splsoft()	_splraise(MIPS_SOFT_INT_MASK_1)
163 #define splsoftclock()	splsoft()
164 #define splsoftnet()	splsoft()
165 
166 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_1)
167 
168 extern void *		cpu_intr_establish(int, int, int (*)(void *), void *);
169 void *			softintr_establish(int, void (*)(void *), void *);
170 void			softintr_disestablish(void *);
171 void			softintr_init(void);
172 void			softintr_dispatch(void);
173 
174 
175 #endif /* _LOCORE */
176 #endif /* _KERNEL */
177 
178 #endif	/* !_SGIMIPS_INTR_H_ */
179