1 /* $NetBSD: pi1ppc.c,v 1.9 2011/02/16 23:44:20 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * Copyright (c) 2003, 2004 Gary Thorpe <gathorpe@users.sourceforge.net> 6 * Copyright (c) 2005 Joe Britt <britt@danger.com> - SGI PI1 version 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp 32 * 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: pi1ppc.c,v 1.9 2011/02/16 23:44:20 jmcneill Exp $"); 37 38 #include "opt_pi1ppc.h" 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 #include <sys/systm.h> 47 #include <sys/vnode.h> 48 #include <sys/syslog.h> 49 50 #include <machine/bus.h> 51 /*#include <machine/intr.h>*/ 52 53 #include <dev/ppbus/ppbus_conf.h> 54 #include <dev/ppbus/ppbus_msq.h> 55 #include <dev/ppbus/ppbus_io.h> 56 #include <dev/ppbus/ppbus_var.h> 57 58 #include <machine/autoconf.h> 59 #include <machine/machtype.h> 60 61 #include <sgimips/ioc/iocreg.h> 62 63 #include <sgimips/hpc/hpcvar.h> 64 #include <sgimips/hpc/hpcreg.h> 65 66 #include <sgimips/hpc/pi1ppcreg.h> 67 #include <sgimips/hpc/pi1ppcvar.h> 68 69 #ifdef PI1PPC_DEBUG 70 int pi1ppc_debug = 1; 71 #endif 72 73 #ifdef PI1PPC_VERBOSE 74 int pi1ppc_verbose = 1; 75 #endif 76 77 78 /* Prototypes for functions. */ 79 80 /* PC-style register emulation */ 81 static uint8_t r_reg(int reg, struct pi1ppc_softc *pi1ppc); 82 static void w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte); 83 84 #define AT_DATA_REG 0 85 #define AT_STAT_REG 1 86 #define AT_CTL_REG 2 87 88 #define pi1ppc_r_str(_x) r_reg(AT_STAT_REG,_x) 89 #define pi1ppc_r_ctr(_x) r_reg(AT_CTL_REG,_x) 90 #define pi1ppc_r_dtr(_x) r_reg(AT_DATA_REG,_x) 91 92 #define pi1ppc_w_str(_x,_y) 93 #define pi1ppc_w_ctr(_x,_y) w_reg(AT_CTL_REG,_x,_y) 94 #define pi1ppc_w_dtr(_x,_y) w_reg(AT_DATA_REG,_x,_y) 95 96 /* do we need to do these? */ 97 #define pi1ppc_barrier_r(_x) bus_space_barrier(_x->sc_iot,_x->sc_ioh, \ 98 0,4,BUS_SPACE_BARRIER_READ) 99 #define pi1ppc_barrier_w(_x) bus_space_barrier(_x->sc_iot,_x->sc_ioh, \ 100 0,4,BUS_SPACE_BARRIER_WRITE) 101 #define pi1ppc_barrier(_x) pi1ppc_barrier_r(_x) 102 103 104 /* Print function for config_found() */ 105 static int pi1ppc_print(void *, const char *); 106 107 /* Routines for ppbus interface (bus + device) */ 108 static int pi1ppc_read(device_t, char *, int, int, size_t *); 109 static int pi1ppc_write(device_t, char *, int, int, size_t *); 110 static int pi1ppc_setmode(device_t, int); 111 static int pi1ppc_getmode(device_t); 112 static int pi1ppc_exec_microseq(device_t, struct ppbus_microseq * *); 113 static uint8_t pi1ppc_io(device_t, int, u_char *, int, u_char); 114 static int pi1ppc_read_ivar(device_t, int, unsigned int *); 115 static int pi1ppc_write_ivar(device_t, int, unsigned int *); 116 static int pi1ppc_add_handler(device_t, void (*)(void *), void *); 117 static int pi1ppc_remove_handler(device_t, void (*)(void *)); 118 119 /* no-ops, do any IOC machines have ECP/EPP-capable ports? */ 120 static void pi1ppc_reset_epp_timeout(device_t); 121 static void pi1ppc_ecp_sync(device_t); 122 123 /* Utility functions */ 124 125 /* Functions to read bytes into device's input buffer */ 126 static void pi1ppc_nibble_read(struct pi1ppc_softc * const); 127 static void pi1ppc_byte_read(struct pi1ppc_softc * const); 128 129 /* Functions to write bytes to device's output buffer */ 130 static void pi1ppc_std_write(struct pi1ppc_softc * const); 131 132 /* Miscellaneous */ 133 static void pi1ppc_set_intr_mask(struct pi1ppc_softc * const, uint8_t); 134 static uint8_t pi1ppc_get_intr_stat(struct pi1ppc_softc * const); 135 136 #ifdef USE_INDY_ACK_HACK 137 static uint8_t pi1ppc_get_intr_mask(struct pi1ppc_softc * const); 138 #endif 139 140 static int pi1ppc_poll_str(struct pi1ppc_softc * const, const uint8_t, 141 const uint8_t); 142 static int pi1ppc_wait_interrupt(struct pi1ppc_softc * const, const void *, 143 const uint8_t); 144 145 static int pi1ppc_poll_interrupt_stat(struct pi1ppc_softc * const, 146 const uint8_t); 147 148 static int pi1ppc_match(device_t parent, cfdata_t match, void *aux); 149 static void pi1ppc_attach(device_t parent, device_t self, void *aux); 150 151 CFATTACH_DECL_NEW(pi1ppc, sizeof(struct pi1ppc_softc), 152 pi1ppc_match, 153 pi1ppc_attach, 154 NULL, 155 NULL); 156 157 /* Currently only matching on Indy, though I think the Indigo1 also 158 uses PI1. If it does, then the driver should work (if it is attached 159 at the appropriate base addr). 160 */ 161 162 static int 163 pi1ppc_match(device_t parent, cfdata_t match, void *aux) 164 { 165 struct hpc_attach_args *ha = aux; 166 167 if (strcmp(ha->ha_name, match->cf_name) != 0) 168 return 0; 169 170 if (mach_type == MACH_SGI_IP22) 171 return 1; 172 173 return 0; 174 } 175 176 static void 177 pi1ppc_attach(device_t parent, device_t self, void *aux) 178 { 179 struct pi1ppc_softc *sc; 180 struct hpc_attach_args *haa; 181 182 sc = device_private(self); 183 sc->sc_dev = self; 184 haa = aux; 185 sc->sc_iot = haa->ha_st; 186 187 if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff, 188 0x28, /* # bytes in par port regs */ 189 &sc->sc_ioh)) { 190 aprint_error(": unable to map control registers\n"); 191 return; 192 } 193 194 pi1ppc_sc_attach(sc); 195 } 196 197 /* 198 * Generic attach and detach functions for pi1ppc device. 199 * 200 * If sc_dev_ok in soft configuration data is not ATPPC_ATTACHED, these should 201 * be skipped altogether. 202 */ 203 204 /* Soft configuration attach for pi1ppc */ 205 void 206 pi1ppc_sc_attach(struct pi1ppc_softc *lsc) 207 { 208 /* Adapter used to configure ppbus device */ 209 struct parport_adapter sc_parport_adapter; 210 char buf[64]; 211 212 PI1PPC_LOCK_INIT(lsc); 213 214 /* For a PC, this is where the installed chipset is probed. 215 * We *know* what we have, no need to probe. 216 */ 217 lsc->sc_type = PI1PPC_TYPE_INDY; 218 lsc->sc_model = GENERIC; 219 220 /* XXX Once we support Interrupts & DMA, update this */ 221 lsc->sc_has = PI1PPC_HAS_PS2; 222 223 /* Print out chipset capabilities */ 224 snprintb(buf, sizeof(buf), "\20\1INTR\2DMA\3FIFO\4PS2\5ECP\6EPP", 225 lsc->sc_has); 226 printf("\n%s: capabilities=%s\n", device_xname(lsc->sc_dev), buf); 227 228 /* Initialize device's buffer pointers */ 229 lsc->sc_outb = lsc->sc_outbstart = lsc->sc_inb = lsc->sc_inbstart 230 = NULL; 231 lsc->sc_inb_nbytes = lsc->sc_outb_nbytes = 0; 232 233 /* Last configuration step: set mode to standard mode */ 234 if (pi1ppc_setmode(lsc->sc_dev, PPBUS_COMPATIBLE) != 0) { 235 PI1PPC_DPRINTF(("%s: unable to initialize mode.\n", 236 device_xname(lsc->sc_dev))); 237 } 238 239 #if defined (MULTIPROCESSOR) || defined (LOCKDEBUG) 240 /* Initialize lock structure */ 241 simple_lock_init(&(lsc->sc_lock)); 242 #endif 243 244 /* Set up parport_adapter structure */ 245 246 /* Set capabilites */ 247 sc_parport_adapter.capabilities = 0; 248 if (lsc->sc_has & PI1PPC_HAS_INTR) { 249 sc_parport_adapter.capabilities |= PPBUS_HAS_INTR; 250 } 251 if (lsc->sc_has & PI1PPC_HAS_DMA) { 252 sc_parport_adapter.capabilities |= PPBUS_HAS_DMA; 253 } 254 if (lsc->sc_has & PI1PPC_HAS_FIFO) { 255 sc_parport_adapter.capabilities |= PPBUS_HAS_FIFO; 256 } 257 if (lsc->sc_has & PI1PPC_HAS_PS2) { 258 sc_parport_adapter.capabilities |= PPBUS_HAS_PS2; 259 } 260 261 /* Set function pointers */ 262 sc_parport_adapter.parport_io = pi1ppc_io; 263 sc_parport_adapter.parport_exec_microseq = pi1ppc_exec_microseq; 264 sc_parport_adapter.parport_setmode = pi1ppc_setmode; 265 sc_parport_adapter.parport_getmode = pi1ppc_getmode; 266 sc_parport_adapter.parport_read = pi1ppc_read; 267 sc_parport_adapter.parport_write = pi1ppc_write; 268 sc_parport_adapter.parport_read_ivar = pi1ppc_read_ivar; 269 sc_parport_adapter.parport_write_ivar = pi1ppc_write_ivar; 270 sc_parport_adapter.parport_dma_malloc = lsc->sc_dma_malloc; 271 sc_parport_adapter.parport_dma_free = lsc->sc_dma_free; 272 sc_parport_adapter.parport_add_handler = pi1ppc_add_handler; 273 sc_parport_adapter.parport_remove_handler = pi1ppc_remove_handler; 274 275 /* these are no-ops (does later machines have ECP/EPP support?) */ 276 sc_parport_adapter.parport_ecp_sync = pi1ppc_ecp_sync; 277 sc_parport_adapter.parport_reset_epp_timeout = 278 pi1ppc_reset_epp_timeout; 279 280 /* Initialize handler list, may be added to by grandchildren */ 281 SLIST_INIT(&(lsc->sc_handler_listhead)); 282 283 /* Initialize interrupt state */ 284 lsc->sc_irqstat = PI1PPC_IRQ_NONE; 285 lsc->sc_ecr_intr = lsc->sc_ctr_intr = lsc->sc_str_intr = 0; 286 287 /* Disable DMA/interrupts (each ppbus driver selects usage itself) */ 288 lsc->sc_use = 0; 289 290 /* Configure child of the device. */ 291 lsc->child = config_found(lsc->sc_dev, &(sc_parport_adapter), 292 pi1ppc_print); 293 294 return; 295 } 296 297 /* Soft configuration detach */ 298 int 299 pi1ppc_sc_detach(struct pi1ppc_softc *lsc, int flag) 300 { 301 device_t dev = lsc->sc_dev; 302 303 /* Detach children devices */ 304 if (config_detach(lsc->child, flag) && !(flag & DETACH_QUIET)) { 305 printf("%s not able to detach child device, ", device_xname(dev)); 306 307 if (!(flag & DETACH_FORCE)) { 308 printf("cannot detach\n"); 309 return 1; 310 } else { 311 printf("continuing (DETACH_FORCE)\n"); 312 } 313 } 314 315 if (!(flag & DETACH_QUIET)) 316 printf("%s detached", device_xname(dev)); 317 318 return 0; 319 } 320 321 /* Used by config_found() to print out device information */ 322 static int 323 pi1ppc_print(void *aux, const char *name) 324 { 325 /* Print out something on failure. */ 326 if (name != NULL) { 327 printf("%s: child devices", name); 328 return UNCONF; 329 } 330 331 return QUIET; 332 } 333 334 /* Interrupt handler for pi1ppc device: wakes up read/write functions */ 335 int 336 pi1ppcintr(void *arg) 337 { 338 /* NO INTERRUPTS YET */ 339 #if 0 340 device_t dev = arg; 341 struct pi1ppc_softc *pi1ppc = device_private(dev); 342 int claim = 1; 343 enum { NONE, READER, WRITER } wake_up = NONE; 344 int s; 345 346 s = splpi1ppc(); 347 PI1PPC_LOCK(pi1ppc); 348 349 /* Record registers' status */ 350 pi1ppc->sc_str_intr = pi1ppc_r_str(pi1ppc); 351 pi1ppc->sc_ctr_intr = pi1ppc_r_ctr(pi1ppc); 352 pi1ppc_barrier_r(pi1ppc); 353 354 /* Determine cause of interrupt and wake up top half */ 355 switch (atppc->sc_mode) { 356 case ATPPC_MODE_STD: 357 /* nAck pulsed for 5 usec, too fast to check reliably, assume */ 358 atppc->sc_irqstat = ATPPC_IRQ_nACK; 359 if (atppc->sc_outb) 360 wake_up = WRITER; 361 else 362 claim = 0; 363 break; 364 365 case ATPPC_MODE_NIBBLE: 366 case ATPPC_MODE_PS2: 367 /* nAck is set low by device and then high on ack */ 368 if (!(atppc->sc_str_intr & nACK)) { 369 claim = 0; 370 break; 371 } 372 atppc->sc_irqstat = ATPPC_IRQ_nACK; 373 if (atppc->sc_inb) 374 wake_up = READER; 375 break; 376 377 case ATPPC_MODE_ECP: 378 case ATPPC_MODE_FAST: 379 /* Confirm interrupt cause: these are not pulsed as in nAck. */ 380 if (atppc->sc_ecr_intr & ATPPC_SERVICE_INTR) { 381 if (atppc->sc_ecr_intr & ATPPC_ENABLE_DMA) 382 atppc->sc_irqstat |= ATPPC_IRQ_DMA; 383 else 384 atppc->sc_irqstat |= ATPPC_IRQ_FIFO; 385 386 /* Decide where top half will be waiting */ 387 if (atppc->sc_mode & ATPPC_MODE_ECP) { 388 if (atppc->sc_ctr_intr & PCD) { 389 if (atppc->sc_inb) 390 wake_up = READER; 391 else 392 claim = 0; 393 } else { 394 if (atppc->sc_outb) 395 wake_up = WRITER; 396 else 397 claim = 0; 398 } 399 } else { 400 if (atppc->sc_outb) 401 wake_up = WRITER; 402 else 403 claim = 0; 404 } 405 } 406 /* Determine if nFault has occurred */ 407 if ((atppc->sc_mode & ATPPC_MODE_ECP) && 408 (atppc->sc_ecr_intr & ATPPC_nFAULT_INTR) && 409 !(atppc->sc_str_intr & nFAULT)) { 410 411 /* Device is requesting the channel */ 412 atppc->sc_irqstat |= ATPPC_IRQ_nFAULT; 413 claim = 1; 414 } 415 break; 416 417 case ATPPC_MODE_EPP: 418 /* nAck pulsed for 5 usec, too fast to check reliably */ 419 atppc->sc_irqstat = ATPPC_IRQ_nACK; 420 if (atppc->sc_inb) 421 wake_up = WRITER; 422 else if (atppc->sc_outb) 423 wake_up = READER; 424 else 425 claim = 0; 426 break; 427 428 default: 429 panic("%s: chipset is in invalid mode.", device_xname(dev)); 430 } 431 432 if (claim) { 433 switch (wake_up) { 434 case NONE: 435 break; 436 437 case READER: 438 wakeup(atppc->sc_inb); 439 break; 440 441 case WRITER: 442 wakeup(atppc->sc_outb); 443 break; 444 } 445 } 446 447 PI1PPC_UNLOCK(atppc); 448 449 /* Call all of the installed handlers */ 450 if (claim) { 451 struct atppc_handler_node * callback; 452 SLIST_FOREACH(callback, &(atppc->sc_handler_listhead), 453 entries) { 454 (*callback->func)(callback->arg); 455 } 456 } 457 458 splx(s); 459 460 return claim; 461 #else 462 return 0; /* NO INTERRUPTS YET */ 463 #endif 464 } 465 466 /* Functions which support ppbus interface */ 467 468 static void 469 pi1ppc_reset_epp_timeout(device_t dev) 470 { 471 return; 472 } 473 474 /* Read from pi1ppc device: returns 0 on success. */ 475 static int 476 pi1ppc_read(device_t dev, char *buf, int len, int ioflag, 477 size_t *cnt) 478 { 479 struct pi1ppc_softc *pi1ppc = device_private(dev); 480 int error = 0; 481 int s; 482 483 s = splpi1ppc(); 484 PI1PPC_LOCK(pi1ppc); 485 486 *cnt = 0; 487 488 /* Initialize buffer */ 489 pi1ppc->sc_inb = pi1ppc->sc_inbstart = buf; 490 pi1ppc->sc_inb_nbytes = len; 491 492 /* Initialize device input error state for new operation */ 493 pi1ppc->sc_inerr = 0; 494 495 /* Call appropriate function to read bytes */ 496 switch(pi1ppc->sc_mode) { 497 case PI1PPC_MODE_STD: 498 error = ENODEV; 499 break; 500 501 case PI1PPC_MODE_NIBBLE: 502 pi1ppc_nibble_read(pi1ppc); 503 break; 504 505 case PI1PPC_MODE_PS2: 506 pi1ppc_byte_read(pi1ppc); 507 break; 508 509 default: 510 panic("%s(%s): chipset in invalid mode.\n", __func__, 511 device_xname(dev)); 512 } 513 514 /* Update counter*/ 515 *cnt = (pi1ppc->sc_inbstart - pi1ppc->sc_inb); 516 517 /* Reset buffer */ 518 pi1ppc->sc_inb = pi1ppc->sc_inbstart = NULL; 519 pi1ppc->sc_inb_nbytes = 0; 520 521 if (!(error)) 522 error = pi1ppc->sc_inerr; 523 524 PI1PPC_UNLOCK(pi1ppc); 525 splx(s); 526 527 return (error); 528 } 529 530 /* Write to pi1ppc device: returns 0 on success. */ 531 static int 532 pi1ppc_write(device_t dev, char *buf, int len, int ioflag, size_t *cnt) 533 { 534 struct pi1ppc_softc * const pi1ppc = device_private(dev); 535 int error = 0; 536 int s; 537 538 *cnt = 0; 539 540 s = splpi1ppc(); 541 PI1PPC_LOCK(pi1ppc); 542 543 /* Set up line buffer */ 544 pi1ppc->sc_outb = pi1ppc->sc_outbstart = buf; 545 pi1ppc->sc_outb_nbytes = len; 546 547 /* Initialize device output error state for new operation */ 548 pi1ppc->sc_outerr = 0; 549 550 /* Call appropriate function to write bytes */ 551 switch (pi1ppc->sc_mode) { 552 case PI1PPC_MODE_STD: 553 pi1ppc_std_write(pi1ppc); 554 break; 555 556 case PI1PPC_MODE_NIBBLE: 557 case PI1PPC_MODE_PS2: 558 error = ENODEV; 559 break; 560 561 default: 562 panic("%s(%s): chipset in invalid mode.\n", __func__, 563 device_xname(dev)); 564 } 565 566 /* Update counter*/ 567 *cnt = (pi1ppc->sc_outbstart - pi1ppc->sc_outb); 568 569 /* Reset output buffer */ 570 pi1ppc->sc_outb = pi1ppc->sc_outbstart = NULL; 571 pi1ppc->sc_outb_nbytes = 0; 572 573 if (!(error)) 574 error = pi1ppc->sc_outerr; 575 576 PI1PPC_UNLOCK(pi1ppc); 577 splx(s); 578 579 return (error); 580 } 581 582 /* 583 * Set mode of chipset to mode argument. Modes not supported are ignored. If 584 * multiple modes are flagged, the mode is not changed. Modes are those 585 * defined for ppbus_softc.sc_mode in ppbus_conf.h. Only ECP-capable chipsets 586 * can change their mode of operation. However, ALL operation modes support 587 * centronics mode and nibble mode. Modes determine both hardware AND software 588 * behaviour. 589 * NOTE: the mode for ECP should only be changed when the channel is in 590 * forward idle mode. This function does not make sure FIFO's have flushed or 591 * any consistency checks. 592 */ 593 static int 594 pi1ppc_setmode(device_t dev, int mode) 595 { 596 struct pi1ppc_softc *pi1ppc = device_private(dev); 597 uint8_t ecr; 598 uint8_t chipset_mode; 599 int s; 600 int rval = 0; 601 602 s = splpi1ppc(); 603 PI1PPC_LOCK(pi1ppc); 604 605 switch (mode) { 606 case PPBUS_PS2: 607 /* Indy has this, other PI1 machines do too? */ 608 chipset_mode = PI1PPC_MODE_PS2; 609 break; 610 611 case PPBUS_NIBBLE: 612 /* Set nibble mode (virtual) */ 613 chipset_mode = PI1PPC_MODE_NIBBLE; 614 break; 615 616 case PPBUS_COMPATIBLE: 617 chipset_mode = PI1PPC_MODE_STD; 618 break; 619 620 case PPBUS_ECP: 621 case PPBUS_EPP: 622 rval = ENODEV; 623 goto end; 624 625 default: 626 PI1PPC_DPRINTF(("%s(%s): invalid mode passed as " 627 "argument.\n", __func__, device_xname(dev))); 628 rval = ENODEV; 629 goto end; 630 } 631 632 pi1ppc->sc_mode = chipset_mode; 633 if (chipset_mode == PI1PPC_MODE_PS2) { 634 /* Set direction bit to reverse */ 635 ecr = pi1ppc_r_ctr(pi1ppc); 636 pi1ppc_barrier_r(pi1ppc); 637 ecr |= PCD; /* data is INPUT */ 638 pi1ppc_w_ctr(pi1ppc, ecr); 639 pi1ppc_barrier_w(pi1ppc); 640 } 641 642 end: 643 PI1PPC_UNLOCK(pi1ppc); 644 splx(s); 645 646 return rval; 647 } 648 649 /* Get the current mode of chipset */ 650 static int 651 pi1ppc_getmode(device_t dev) 652 { 653 struct pi1ppc_softc *pi1ppc = device_private(dev); 654 int mode; 655 int s; 656 657 s = splpi1ppc(); 658 PI1PPC_LOCK(pi1ppc); 659 660 /* The chipset can only be in one mode at a time logically */ 661 switch (pi1ppc->sc_mode) { 662 case PI1PPC_MODE_PS2: 663 mode = PPBUS_PS2; 664 break; 665 666 case PI1PPC_MODE_STD: 667 mode = PPBUS_COMPATIBLE; 668 break; 669 670 case PI1PPC_MODE_NIBBLE: 671 mode = PPBUS_NIBBLE; 672 break; 673 674 default: 675 panic("%s(%s): device is in invalid mode!", __func__, 676 device_xname(dev)); 677 break; 678 } 679 680 PI1PPC_UNLOCK(pi1ppc); 681 splx(s); 682 683 return mode; 684 } 685 686 687 /* Wait for FIFO buffer to empty for ECP-capable chipset */ 688 static void 689 pi1ppc_ecp_sync(device_t dev) 690 { 691 return; 692 } 693 694 /* Execute a microsequence to handle fast I/O operations. */ 695 696 /* microsequence registers are equivalent to PC-like port registers */ 697 /* therefore, translate bit positions & polarities */ 698 699 /* Bit 4 of ctl_reg_int_en is used to emulate the PC's int enable 700 bit. Without it, lpt doesn't like the port. 701 */ 702 static uint8_t ctl_reg_int_en = 0; 703 704 static uint8_t 705 r_reg(int reg, struct pi1ppc_softc *pi1ppc) 706 { 707 int val = 0; 708 709 /* if we read the status reg, make it look like the PC */ 710 if(reg == AT_STAT_REG) { 711 val = bus_space_read_4((pi1ppc)->sc_iot, 712 (pi1ppc)->sc_ioh, IOC_PLP_STAT); 713 val &= 0xff; 714 715 /* invert /BUSY */ 716 val ^= 0x80; 717 718 /* bit 2 reads as '1' on Indy (why?) */ 719 val &= 0xf8; 720 721 return val; 722 } 723 724 /* if we read the ctl reg, make it look like the PC */ 725 if(reg == AT_CTL_REG) { 726 val = bus_space_read_4((pi1ppc)->sc_iot, 727 (pi1ppc)->sc_ioh, IOC_PLP_CTL); 728 val &= 0xff; 729 730 /* get the dir bit in the right place */ 731 val = ((val >> 1) & 0x20) | (val & 0x0f); 732 733 /* invert /SEL, /AUTOFD, and /STB */ 734 val ^= 0x0b; 735 736 /* emulate the PC's int enable ctl bit */ 737 val |= (ctl_reg_int_en & 0x10); 738 739 return val; 740 } 741 742 if(reg == AT_DATA_REG) { 743 val = bus_space_read_4((pi1ppc)->sc_iot, 744 (pi1ppc)->sc_ioh, IOC_PLP_DATA); 745 val &= 0xff; 746 747 return val; 748 } 749 750 return 0; 751 } 752 753 static void 754 w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte) 755 { 756 /* don't try to write to the status reg */ 757 758 /* if we are writing the ctl reg, adjust PC style -> IOC style */ 759 if(reg == AT_CTL_REG) { 760 /* preserve pc-style int enable bit */ 761 ctl_reg_int_en = (byte & 0x10); 762 763 /* get the dir bit in the right place */ 764 byte = ((byte << 1) & 0x40) | (byte & 0x0f); 765 766 /* invert /SEL, /AUTOFD, and /STB */ 767 byte ^= 0x0b; 768 769 bus_space_write_4((pi1ppc)->sc_iot, 770 (pi1ppc)->sc_ioh, IOC_PLP_CTL, byte); 771 } 772 773 if(reg == AT_DATA_REG) { 774 bus_space_write_4((pi1ppc)->sc_iot, 775 (pi1ppc)->sc_ioh, IOC_PLP_DATA, byte); 776 } 777 } 778 779 static int 780 pi1ppc_exec_microseq(device_t dev, struct ppbus_microseq **p_msq) 781 { 782 struct pi1ppc_softc *pi1ppc = device_private(dev); 783 struct ppbus_microseq *mi = *p_msq; 784 char cc, *p; 785 int i, iter, len; 786 int error; 787 int s; 788 register int reg; 789 register unsigned char mask; 790 register int accum = 0; 791 register char *ptr = NULL; 792 struct ppbus_microseq *stack = NULL; 793 794 s = splpi1ppc(); 795 PI1PPC_LOCK(pi1ppc); 796 797 /* Loop until microsequence execution finishes (ending op code) */ 798 for (;;) { 799 switch (mi->opcode) { 800 case MS_OP_RSET: 801 cc = r_reg(mi->arg[0].i, pi1ppc); 802 pi1ppc_barrier_r(pi1ppc); 803 cc &= (char)mi->arg[2].i; /* clear mask */ 804 cc |= (char)mi->arg[1].i; /* assert mask */ 805 w_reg(mi->arg[0].i, pi1ppc, cc); 806 pi1ppc_barrier_w(pi1ppc); 807 mi++; 808 break; 809 810 case MS_OP_RASSERT_P: 811 reg = mi->arg[1].i; 812 ptr = pi1ppc->sc_ptr; 813 814 if ((len = mi->arg[0].i) == MS_ACCUM) { 815 accum = pi1ppc->sc_accum; 816 for (; accum; accum--) { 817 w_reg(reg, pi1ppc, *ptr++); 818 pi1ppc_barrier_w(pi1ppc); 819 } 820 pi1ppc->sc_accum = accum; 821 } else { 822 for (i = 0; i < len; i++) { 823 w_reg(reg, pi1ppc, *ptr++); 824 pi1ppc_barrier_w(pi1ppc); 825 } 826 } 827 828 pi1ppc->sc_ptr = ptr; 829 mi++; 830 break; 831 832 case MS_OP_RFETCH_P: 833 reg = mi->arg[1].i; 834 mask = (char)mi->arg[2].i; 835 ptr = pi1ppc->sc_ptr; 836 837 if ((len = mi->arg[0].i) == MS_ACCUM) { 838 accum = pi1ppc->sc_accum; 839 for (; accum; accum--) { 840 *ptr++ = r_reg(reg, pi1ppc) & mask; 841 pi1ppc_barrier_r(pi1ppc); 842 } 843 pi1ppc->sc_accum = accum; 844 } else { 845 for (i = 0; i < len; i++) { 846 *ptr++ = r_reg(reg, pi1ppc) & mask; 847 pi1ppc_barrier_r(pi1ppc); 848 } 849 } 850 851 pi1ppc->sc_ptr = ptr; 852 mi++; 853 break; 854 855 case MS_OP_RFETCH: 856 *((char *)mi->arg[2].p) = r_reg(mi->arg[0].i, pi1ppc) & 857 (char)mi->arg[1].i; 858 pi1ppc_barrier_r(pi1ppc); 859 mi++; 860 break; 861 862 case MS_OP_RASSERT: 863 case MS_OP_DELAY: 864 /* let's suppose the next instr. is the same */ 865 do { 866 for (;mi->opcode == MS_OP_RASSERT; mi++) { 867 w_reg(mi->arg[0].i, pi1ppc, 868 (char)mi->arg[1].i); 869 pi1ppc_barrier_w(pi1ppc); 870 } 871 872 for (;mi->opcode == MS_OP_DELAY; mi++) { 873 delay(mi->arg[0].i); 874 } 875 } while (mi->opcode == MS_OP_RASSERT); 876 break; 877 878 case MS_OP_ADELAY: 879 if (mi->arg[0].i) { 880 tsleep(pi1ppc, PPBUSPRI, "pi1ppcdelay", 881 mi->arg[0].i * (hz/1000)); 882 } 883 mi++; 884 break; 885 886 case MS_OP_TRIG: 887 reg = mi->arg[0].i; 888 iter = mi->arg[1].i; 889 p = (char *)mi->arg[2].p; 890 891 /* XXX delay limited to 255 us */ 892 for (i = 0; i < iter; i++) { 893 w_reg(reg, pi1ppc, *p++); 894 pi1ppc_barrier_w(pi1ppc); 895 delay((unsigned char)*p++); 896 } 897 898 mi++; 899 break; 900 901 case MS_OP_SET: 902 pi1ppc->sc_accum = mi->arg[0].i; 903 mi++; 904 break; 905 906 case MS_OP_DBRA: 907 if (--pi1ppc->sc_accum > 0) { 908 mi += mi->arg[0].i; 909 } 910 911 mi++; 912 break; 913 914 case MS_OP_BRSET: 915 cc = pi1ppc_r_str(pi1ppc); 916 pi1ppc_barrier_r(pi1ppc); 917 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) { 918 mi += mi->arg[1].i; 919 } 920 mi++; 921 break; 922 923 case MS_OP_BRCLEAR: 924 cc = pi1ppc_r_str(pi1ppc); 925 pi1ppc_barrier_r(pi1ppc); 926 if ((cc & (char)mi->arg[0].i) == 0) { 927 mi += mi->arg[1].i; 928 } 929 mi++; 930 break; 931 932 case MS_OP_BRSTAT: 933 cc = pi1ppc_r_str(pi1ppc); 934 pi1ppc_barrier_r(pi1ppc); 935 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 936 (char)mi->arg[0].i) { 937 mi += mi->arg[2].i; 938 } 939 mi++; 940 break; 941 942 case MS_OP_C_CALL: 943 /* 944 * If the C call returns !0 then end the microseq. 945 * The current state of ptr is passed to the C function 946 */ 947 if ((error = mi->arg[0].f(mi->arg[1].p, 948 pi1ppc->sc_ptr))) { 949 PI1PPC_UNLOCK(pi1ppc); 950 splx(s); 951 return (error); 952 } 953 mi++; 954 break; 955 956 case MS_OP_PTR: 957 pi1ppc->sc_ptr = (char *)mi->arg[0].p; 958 mi++; 959 break; 960 961 case MS_OP_CALL: 962 if (stack) { 963 panic("%s - %s: too many calls", device_xname(dev), 964 __func__); 965 } 966 967 if (mi->arg[0].p) { 968 /* store state of the actual microsequence */ 969 stack = mi; 970 971 /* jump to the new microsequence */ 972 mi = (struct ppbus_microseq *)mi->arg[0].p; 973 } else { 974 mi++; 975 } 976 break; 977 978 case MS_OP_SUBRET: 979 /* retrieve microseq and pc state before the call */ 980 mi = stack; 981 982 /* reset the stack */ 983 stack = 0; 984 985 /* XXX return code */ 986 987 mi++; 988 break; 989 990 case MS_OP_PUT: 991 case MS_OP_GET: 992 case MS_OP_RET: 993 /* 994 * Can't return to pi1ppc level during the execution 995 * of a submicrosequence. 996 */ 997 if (stack) { 998 panic("%s: cannot return to pi1ppc level", 999 __func__); 1000 } 1001 /* update pc for pi1ppc level of execution */ 1002 *p_msq = mi; 1003 1004 PI1PPC_UNLOCK(pi1ppc); 1005 splx(s); 1006 return (0); 1007 break; 1008 1009 default: 1010 panic("%s: unknown microsequence " 1011 "opcode 0x%x", __func__, mi->opcode); 1012 break; 1013 } 1014 } 1015 1016 /* Should not be reached! */ 1017 #ifdef PI1PPC_DEBUG 1018 panic("%s: unexpected code reached!\n", __func__); 1019 #endif 1020 } 1021 1022 /* General I/O routine */ 1023 static uint8_t 1024 pi1ppc_io(device_t dev, int iop, u_char *addr, int cnt, u_char byte) 1025 { 1026 struct pi1ppc_softc *pi1ppc = device_private(dev); 1027 uint8_t val = 0; 1028 int s; 1029 1030 s = splpi1ppc(); 1031 PI1PPC_LOCK(pi1ppc); 1032 1033 switch (iop) { 1034 case PPBUS_RDTR: 1035 val = r_reg(AT_DATA_REG, pi1ppc); 1036 break; 1037 case PPBUS_RSTR: 1038 val = r_reg(AT_STAT_REG, pi1ppc); 1039 break; 1040 case PPBUS_RCTR: 1041 val = r_reg(AT_CTL_REG, pi1ppc); 1042 break; 1043 case PPBUS_WDTR: 1044 w_reg(AT_DATA_REG, pi1ppc, byte); 1045 break; 1046 case PPBUS_WSTR: 1047 /* writing to the status register is weird */ 1048 break; 1049 case PPBUS_WCTR: 1050 w_reg(AT_CTL_REG, pi1ppc, byte); 1051 break; 1052 default: 1053 panic("%s(%s): unknown I/O operation", device_xname(dev), 1054 __func__); 1055 break; 1056 } 1057 1058 pi1ppc_barrier(pi1ppc); 1059 1060 PI1PPC_UNLOCK(pi1ppc); 1061 splx(s); 1062 1063 return val; 1064 } 1065 1066 /* Read "instance variables" of pi1ppc device */ 1067 static int 1068 pi1ppc_read_ivar(device_t dev, int index, unsigned int *val) 1069 { 1070 struct pi1ppc_softc *pi1ppc = device_private(dev); 1071 int rval = 0; 1072 int s; 1073 1074 s = splpi1ppc(); 1075 PI1PPC_LOCK(pi1ppc); 1076 1077 switch(index) { 1078 case PPBUS_IVAR_INTR: 1079 *val = ((pi1ppc->sc_use & PI1PPC_USE_INTR) != 0); 1080 break; 1081 1082 case PPBUS_IVAR_DMA: 1083 *val = ((pi1ppc->sc_use & PI1PPC_USE_DMA) != 0); 1084 break; 1085 1086 default: 1087 rval = ENODEV; 1088 } 1089 1090 PI1PPC_UNLOCK(pi1ppc); 1091 splx(s); 1092 1093 return rval; 1094 } 1095 1096 /* Write "instance varaibles" of pi1ppc device */ 1097 static int 1098 pi1ppc_write_ivar(device_t dev, int index, unsigned int *val) 1099 { 1100 struct pi1ppc_softc *pi1ppc = device_private(dev); 1101 int rval = 0; 1102 int s; 1103 1104 s = splpi1ppc(); 1105 PI1PPC_LOCK(pi1ppc); 1106 1107 switch(index) { 1108 case PPBUS_IVAR_INTR: 1109 if (*val == 0) 1110 pi1ppc->sc_use &= ~PI1PPC_USE_INTR; 1111 else if (pi1ppc->sc_has & PI1PPC_HAS_INTR) 1112 pi1ppc->sc_use |= PI1PPC_USE_INTR; 1113 else 1114 rval = ENODEV; 1115 break; 1116 1117 case PPBUS_IVAR_DMA: 1118 if (*val == 0) 1119 pi1ppc->sc_use &= ~PI1PPC_USE_DMA; 1120 else if (pi1ppc->sc_has & PI1PPC_HAS_DMA) 1121 pi1ppc->sc_use |= PI1PPC_USE_DMA; 1122 else 1123 rval = ENODEV; 1124 break; 1125 1126 default: 1127 rval = ENODEV; 1128 } 1129 1130 PI1PPC_UNLOCK(pi1ppc); 1131 splx(s); 1132 1133 return rval; 1134 } 1135 1136 /* Add a handler routine to be called by the interrupt handler */ 1137 static int 1138 pi1ppc_add_handler(device_t dev, void (*handler)(void *), void *arg) 1139 { 1140 struct pi1ppc_softc *pi1ppc = device_private(dev); 1141 struct pi1ppc_handler_node *callback; 1142 int rval = 0; 1143 int s; 1144 1145 s = splpi1ppc(); 1146 PI1PPC_LOCK(pi1ppc); 1147 1148 if (handler == NULL) { 1149 PI1PPC_DPRINTF(("%s(%s): attempt to register NULL handler.\n", 1150 __func__, device_xname(dev))); 1151 rval = EINVAL; 1152 } else { 1153 callback = malloc(sizeof(struct pi1ppc_handler_node), M_DEVBUF, 1154 M_NOWAIT); 1155 if (callback) { 1156 callback->func = handler; 1157 callback->arg = arg; 1158 SLIST_INSERT_HEAD(&(pi1ppc->sc_handler_listhead), 1159 callback, entries); 1160 } else { 1161 rval = ENOMEM; 1162 } 1163 } 1164 1165 PI1PPC_UNLOCK(pi1ppc); 1166 splx(s); 1167 1168 return rval; 1169 } 1170 1171 /* Remove a handler added by pi1ppc_add_handler() */ 1172 static int 1173 pi1ppc_remove_handler(device_t dev, void (*handler)(void *)) 1174 { 1175 struct pi1ppc_softc *pi1ppc = device_private(dev); 1176 struct pi1ppc_handler_node *callback; 1177 int rval = EINVAL; 1178 int s; 1179 1180 s = splpi1ppc(); 1181 PI1PPC_LOCK(pi1ppc); 1182 1183 if (SLIST_EMPTY(&(pi1ppc->sc_handler_listhead))) 1184 panic("%s(%s): attempt to remove handler from empty list.\n", 1185 __func__, device_xname(dev)); 1186 1187 /* Search list for handler */ 1188 SLIST_FOREACH(callback, &(pi1ppc->sc_handler_listhead), entries) { 1189 if (callback->func == handler) { 1190 SLIST_REMOVE(&(pi1ppc->sc_handler_listhead), callback, 1191 pi1ppc_handler_node, entries); 1192 free(callback, M_DEVBUF); 1193 rval = 0; 1194 break; 1195 } 1196 } 1197 1198 PI1PPC_UNLOCK(pi1ppc); 1199 splx(s); 1200 1201 return rval; 1202 } 1203 1204 /* Utility functions */ 1205 1206 /* 1207 * Functions that read bytes from port into buffer: called from interrupt 1208 * handler depending on current chipset mode and cause of interrupt. Return 1209 * value: number of bytes moved. 1210 */ 1211 1212 /* note: BUSY is inverted in the PC world, but not on Indy, but the r_reg() 1213 and w_reg() functions make the Indy look like the PC. */ 1214 1215 /* Only the lower 4 bits of the final value are valid */ 1216 #define nibble2char(s) ((((s) & ~nACK) >> 3) | (~(s) & nBUSY) >> 4) 1217 1218 1219 /* Read bytes in nibble mode */ 1220 static void 1221 pi1ppc_nibble_read(struct pi1ppc_softc *pi1ppc) 1222 { 1223 int i; 1224 uint8_t nibble[2]; 1225 uint8_t ctr; 1226 uint8_t str; 1227 1228 /* Enable interrupts if needed */ 1229 if (pi1ppc->sc_use & PI1PPC_USE_INTR) { 1230 1231 /* XXX JOE - need code to enable interrupts 1232 --> emulate PC behavior in r_reg/w_reg 1233 */ 1234 #if 0 1235 ctr = pi1ppc_r_ctr(pi1ppc); 1236 pi1ppc_barrier_r(ioppc); 1237 if (!(ctr & IRQENABLE)) { 1238 ctr |= IRQENABLE; 1239 pi1ppc_w_ctr(pi1ppc, ctr); 1240 pi1ppc_barrier_w(pi1ppc); 1241 } 1242 #endif 1243 } 1244 1245 while (pi1ppc->sc_inbstart < (pi1ppc->sc_inb + pi1ppc->sc_inb_nbytes)) { 1246 /* Check if device has data to send in idle phase */ 1247 str = pi1ppc_r_str(pi1ppc); 1248 pi1ppc_barrier_r(pi1ppc); 1249 if (str & nDATAVAIL) { 1250 return; 1251 } 1252 1253 /* Nibble-mode handshake transfer */ 1254 for (i = 0; i < 2; i++) { 1255 /* Event 7 - ready to take data (HOSTBUSY low) */ 1256 ctr = pi1ppc_r_ctr(pi1ppc); 1257 pi1ppc_barrier_r(pi1ppc); 1258 ctr |= HOSTBUSY; 1259 pi1ppc_w_ctr(pi1ppc, ctr); 1260 pi1ppc_barrier_w(pi1ppc); 1261 1262 /* Event 8 - peripheral writes the first nibble */ 1263 1264 /* Event 9 - peripheral set nAck low */ 1265 pi1ppc->sc_inerr = pi1ppc_poll_str(pi1ppc, 0, PTRCLK); 1266 if (pi1ppc->sc_inerr) 1267 return; 1268 1269 /* read nibble */ 1270 nibble[i] = pi1ppc_r_str(pi1ppc); 1271 1272 /* Event 10 - ack, nibble received */ 1273 ctr &= ~HOSTBUSY; 1274 pi1ppc_w_ctr(pi1ppc, ctr); 1275 1276 /* Event 11 - wait ack from peripherial */ 1277 if (pi1ppc->sc_use & PI1PPC_USE_INTR) 1278 pi1ppc->sc_inerr = pi1ppc_wait_interrupt(pi1ppc, 1279 pi1ppc->sc_inb, PI1PPC_IRQ_nACK); 1280 else 1281 pi1ppc->sc_inerr = pi1ppc_poll_str(pi1ppc, PTRCLK, 1282 PTRCLK); 1283 if (pi1ppc->sc_inerr) 1284 return; 1285 } 1286 1287 /* Store byte transfered */ 1288 *(pi1ppc->sc_inbstart) = ((nibble2char(nibble[1]) << 4) & 0xf0) | 1289 (nibble2char(nibble[0]) & 0x0f); 1290 pi1ppc->sc_inbstart++; 1291 } 1292 } 1293 1294 /* Read bytes in bidirectional mode */ 1295 static void 1296 pi1ppc_byte_read(struct pi1ppc_softc * const pi1ppc) 1297 { 1298 uint8_t ctr; 1299 uint8_t str; 1300 1301 /* Check direction bit */ 1302 ctr = pi1ppc_r_ctr(pi1ppc); 1303 pi1ppc_barrier_r(pi1ppc); 1304 if (!(ctr & PCD)) { 1305 PI1PPC_DPRINTF(("%s: byte-mode read attempted without direction " 1306 "bit set.", device_xname(pi1ppc->sc_dev))); 1307 pi1ppc->sc_inerr = ENODEV; 1308 return; 1309 } 1310 /* Enable interrupts if needed */ 1311 1312 /* XXX JOE - need code to enable interrupts */ 1313 #if 0 1314 if (pi1ppc->sc_use & PI1PPC_USE_INTR) { 1315 if (!(ctr & IRQENABLE)) { 1316 ctr |= IRQENABLE; 1317 pi1ppc_w_ctr(pi1ppc, ctr); 1318 pi1ppc_barrier_w(pi1ppc); 1319 } 1320 } 1321 #endif 1322 1323 /* Byte-mode handshake transfer */ 1324 while (pi1ppc->sc_inbstart < (pi1ppc->sc_inb + pi1ppc->sc_inb_nbytes)) { 1325 /* Check if device has data to send */ 1326 str = pi1ppc_r_str(pi1ppc); 1327 pi1ppc_barrier_r(pi1ppc); 1328 if (str & nDATAVAIL) { 1329 return; 1330 } 1331 1332 /* Event 7 - ready to take data (nAUTO low) */ 1333 ctr |= HOSTBUSY; 1334 pi1ppc_w_ctr(pi1ppc, ctr); 1335 pi1ppc_barrier_w(pi1ppc); 1336 1337 /* Event 9 - peripheral set nAck low */ 1338 pi1ppc->sc_inerr = pi1ppc_poll_str(pi1ppc, 0, PTRCLK); 1339 if (pi1ppc->sc_inerr) 1340 return; 1341 1342 /* Store byte transfered */ 1343 *(pi1ppc->sc_inbstart) = pi1ppc_r_dtr(pi1ppc); 1344 pi1ppc_barrier_r(pi1ppc); 1345 1346 /* Event 10 - data received, can't accept more */ 1347 ctr &= ~HOSTBUSY; 1348 pi1ppc_w_ctr(pi1ppc, ctr); 1349 pi1ppc_barrier_w(pi1ppc); 1350 1351 /* Event 11 - peripheral ack */ 1352 if (pi1ppc->sc_use & PI1PPC_USE_INTR) 1353 pi1ppc->sc_inerr = pi1ppc_wait_interrupt(pi1ppc, 1354 pi1ppc->sc_inb, PI1PPC_IRQ_nACK); 1355 else 1356 pi1ppc->sc_inerr = pi1ppc_poll_str(pi1ppc, PTRCLK, PTRCLK); 1357 if (pi1ppc->sc_inerr) 1358 return; 1359 1360 /* Event 16 - strobe */ 1361 str |= HOSTCLK; 1362 pi1ppc_w_str(pi1ppc, str); 1363 pi1ppc_barrier_w(pi1ppc); 1364 DELAY(1); 1365 str &= ~HOSTCLK; 1366 pi1ppc_w_str(pi1ppc, str); 1367 pi1ppc_barrier_w(pi1ppc); 1368 1369 /* Update counter */ 1370 pi1ppc->sc_inbstart++; 1371 } 1372 } 1373 1374 /* 1375 * Functions that write bytes to port from buffer: called from pi1ppc_write() 1376 * function depending on current chipset mode. Returns number of bytes moved. 1377 */ 1378 1379 static void 1380 pi1ppc_set_intr_mask(struct pi1ppc_softc * const pi1ppc, uint8_t mask) 1381 { 1382 /* invert valid bits (0 = enabled) */ 1383 mask = ~mask; 1384 mask &= 0xfc; 1385 1386 bus_space_write_4((pi1ppc)->sc_iot, (pi1ppc)->sc_ioh, IOC_PLP_INTMASK, mask); 1387 pi1ppc_barrier_w(pi1ppc); 1388 } 1389 1390 1391 #ifdef USE_INDY_ACK_HACK 1392 static uint8_t 1393 pi1ppc_get_intr_mask(struct pi1ppc_softc * const pi1ppc) 1394 { 1395 int val; 1396 val = bus_space_read_4((pi1ppc)->sc_iot, (pi1ppc)->sc_ioh, IOC_PLP_INTMASK); 1397 pi1ppc_barrier_r(pi1ppc); 1398 1399 /* invert (0 = enabled) */ 1400 val = ~val; 1401 1402 return (val & 0xfc); 1403 } 1404 #endif 1405 1406 static uint8_t 1407 pi1ppc_get_intr_stat(struct pi1ppc_softc * const pi1ppc) 1408 { 1409 int val; 1410 val = bus_space_read_4((pi1ppc)->sc_iot, (pi1ppc)->sc_ioh, IOC_PLP_INTSTAT); 1411 pi1ppc_barrier_r(pi1ppc); 1412 1413 return (val & 0xfc); 1414 } 1415 1416 /* Write bytes in std/bidirectional mode */ 1417 static void 1418 pi1ppc_std_write(struct pi1ppc_softc * const pi1ppc) 1419 { 1420 unsigned char ctr; 1421 1422 ctr = pi1ppc_r_ctr(pi1ppc); 1423 pi1ppc_barrier_r(pi1ppc); 1424 1425 /* Ensure that the data lines are in OUTPUT mode */ 1426 ctr &= ~PCD; 1427 pi1ppc_w_ctr(pi1ppc, ctr); 1428 pi1ppc_barrier_w(pi1ppc); 1429 1430 /* XXX JOE - need code to enable interrupts */ 1431 #if 0 1432 /* Enable interrupts if needed */ 1433 if (pi1ppc->sc_use & PI1PPC_USE_INTR) { 1434 if (!(ctr & IRQENABLE)) { 1435 ctr |= IRQENABLE; 1436 pi1ppc_w_ctr(pi1ppc, ctr); 1437 pi1ppc_barrier_w(pi1ppc); 1438 } 1439 } 1440 #endif 1441 1442 while (pi1ppc->sc_outbstart < (pi1ppc->sc_outb + pi1ppc->sc_outb_nbytes)) { 1443 1444 /* Wait for peripheral to become ready for MAXBUSYWAIT */ 1445 pi1ppc->sc_outerr = pi1ppc_poll_str(pi1ppc, SPP_READY, SPP_MASK); 1446 if (pi1ppc->sc_outerr) { 1447 printf("pi1ppc: timeout waiting for peripheral to become ready\n"); 1448 return; 1449 } 1450 1451 /* Put data in data register */ 1452 pi1ppc_w_dtr(pi1ppc, *(pi1ppc->sc_outbstart)); 1453 pi1ppc_barrier_w(pi1ppc); 1454 DELAY(1); 1455 1456 /* If no intr, prepare to catch the rising edge of nACK */ 1457 if (!(pi1ppc->sc_use & PI1PPC_USE_INTR)) { 1458 pi1ppc_get_intr_stat(pi1ppc); /* clear any pending intr */ 1459 pi1ppc_set_intr_mask(pi1ppc, PI1_PLP_ACK_INTR); 1460 } 1461 1462 /* Pulse strobe to indicate valid data on lines */ 1463 ctr |= STROBE; 1464 pi1ppc_w_ctr(pi1ppc, ctr); 1465 pi1ppc_barrier_w(pi1ppc); 1466 DELAY(1); 1467 ctr &= ~STROBE; 1468 pi1ppc_w_ctr(pi1ppc, ctr); 1469 pi1ppc_barrier_w(pi1ppc); 1470 1471 /* Wait for nACK for MAXBUSYWAIT */ 1472 if (pi1ppc->sc_use & PI1PPC_USE_INTR) { 1473 pi1ppc->sc_outerr = pi1ppc_wait_interrupt(pi1ppc, 1474 pi1ppc->sc_outb, PI1PPC_IRQ_nACK); 1475 if (pi1ppc->sc_outerr) 1476 return; 1477 } else { 1478 /* Try to catch the pulsed acknowledgement */ 1479 pi1ppc->sc_outerr = pi1ppc_poll_interrupt_stat(pi1ppc, 1480 PI1_PLP_ACK_INTR); 1481 1482 if (pi1ppc->sc_outerr) { 1483 printf("pi1ppc: timeout waiting for ACK: %02x\n",pi1ppc_r_str(pi1ppc)); 1484 return; 1485 } 1486 } 1487 1488 /* Update buffer position, byte count and counter */ 1489 pi1ppc->sc_outbstart++; 1490 } 1491 } 1492 1493 1494 /* 1495 * Poll status register using mask and status for MAXBUSYWAIT. 1496 * Returns 0 if device ready, error value otherwise. 1497 */ 1498 static int 1499 pi1ppc_poll_str(struct pi1ppc_softc * const pi1ppc, const uint8_t status, 1500 const uint8_t mask) 1501 { 1502 unsigned int timecount; 1503 uint8_t str; 1504 int error = EIO; 1505 1506 /* Wait for str to have status for MAXBUSYWAIT */ 1507 for (timecount = 0; timecount < ((MAXBUSYWAIT/hz)*1000000); 1508 timecount++) { 1509 1510 str = pi1ppc_r_str(pi1ppc); 1511 pi1ppc_barrier_r(pi1ppc); 1512 if ((str & mask) == status) { 1513 error = 0; 1514 break; 1515 } 1516 DELAY(1); 1517 } 1518 1519 return error; 1520 } 1521 1522 /* Wait for interrupt for MAXBUSYWAIT: returns 0 if acknowledge received. */ 1523 static int 1524 pi1ppc_wait_interrupt(struct pi1ppc_softc * const pi1ppc, const void *where, 1525 const uint8_t irqstat) 1526 { 1527 int error = EIO; 1528 1529 pi1ppc->sc_irqstat &= ~irqstat; 1530 1531 /* Wait for interrupt for MAXBUSYWAIT */ 1532 error = ltsleep(where, PPBUSPRI | PCATCH, __func__, MAXBUSYWAIT, 1533 PI1PPC_SC_LOCK(pi1ppc)); 1534 1535 if (!(error) && (pi1ppc->sc_irqstat & irqstat)) { 1536 pi1ppc->sc_irqstat &= ~irqstat; 1537 error = 0; 1538 } 1539 1540 return error; 1541 } 1542 1543 /* 1544 INDY ACK HACK DESCRIPTION 1545 1546 There appears to be a bug in the Indy's PI1 hardware - it sometimes 1547 *misses* the rising edge of /ACK. Ugh! 1548 1549 (Also, unlike the other status bits, /ACK doesn't generate an 1550 interrupt on its falling edge.) 1551 1552 So, we do something kind of skanky here. We use a shorter timeout, 1553 and, if we timeout, we first check BUSY. If BUSY is high, we go 1554 back to waiting for /ACK (because maybe this really is just a slow 1555 peripheral). 1556 1557 If it's a normal printer, it will raise BUSY from when it sees our 1558 /STROBE until it raises its /ACK: 1559 _____ _____________________ 1560 /STB \_/ 1561 ________________ __________ 1562 /ACK \_/ 1563 ___________ 1564 BUSY ______/ \__________ 1565 1566 So, if we time out and see BUSY low, then we probably just missed 1567 the /ACK. 1568 1569 In that case, we then check /ERROR and SELECTIN. If both are hi, 1570 (the peripheral thinks it is selected, and is not asserting /ERROR) 1571 we assume that the Indy's parallel port missed the /ACK, and return 1572 success. 1573 */ 1574 1575 #ifdef USE_INDY_ACK_HACK 1576 #define ACK_TIMEOUT_SCALER 1000 1577 #else 1578 #define ACK_TIMEOUT_SCALER 1000000 1579 #endif 1580 1581 static int 1582 pi1ppc_poll_interrupt_stat(struct pi1ppc_softc * const pi1ppc, 1583 const uint8_t match) 1584 { 1585 unsigned int timecount; 1586 uint8_t cur; 1587 int error = EIO; 1588 1589 #ifdef USE_INDY_ACK_HACK 1590 /* retry 10000x */ 1591 int retry_count = 10000; 1592 1593 retry: 1594 #endif 1595 1596 /* Wait for intr status to have match bits set for MAXBUSYWAIT */ 1597 for (timecount = 0; timecount < ((MAXBUSYWAIT/hz)*ACK_TIMEOUT_SCALER); 1598 timecount++) { 1599 cur = pi1ppc_get_intr_stat(pi1ppc); 1600 if ((cur & match) == match) { 1601 error = 0; 1602 break; 1603 } 1604 DELAY(1); 1605 } 1606 1607 #ifdef USE_INDY_ACK_HACK 1608 if(error != 0) { 1609 cur = pi1ppc_r_str(pi1ppc); 1610 1611 /* retry if BUSY is hi (inverted, so lo) and we haven't 1612 waited the usual amt */ 1613 1614 if(((cur&nBUSY) == 0) && retry_count) { 1615 retry_count--; 1616 goto retry; 1617 } 1618 1619 /* if /ERROR and SELECT are high, and the peripheral isn't 1620 BUSY, assume that we just missed the /ACK. 1621 (Remember, we emulate the PC's inverted BUSY!) 1622 */ 1623 1624 if((cur&(nFAULT|SELECT|nBUSY)) == (nFAULT|SELECT|nBUSY)) 1625 error = 0; 1626 1627 /* if things still look bad, print out some info */ 1628 if(error!=0) 1629 printf("int mask=%02x, int stat=%02x, str=%02x\n", 1630 pi1ppc_get_intr_mask(pi1ppc), 1631 pi1ppc_get_intr_stat(pi1ppc), 1632 cur); 1633 } 1634 #endif 1635 1636 return error; 1637 } 1638 1639