xref: /netbsd-src/sys/arch/sgimips/hpc/hpcdma.c (revision da5f4674a3fc214be3572d358b66af40ab9401e7)
1 /*	$NetBSD: hpcdma.c,v 1.7 2003/07/15 03:35:53 lukem Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Wayne Knowles
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Wayne Knowles
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Support for SCSI DMA provided by the HPC.
41  *
42  * Note: We use SCSI0 offsets, etc. here.  Since the layout of SCSI0
43  * and SCSI1 are the same, this is no problem.
44  */
45 
46 #include <sys/cdefs.h>
47 __KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.7 2003/07/15 03:35:53 lukem Exp $");
48 
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/device.h>
52 #include <sys/buf.h>
53 
54 #include <uvm/uvm_extern.h>
55 
56 #include <machine/bus.h>
57 
58 #include <sgimips/hpc/hpcvar.h>
59 #include <sgimips/hpc/hpcreg.h>
60 #include <sgimips/hpc/hpcdma.h>
61 
62 /*
63  * Allocate DMA Chain descriptor list
64  */
65 void
66 hpcdma_init(struct hpc_attach_args *haa, struct hpc_dma_softc *sc, int ndesc)
67 {
68 	bus_dma_segment_t seg;
69 	int rseg, allocsz;
70 
71 	sc->sc_bst = haa->ha_st;
72 	sc->sc_dmat = haa->ha_dmat;
73 	sc->sc_ndesc = ndesc;
74 	sc->sc_flags = 0;
75 
76 	if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff,
77 	    HPC_SCSI0_REGS_SIZE, &sc->sc_bsh) != 0) {
78 		printf(": can't map DMA registers\n");
79 		return;
80 	}
81 
82 	/* Alloc 1 additional descriptor - needed for DMA bug fix */
83 	allocsz = sizeof(struct hpc_dma_desc) * (ndesc + 1);
84 	KASSERT(allocsz <= PAGE_SIZE);
85 
86 	if (bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1 /*seg*/,
87 			      PAGE_SIZE, 0, BUS_DMA_WAITOK,
88 			      &sc->sc_dmamap) != 0) {
89 		printf(": failed to create dmamap\n");
90 		return;
91 	}
92 
93 	/*
94 	 * Allocate a block of memory for dma chaining pointers
95 	 */
96 	if (bus_dmamem_alloc(sc->sc_dmat, allocsz, 0, 0,
97 			     &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
98 		printf(": can't allocate sglist\n");
99 		return;
100 	}
101 	/* Map pages into kernel memory */
102 	if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, allocsz,
103 			   (caddr_t *)&sc->sc_desc_kva, BUS_DMA_NOWAIT)) {
104 		printf(": can't map sglist\n");
105 		bus_dmamem_free(sc->sc_dmat, &seg, rseg);
106 		return;
107 	}
108 
109 	if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_desc_kva,
110 			    allocsz, NULL, BUS_DMA_NOWAIT)) {
111 		printf(": can't load sglist\n");
112 		return;
113 	}
114 
115 	sc->sc_desc_pa = (void *) sc->sc_dmamap->dm_segs[0].ds_addr;
116 }
117 
118 
119 void
120 hpcdma_sglist_create(struct hpc_dma_softc *sc, bus_dmamap_t dmamap)
121 {
122 	struct hpc_dma_desc *hva, *hpa;
123 	bus_dma_segment_t *segp;
124 	int i;
125 
126 	KASSERT(dmamap->dm_nsegs <= sc->sc_ndesc);
127 
128 	hva  = sc->sc_desc_kva;
129 	hpa  = sc->sc_desc_pa;
130 	segp = dmamap->dm_segs;
131 
132 #ifdef DMA_DEBUG
133 	printf("DMA_SGLIST<");
134 #endif
135 	for (i = dmamap->dm_nsegs; i; i--) {
136 #ifdef DMA_DEBUG
137 		printf("%p:%ld, ", (void *)segp->ds_addr, segp->ds_len);
138 #endif
139 		hva->hdd_bufptr = segp->ds_addr;
140 		hva->hdd_ctl    = segp->ds_len;
141 		hva->hdd_descptr = (u_int32_t) ++hpa;
142 		++hva; ++segp;
143 	}
144 	/* Work around HPC3 DMA bug */
145 	hva->hdd_bufptr  = 0;
146 	hva->hdd_ctl     = HDD_CTL_EOCHAIN;
147 	hva->hdd_descptr = 0;
148 	hva++;
149 #ifdef DMA_DEBUG
150 	printf(">\n");
151 #endif
152 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
153 	    0, sc->sc_dmamap->dm_mapsize,
154 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
155 
156 	/* Load DMA Descriptor list */
157 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_NDBP,
158 			    (u_int32_t)sc->sc_desc_pa);
159 }
160 
161 void
162 hpcdma_cntl(struct hpc_dma_softc *sc, uint32_t mode)
163 {
164 
165 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, mode);
166 }
167 
168 void
169 hpcdma_reset(struct hpc_dma_softc *sc)
170 {
171 
172 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
173 	    HPC_DMACTL_RESET);
174 	delay(100);
175 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 0);
176 	delay(1000);
177 }
178 
179 void
180 hpcdma_flush(struct hpc_dma_softc *sc)
181 {
182 	u_int32_t	mode;
183 
184 	mode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL);
185 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
186 	    			mode | HPC_DMACTL_FLUSH);
187 
188 	/* Wait for Active bit to drop */
189 	while (bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL) &
190 	    HPC_DMACTL_ACTIVE) {
191 		bus_space_barrier(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 4,
192 		    BUS_SPACE_BARRIER_READ);
193 	}
194 }
195