1 /* $NetBSD: hpc.c,v 1.25 2004/01/02 01:04:46 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.25 2004/01/02 01:04:46 sekiya Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/reboot.h> 44 45 #include <machine/machtype.h> 46 47 #include <sgimips/gio/gioreg.h> 48 #include <sgimips/gio/giovar.h> 49 50 #include <sgimips/hpc/hpcvar.h> 51 #include <sgimips/hpc/hpcreg.h> 52 #include <sgimips/ioc/iocreg.h> 53 54 #include "locators.h" 55 56 const struct hpc_device { 57 const char *hd_name; 58 bus_addr_t hd_devoff; 59 bus_addr_t hd_dmaoff; 60 int hd_irq; 61 int hd_sysmask; 62 } hpc_devices[] = { 63 { "zsc", 64 /* XXX Magic numbers */ 65 HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 66 29, 67 HPCDEV_IP22 | HPCDEV_IP24 }, 68 69 /* probe order is important for IP20 zsc */ 70 71 { "zsc", /* serial 0/1 duart 1 */ 72 0x0d10, 0, 73 5, 74 HPCDEV_IP20 }, 75 76 { "zsc", /* serial 0/1 duart 0 */ 77 0x0d00, 0, 78 5, 79 HPCDEV_IP20 }, 80 81 { "pckbc", 82 HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 83 28, 84 HPCDEV_IP22 | HPCDEV_IP24 }, 85 86 { "sq", 87 HPC_ENET_DEVREGS, HPC_ENET_REGS, 88 3, 89 HPCDEV_IP22 | HPCDEV_IP24 }, 90 91 { "sq", 92 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 93 3, 94 HPCDEV_IP20 }, 95 96 { "wdsc", 97 HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS, 98 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 99 HPCDEV_IP22 | HPCDEV_IP24 }, 100 101 { "wdsc", 102 HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS, 103 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 104 HPCDEV_IP22 }, 105 106 { "wdsc", 107 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 108 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 109 HPCDEV_IP20 }, 110 111 { "dpclock", 112 HPC1_PBUS_BBRAM, 0, 113 -1, 114 HPCDEV_IP20 }, 115 116 { "dsclock", 117 HPC_PBUS_BBRAM, 0, 118 -1, 119 HPCDEV_IP22 | HPCDEV_IP24 }, 120 121 { "haltwo", 122 HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS, 123 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 124 HPCDEV_IP22 | HPCDEV_IP24 }, 125 126 { NULL, 127 0, 0, 128 0, 129 0 130 } 131 }; 132 133 struct hpc_softc { 134 struct device sc_dev; 135 136 bus_addr_t sc_base; 137 138 bus_space_tag_t sc_ct; 139 bus_space_handle_t sc_ch; 140 }; 141 142 static struct hpc_values hpc1_values = { 143 .revision = 1, 144 .scsi0_regs = HPC1_SCSI0_REGS, 145 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 146 .scsi0_cbp = HPC1_SCSI0_CBP, 147 .scsi0_ndbp = HPC1_SCSI0_NDBP, 148 .scsi0_bc = HPC1_SCSI0_BC, 149 .scsi0_ctl = HPC1_SCSI0_CTL, 150 .scsi0_gio = HPC1_SCSI0_GIO, 151 .scsi0_dev = HPC1_SCSI0_DEV, 152 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 153 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 154 .scsi1_regs = HPC1_SCSI1_REGS, 155 .scsi1_regs_size = HPC1_SCSI1_REGS_SIZE, 156 .scsi1_cbp = HPC1_SCSI1_CBP, 157 .scsi1_ndbp = HPC1_SCSI1_NDBP, 158 .scsi1_bc = HPC1_SCSI1_BC, 159 .scsi1_ctl = HPC1_SCSI1_CTL, 160 .scsi1_gio = HPC1_SCSI1_GIO, 161 .scsi1_dev = HPC1_SCSI1_DEV, 162 .scsi1_dmacfg = HPC1_SCSI1_DMACFG, 163 .scsi1_piocfg = HPC1_SCSI1_PIOCFG, 164 .dmactl_dir = HPC1_DMACTL_DIR, 165 .dmactl_flush = HPC1_DMACTL_FLUSH, 166 .dmactl_active = HPC1_DMACTL_ACTIVE, 167 .dmactl_reset = HPC1_DMACTL_RESET, 168 .enet_regs = HPC1_ENET_REGS, 169 .enet_regs_size = HPC1_ENET_REGS_SIZE, 170 .enet_intdelay = HPC1_ENET_INTDELAY, 171 .enet_intdelayval = HPC1_ENET_INTDELAYVAL, 172 .enetr_cbp = HPC1_ENETR_CBP, 173 .enetr_ndbp = HPC1_ENETR_NDBP, 174 .enetr_bc = HPC1_ENETR_BC, 175 .enetr_ctl = HPC1_ENETR_CTL, 176 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 177 .enetr_reset = HPC1_ENETR_RESET, 178 .enetr_dmacfg = 0, 179 .enetr_piocfg = HPC1_ENETR_PIOCFG, 180 .enetx_cbp = HPC1_ENETX_CBP, 181 .enetx_ndbp = HPC1_ENETX_NDBP, 182 .enetx_bc = HPC1_ENETX_BC, 183 .enetx_ctl = HPC1_ENETX_CTL, 184 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 185 .enetx_dev = HPC1_ENETX_DEV, 186 .enetr_fifo = HPC1_ENETR_FIFO, 187 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 188 .enetx_fifo = HPC1_ENETX_FIFO, 189 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 190 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 191 .scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 192 .enet_devregs = HPC1_ENET_DEVREGS, 193 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 194 .pbus_fifo = HPC1_PBUS_FIFO, 195 .pbus_fifo_size = HPC1_PBUS_FIFO_SIZE, 196 .pbus_bbram = HPC1_PBUS_BBRAM, 197 #define MAX_SCSI_XFER (512*1024) 198 .scsi_max_xfer = MAX_SCSI_XFER, 199 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 200 .scsi_dma_segs_size = 4096, 201 .clk_freq = 100, 202 .dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 203 .dma_dataout_cmd = HPC1_DMACTL_ACTIVE, 204 .scsi_dmactl_flush = HPC1_DMACTL_FLUSH, 205 .scsi_dmactl_active = HPC1_DMACTL_ACTIVE, 206 .scsi_dmactl_reset = HPC1_DMACTL_RESET 207 }; 208 209 static struct hpc_values hpc3_values = { 210 .revision 3, 211 .scsi0_regs = HPC_SCSI0_REGS, 212 .scsi0_regs_size = HPC_SCSI0_REGS_SIZE, 213 .scsi0_cbp = HPC_SCSI0_CBP, 214 .scsi0_ndbp = HPC_SCSI0_NDBP, 215 .scsi0_bc = HPC_SCSI0_BC, 216 .scsi0_ctl = HPC_SCSI0_CTL, 217 .scsi0_gio = HPC_SCSI0_GIO, 218 .scsi0_dev = HPC_SCSI0_DEV, 219 .scsi0_dmacfg = HPC_SCSI0_DMACFG, 220 .scsi0_piocfg = HPC_SCSI0_PIOCFG, 221 .scsi1_regs = HPC_SCSI1_REGS, 222 .scsi1_regs_size = HPC_SCSI1_REGS_SIZE, 223 .scsi1_cbp = HPC_SCSI1_CBP, 224 .scsi1_ndbp = HPC_SCSI1_NDBP, 225 .scsi1_bc = HPC_SCSI1_BC, 226 .scsi1_ctl = HPC_SCSI1_CTL, 227 .scsi1_gio = HPC_SCSI1_GIO, 228 .scsi1_dev = HPC_SCSI1_DEV, 229 .scsi1_dmacfg = HPC_SCSI1_DMACFG, 230 .scsi1_piocfg = HPC_SCSI1_PIOCFG, 231 .dmactl_dir = HPC_DMACTL_DIR, 232 .dmactl_flush = HPC_DMACTL_FLUSH, 233 .dmactl_active = HPC_DMACTL_ACTIVE, 234 .dmactl_reset = HPC_DMACTL_RESET, 235 .enet_regs = HPC_ENET_REGS, 236 .enet_regs_size = HPC_ENET_REGS_SIZE, 237 .enet_intdelay = 0, 238 .enet_intdelayval = 0, 239 .enetr_cbp = HPC_ENETR_CBP, 240 .enetr_ndbp = HPC_ENETR_NDBP, 241 .enetr_bc = HPC_ENETR_BC, 242 .enetr_ctl = HPC_ENETR_CTL, 243 .enetr_ctl_active = ENETR_CTL_ACTIVE, 244 .enetr_reset = HPC_ENETR_RESET, 245 .enetr_dmacfg = HPC_ENETR_DMACFG, 246 .enetr_piocfg = HPC_ENETR_PIOCFG, 247 .enetx_cbp = HPC_ENETX_CBP, 248 .enetx_ndbp = HPC_ENETX_NDBP, 249 .enetx_bc = HPC_ENETX_BC, 250 .enetx_ctl = HPC_ENETX_CTL, 251 .enetx_ctl_active = ENETX_CTL_ACTIVE, 252 .enetx_dev = HPC_ENETX_DEV, 253 .enetr_fifo = HPC_ENETR_FIFO, 254 .enetr_fifo_size = HPC_ENETR_FIFO_SIZE, 255 .enetx_fifo = HPC_ENETX_FIFO, 256 .enetx_fifo_size = HPC_ENETX_FIFO_SIZE, 257 .scsi0_devregs_size = HPC_SCSI0_DEVREGS_SIZE, 258 .scsi1_devregs_size = HPC_SCSI1_DEVREGS_SIZE, 259 .enet_devregs = HPC_ENET_DEVREGS, 260 .enet_devregs_size = HPC_ENET_DEVREGS_SIZE, 261 .pbus_fifo = HPC_PBUS_FIFO, 262 .pbus_fifo_size = HPC_PBUS_FIFO_SIZE, 263 .pbus_bbram = HPC_PBUS_BBRAM, 264 .scsi_max_xfer = MAX_SCSI_XFER, 265 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 266 .scsi_dma_segs_size = 8192, 267 .clk_freq = 100, 268 .dma_datain_cmd = HPC_DMACTL_ACTIVE, 269 .dma_dataout_cmd = (HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR), 270 .scsi_dmactl_flush = HPC_DMACTL_FLUSH, 271 .scsi_dmactl_active = HPC_DMACTL_ACTIVE, 272 .scsi_dmactl_reset = HPC_DMACTL_RESET 273 }; 274 275 276 extern int mach_type; /* IPxx type */ 277 extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */ 278 extern int mach_boardrev; /* machine board revision, in case it matters */ 279 280 extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag; 281 282 static int powerintr_established; 283 284 int hpc_match(struct device *, struct cfdata *, void *); 285 void hpc_attach(struct device *, struct device *, void *); 286 int hpc_print(void *, const char *); 287 288 int hpc_submatch(struct device *, struct cfdata *, void *); 289 290 int hpc_power_intr(void *); 291 292 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 293 hpc_match, hpc_attach, NULL, NULL); 294 295 int 296 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 297 { 298 struct gio_attach_args* ga = aux; 299 300 /* Make sure it's actually there and readable */ 301 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 302 return 0; 303 304 return 1; 305 } 306 307 void 308 hpc_attach(struct device *parent, struct device *self, void *aux) 309 { 310 struct hpc_softc *sc = (struct hpc_softc *)self; 311 struct gio_attach_args* ga = aux; 312 struct hpc_attach_args ha; 313 const struct hpc_device *hd; 314 int sysmask, hpctype; 315 316 switch (mach_type) { 317 case MACH_SGI_IP20: 318 hpctype = 15; 319 sysmask = HPCDEV_IP20; 320 break; 321 322 case MACH_SGI_IP22: 323 hpctype = 3; 324 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 325 sysmask = HPCDEV_IP22; 326 else 327 sysmask = HPCDEV_IP24; 328 break; 329 330 default: 331 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 332 }; 333 334 /* Verify HPC1 or HPC1.5 */ 335 if (hpctype != 3) { 336 hpctype = *(u_int32_t *) 337 MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN); 338 339 if (((hpctype >> HPC1_REVSHIFT) & HPC1_REVMASK) == HPC1_REV15) 340 hpctype = 15; 341 else 342 hpctype = 1; 343 344 /* force big-endian mode */ 345 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN) = 346 hpctype & 0xe0; 347 348 } 349 350 printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1, 351 (hpctype == 15) ? ".5" : ""); 352 353 sc->sc_ct = 1; 354 sc->sc_ch = ga->ga_ioh; 355 356 sc->sc_base = ga->ga_addr; 357 358 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 359 if (!(hd->hd_sysmask & sysmask)) 360 continue; 361 362 ha.ha_name = hd->hd_name; 363 ha.ha_devoff = hd->hd_devoff; 364 ha.ha_dmaoff = hd->hd_dmaoff; 365 ha.ha_irq = hd->hd_irq; 366 367 /* XXX This is disgusting. */ 368 ha.ha_st = 1; 369 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 370 ha.ha_dmat = &sgimips_default_bus_dma_tag; 371 if (hpctype == 3) 372 ha.hpc_regs = &hpc3_values; 373 else 374 ha.hpc_regs = &hpc1_values; 375 ha.hpc_regs->revision = hpctype; 376 377 (void) config_found_sm(self, &ha, hpc_print, hpc_submatch); 378 } 379 380 /* 381 * XXX: Only attach the powerfail interrupt once, since the 382 * interrupt code doesn't let you share interrupt just yet. 383 * 384 * Since the powerfail interrupt is hardcoded to read from 385 * a specific register anyway (XXX#2!), we don't care when 386 * it gets attached, as long as it only happens once. 387 */ 388 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 389 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 390 powerintr_established++; 391 } 392 } 393 394 int 395 hpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 396 { 397 struct hpc_attach_args *ha = aux; 398 399 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 400 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 401 return (0); 402 403 return (config_match(parent, cf, aux)); 404 } 405 406 int 407 hpc_print(void *aux, const char *pnp) 408 { 409 struct hpc_attach_args *ha = aux; 410 411 if (pnp) 412 printf("%s at %s", ha->ha_name, pnp); 413 414 printf(" offset 0x%lx", ha->ha_devoff); 415 416 return (UNCONF); 417 } 418 419 int 420 hpc_power_intr(void *arg) 421 { 422 u_int32_t pwr_reg; 423 424 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 425 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 426 427 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 428 429 if (pwr_reg & 2) 430 cpu_reboot(RB_HALT, NULL); 431 432 return 1; 433 } 434