1 /* $NetBSD: hpc.c,v 1.70 2018/09/15 00:37:53 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.70 2018/09/15 00:37:53 macallan Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #include <sys/bus.h> 48 #include <machine/machtype.h> 49 #include <machine/sysconf.h> 50 51 #include <sgimips/gio/gioreg.h> 52 #include <sgimips/gio/giovar.h> 53 54 #include <sgimips/hpc/hpcvar.h> 55 #include <sgimips/hpc/hpcreg.h> 56 #include <sgimips/ioc/iocreg.h> 57 58 #include <dev/ic/smc93cx6var.h> 59 60 #include "locators.h" 61 62 struct hpc_device { 63 const char *hd_name; 64 bus_addr_t hd_base; 65 bus_addr_t hd_devoff; 66 bus_addr_t hd_dmaoff; 67 int hd_irq; 68 int hd_sysmask; 69 }; 70 71 static const struct hpc_device hpc1_devices[] = { 72 /* probe order is important for IP20 zsc */ 73 74 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 75 HPC_BASE_ADDRESS_0, 76 0x0d10, 0, 77 5, 78 HPCDEV_IP12 | HPCDEV_IP20 }, 79 80 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 81 HPC_BASE_ADDRESS_0, 82 0x0d00, 0, 83 5, 84 HPCDEV_IP12 | HPCDEV_IP20 }, 85 86 { "sq", /* Personal Iris/Indigo onboard ethernet */ 87 HPC_BASE_ADDRESS_0, 88 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 89 3, 90 HPCDEV_IP12 | HPCDEV_IP20 }, 91 92 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 93 HPC_BASE_ADDRESS_1, 94 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 95 6, 96 HPCDEV_IP12 | HPCDEV_IP20 }, 97 98 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 99 HPC_BASE_ADDRESS_1, 100 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 101 22, 102 HPCDEV_IP24 }, 103 104 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 105 HPC_BASE_ADDRESS_2, 106 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 107 6, 108 HPCDEV_IP12 | HPCDEV_IP20 }, 109 110 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 111 HPC_BASE_ADDRESS_2, 112 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 113 23, 114 HPCDEV_IP24 }, 115 116 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 117 HPC_BASE_ADDRESS_0, 118 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 119 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 120 HPCDEV_IP12 | HPCDEV_IP20 }, 121 122 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indigo) */ 123 HPC_BASE_ADDRESS_1, 124 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 125 6, 126 HPCDEV_IP12 | HPCDEV_IP20 }, 127 128 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indy) */ 129 HPC_BASE_ADDRESS_1, 130 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 131 22, 132 HPCDEV_IP24 }, 133 134 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indigo) */ 135 HPC_BASE_ADDRESS_2, 136 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 137 6, 138 HPCDEV_IP12 | HPCDEV_IP20 }, 139 140 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indy/Challenge S) */ 141 HPC_BASE_ADDRESS_2, 142 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 143 23, 144 HPCDEV_IP24 }, 145 146 { NULL, 147 0, 148 0, 0, 149 0, 150 0 151 } 152 }; 153 154 static const struct hpc_device hpc3_devices[] = { 155 { "zsc", /* serial 0/1 duart 0 */ 156 HPC_BASE_ADDRESS_0, 157 /* XXX Magic numbers */ 158 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 159 29, 160 HPCDEV_IP22 | HPCDEV_IP24 }, 161 162 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 163 HPC_BASE_ADDRESS_0, 164 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 165 28, 166 HPCDEV_IP22 | HPCDEV_IP24 }, 167 168 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 169 HPC_BASE_ADDRESS_0, 170 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 171 3, 172 HPCDEV_IP22 | HPCDEV_IP24 }, 173 174 { "sq", /* Challenge S IOPLUS secondary ethernet */ 175 HPC_BASE_ADDRESS_1, 176 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 177 0, 178 HPCDEV_IP24 }, 179 180 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 181 HPC_BASE_ADDRESS_0, 182 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 183 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 184 HPCDEV_IP22 | HPCDEV_IP24 }, 185 186 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 187 HPC_BASE_ADDRESS_0, 188 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 189 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 190 HPCDEV_IP22 }, 191 192 { "haltwo", /* Indigo2/Indy onboard audio */ 193 HPC_BASE_ADDRESS_0, 194 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 195 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 196 HPCDEV_IP22 | HPCDEV_IP24 }, 197 198 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 199 HPC_BASE_ADDRESS_0, 200 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 201 -1, 202 HPCDEV_IP22 | HPCDEV_IP24 }, 203 204 { "button", /* Indy front panel */ 205 HPC_BASE_ADDRESS_0, 206 HPC3_PBUS_CH6_DEVREGS + IOC_PANEL, 0, 207 9, 208 HPCDEV_IP24 }, 209 210 { NULL, 211 0, 212 0, 0, 213 0, 214 0 215 } 216 }; 217 218 struct hpc_softc { 219 device_t sc_dev; 220 221 bus_addr_t sc_base; 222 223 bus_space_tag_t sc_ct; 224 bus_space_handle_t sc_ch; 225 }; 226 227 static struct hpc_values hpc1_values = { 228 .revision = 1, 229 .scsi0_regs = HPC1_SCSI0_REGS, 230 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 231 .scsi0_cbp = HPC1_SCSI0_CBP, 232 .scsi0_ndbp = HPC1_SCSI0_NDBP, 233 .scsi0_bc = HPC1_SCSI0_BC, 234 .scsi0_ctl = HPC1_SCSI0_CTL, 235 .scsi0_gio = HPC1_SCSI0_GIO, 236 .scsi0_dev = HPC1_SCSI0_DEV, 237 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 238 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 239 .scsi1_regs = 0, 240 .scsi1_regs_size = 0, 241 .scsi1_cbp = 0, 242 .scsi1_ndbp = 0, 243 .scsi1_bc = 0, 244 .scsi1_ctl = 0, 245 .scsi1_gio = 0, 246 .scsi1_dev = 0, 247 .scsi1_dmacfg = 0, 248 .scsi1_piocfg = 0, 249 .enet_regs = HPC1_ENET_REGS, 250 .enet_regs_size = HPC1_ENET_REGS_SIZE, 251 .enet_intdelay = HPC1_ENET_INTDELAY, 252 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 253 .enetr_cbp = HPC1_ENETR_CBP, 254 .enetr_ndbp = HPC1_ENETR_NDBP, 255 .enetr_bc = HPC1_ENETR_BC, 256 .enetr_ctl = HPC1_ENETR_CTL, 257 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 258 .enetr_reset = HPC1_ENETR_RESET, 259 .enetr_dmacfg = 0, 260 .enetr_piocfg = 0, 261 .enetx_cbp = HPC1_ENETX_CBP, 262 .enetx_ndbp = HPC1_ENETX_NDBP, 263 .enetx_bc = HPC1_ENETX_BC, 264 .enetx_ctl = HPC1_ENETX_CTL, 265 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 266 .enetx_dev = 0, 267 .enetr_fifo = HPC1_ENETR_FIFO, 268 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 269 .enetx_fifo = HPC1_ENETX_FIFO, 270 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 271 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 272 .scsi1_devregs_size = 0, 273 .enet_devregs = HPC1_ENET_DEVREGS, 274 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 275 .pbus_fifo = 0, 276 .pbus_fifo_size = 0, 277 .pbus_bbram = 0, 278 #define MAX_SCSI_XFER (512*1024) 279 .scsi_max_xfer = MAX_SCSI_XFER, 280 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 281 .scsi_dma_segs_size = 4096, 282 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 283 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 284 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 285 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 286 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 287 }; 288 289 static struct hpc_values hpc3_values = { 290 .revision = 3, 291 .scsi0_regs = HPC3_SCSI0_REGS, 292 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 293 .scsi0_cbp = HPC3_SCSI0_CBP, 294 .scsi0_ndbp = HPC3_SCSI0_NDBP, 295 .scsi0_bc = HPC3_SCSI0_BC, 296 .scsi0_ctl = HPC3_SCSI0_CTL, 297 .scsi0_gio = HPC3_SCSI0_GIO, 298 .scsi0_dev = HPC3_SCSI0_DEV, 299 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 300 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 301 .scsi1_regs = HPC3_SCSI1_REGS, 302 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 303 .scsi1_cbp = HPC3_SCSI1_CBP, 304 .scsi1_ndbp = HPC3_SCSI1_NDBP, 305 .scsi1_bc = HPC3_SCSI1_BC, 306 .scsi1_ctl = HPC3_SCSI1_CTL, 307 .scsi1_gio = HPC3_SCSI1_GIO, 308 .scsi1_dev = HPC3_SCSI1_DEV, 309 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 310 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 311 .enet_regs = HPC3_ENET_REGS, 312 .enet_regs_size = HPC3_ENET_REGS_SIZE, 313 .enet_intdelay = 0, 314 .enet_intdelayval = 0, 315 .enetr_cbp = HPC3_ENETR_CBP, 316 .enetr_ndbp = HPC3_ENETR_NDBP, 317 .enetr_bc = HPC3_ENETR_BC, 318 .enetr_ctl = HPC3_ENETR_CTL, 319 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 320 .enetr_reset = HPC3_ENETR_RESET, 321 .enetr_dmacfg = HPC3_ENETR_DMACFG, 322 .enetr_piocfg = HPC3_ENETR_PIOCFG, 323 .enetx_cbp = HPC3_ENETX_CBP, 324 .enetx_ndbp = HPC3_ENETX_NDBP, 325 .enetx_bc = HPC3_ENETX_BC, 326 .enetx_ctl = HPC3_ENETX_CTL, 327 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 328 .enetx_dev = HPC3_ENETX_DEV, 329 .enetr_fifo = HPC3_ENETR_FIFO, 330 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 331 .enetx_fifo = HPC3_ENETX_FIFO, 332 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 333 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 334 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 335 .enet_devregs = HPC3_ENET_DEVREGS, 336 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 337 .pbus_fifo = HPC3_PBUS_FIFO, 338 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 339 .pbus_bbram = HPC3_PBUS_BBRAM, 340 .scsi_max_xfer = MAX_SCSI_XFER, 341 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 342 .scsi_dma_segs_size = 8192, 343 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 344 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 345 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 346 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 347 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 348 }; 349 350 351 static int powerintr_established; 352 353 static int hpc_match(device_t, cfdata_t, void *); 354 static void hpc_attach(device_t, device_t, void *); 355 static int hpc_print(void *, const char *); 356 357 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 358 359 static int hpc_submatch(device_t, cfdata_t, const int *, void *); 360 361 //static int hpc_power_intr(void *); 362 363 #if defined(BLINK) 364 static callout_t hpc_blink_ch; 365 static void hpc_blink(void *); 366 #endif 367 368 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 369 uint8_t *, size_t); 370 371 CFATTACH_DECL_NEW(hpc, sizeof(struct hpc_softc), 372 hpc_match, hpc_attach, NULL, NULL); 373 374 static void hpc_bus_mem_init(bus_space_tag_t, void *); 375 376 static struct mips_bus_space hpc_mbst; 377 bus_space_tag_t hpc_memt = NULL; 378 379 380 static int 381 hpc_match(device_t parent, cfdata_t cf, void *aux) 382 { 383 struct gio_attach_args* ga = aux; 384 385 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 || 386 mach_type == MACH_SGI_IP22) { 387 /* Make sure it's actually there and readable */ 388 if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 389 sizeof(uint32_t))) 390 return 1; 391 } 392 393 return 0; 394 } 395 396 static void 397 hpc_attach(device_t parent, device_t self, void *aux) 398 { 399 struct hpc_softc *sc = device_private(self); 400 struct gio_attach_args* ga = aux; 401 struct hpc_attach_args ha; 402 const struct hpc_device *hd; 403 uint32_t hpctype; 404 int isonboard; 405 int isioplus; 406 int sysmask; 407 408 sc->sc_dev = self; 409 410 #ifdef BLINK 411 callout_init(&hpc_blink_ch, 0); 412 #endif 413 414 switch (mach_type) { 415 case MACH_SGI_IP12: 416 sysmask = HPCDEV_IP12; 417 break; 418 419 case MACH_SGI_IP20: 420 sysmask = HPCDEV_IP20; 421 break; 422 423 case MACH_SGI_IP22: 424 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 425 sysmask = HPCDEV_IP22; 426 else 427 sysmask = HPCDEV_IP24; 428 break; 429 430 default: 431 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 432 }; 433 434 if ((hpctype = hpc_revision(sc, ga)) == 0) 435 panic("hpc_attach: could not identify HPC revision\n"); 436 437 /* force big-endian mode */ 438 if (hpctype == 15) 439 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 440 441 /* 442 * All machines have only one HPC on the mainboard itself. ''Extra'' 443 * HPCs require bus arbiter and other magic to run happily. 444 */ 445 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 446 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 447 sysmask == HPCDEV_IP24); 448 449 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 450 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 451 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 452 453 /* 454 * Configure the bus arbiter appropriately. 455 * 456 * In the case of Challenge S, we must tell the IOPLUS board which 457 * DMA channel to use (we steal it from one of the slots). SGI permits 458 * an HPC1.5 in slot 1, in which case IOPLUS must use EXP0, or any 459 * other DMA-capable board in slot 0, which leaves us to use EXP1. Of 460 * course, this means that only one GIO board may use DMA. 461 * 462 * Note that this never happens on Indigo2. 463 */ 464 if (isioplus) { 465 int arb_slot; 466 467 if (platform.badaddr( 468 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) 469 arb_slot = GIO_SLOT_EXP1; 470 else 471 arb_slot = GIO_SLOT_EXP0; 472 473 if (gio_arb_config(arb_slot, GIO_ARB_LB | GIO_ARB_MST | 474 GIO_ARB_64BIT | GIO_ARB_HPC2_64BIT)) { 475 printf("%s: failed to configure GIO bus arbiter\n", 476 device_xname(sc->sc_dev)); 477 return; 478 } 479 480 printf("%s: using EXP%d's DMA channel\n", 481 device_xname(sc->sc_dev), 482 (arb_slot == GIO_SLOT_EXP0) ? 0 : 1); 483 484 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 485 HPC3_PBUS_CFGPIO_REGS, 0x0003ffff); 486 487 if (arb_slot == GIO_SLOT_EXP0) 488 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 489 HPC3_PBUS_CH0_DEVREGS, 0x20202020); 490 else 491 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 492 HPC3_PBUS_CH0_DEVREGS, 0x30303030); 493 } else if (!isonboard) { 494 int arb_slot; 495 496 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 497 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 498 499 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 500 printf("%s: failed to configure GIO bus arbiter\n", 501 device_xname(sc->sc_dev)); 502 return; 503 } 504 } 505 506 hpc_bus_mem_init(&hpc_mbst, NULL); 507 hpc_memt = &hpc_mbst; 508 509 sc->sc_ct = normal_memt; 510 sc->sc_ch = ga->ga_ioh; 511 512 sc->sc_base = ga->ga_addr; 513 514 hpc_read_eeprom(hpctype, normal_memt, 515 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, 516 sizeof(ha.hpc_eeprom)); 517 518 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 519 for (; hd->hd_name != NULL; hd++) { 520 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 521 continue; 522 523 ha.ha_name = hd->hd_name; 524 ha.ha_devoff = hd->hd_devoff; 525 ha.ha_dmaoff = hd->hd_dmaoff; 526 ha.ha_irq = hd->hd_irq; 527 528 /* XXX This is disgusting. */ 529 ha.ha_st = normal_memt; 530 if (bus_space_map(normal_memt, sc->sc_base, 0, 531 BUS_SPACE_MAP_LINEAR, &ha.ha_sh) != 0) 532 continue; 533 ha.ha_dmat = &sgimips_default_bus_dma_tag; 534 if (hpctype == 3) 535 ha.hpc_regs = &hpc3_values; 536 else 537 ha.hpc_regs = &hpc1_values; 538 ha.hpc_regs->revision = hpctype; 539 540 /* XXXgross! avoid complaining in E++ and GIO32 SCSI cases */ 541 if (hpctype != 3 && sc->sc_base != HPC_BASE_ADDRESS_0) { 542 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 543 NULL, hpc_submatch); 544 } else { 545 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 546 hpc_print, hpc_submatch); 547 } 548 } 549 550 /* 551 * XXX: Only attach the powerfail interrupt once, since the 552 * interrupt code doesn't let you share interrupt just yet. 553 * 554 * Since the powerfail interrupt is hardcoded to read from 555 * a specific register anyway (XXX#2!), we don't care when 556 * it gets attached, as long as it only happens once. 557 */ 558 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 559 // cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 560 powerintr_established++; 561 } 562 563 #if defined(BLINK) 564 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 565 hpc_blink(sc); 566 #endif 567 } 568 569 /* 570 * HPC revision detection isn't as simple as it should be. Devices probe 571 * differently depending on their slots, but luckily there is only one 572 * instance in which we have to decide the major revision (HPC1 vs HPC3). 573 * 574 * The HPC is found in the following configurations: 575 * o Personal Iris 4D/3x: 576 * One on-board HPC1 or HPC1.5. 577 * 578 * o Indigo R3k/R4k: 579 * One on-board HPC1 or HPC1.5. 580 * Up to two additional HPC1.5's in GIO slots 0 and 1. 581 * 582 * o Indy: 583 * One on-board HPC3. 584 * Up to two additional HPC1.5's in GIO slots 0 and 1. 585 * 586 * o Challenge S 587 * One on-board HPC3. 588 * Up to one additional HPC3 on the IOPLUS board (if installed). 589 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 590 * 591 * o Indigo2, Challenge M 592 * One on-board HPC3. 593 * 594 * All we really have to worry about is the IP22 case. 595 */ 596 static int 597 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 598 { 599 600 /* No hardware ever supported the last hpc base address. */ 601 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 602 return (0); 603 604 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 605 uint32_t reg; 606 607 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 608 HPC1_BIGENDIAN), 4)) { 609 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 610 HPC1_BIGENDIAN); 611 612 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 613 HPC1_REV15) 614 return (15); 615 else 616 return (1); 617 } 618 619 return (1); 620 } 621 622 /* 623 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 624 * be HPC1.5. 625 */ 626 if (mach_type == MACH_SGI_IP22) { 627 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 628 return (3); 629 630 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 631 return (15); 632 633 /* 634 * Probe for it. We use one of the PBUS registers. Note 635 * that this probe succeeds with my E++ adapter in slot 1 636 * (bad), but it appears to always do the right thing in 637 * slot 0 (good!) and we're only worried about that one 638 * anyhow. 639 */ 640 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 641 HPC3_PBUS_CH7_BP), 4)) 642 return (15); 643 else 644 return (3); 645 } 646 647 return (0); 648 } 649 650 static int 651 hpc_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 652 { 653 struct hpc_attach_args *ha = aux; 654 655 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 656 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 657 return (0); 658 659 return (config_match(parent, cf, aux)); 660 } 661 662 static int 663 hpc_print(void *aux, const char *pnp) 664 { 665 struct hpc_attach_args *ha = aux; 666 667 if (pnp) 668 printf("%s at %s", ha->ha_name, pnp); 669 670 printf(" offset %#" PRIxVADDR, (vaddr_t)ha->ha_devoff); 671 672 return (UNCONF); 673 } 674 675 #if 0 676 static int 677 hpc_power_intr(void *arg) 678 { 679 uint32_t pwr_reg; 680 681 pwr_reg = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 682 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 683 684 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 685 686 if (pwr_reg & 2) 687 cpu_reboot(RB_HALT, NULL); 688 689 return 1; 690 } 691 #endif 692 693 #if defined(BLINK) 694 static void 695 hpc_blink(void *arg) 696 { 697 struct hpc_softc *sc = arg; 698 register int s; 699 int value; 700 701 s = splhigh(); 702 703 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 704 HPC1_AUX_REGS); 705 value ^= HPC1_AUX_CONSLED; 706 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 707 HPC1_AUX_REGS) = value; 708 splx(s); 709 710 /* 711 * Blink rate is: 712 * full cycle every second if completely idle (loadav = 0) 713 * full cycle every 2 seconds if loadav = 1 714 * full cycle every 3 seconds if loadav = 2 715 * etc. 716 */ 717 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 718 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 719 } 720 #endif 721 722 /* 723 * Read the eeprom associated with one of the HPC's. 724 * 725 * NB: An eeprom is not always present, but the HPC should be able to 726 * handle this gracefully. Any consumers should validate the data to 727 * ensure it's reasonable. 728 */ 729 static int 730 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 731 uint8_t *buf, size_t len) 732 { 733 struct seeprom_descriptor sd; 734 bus_space_handle_t bsh; 735 bus_space_tag_t tag; 736 bus_size_t offset; 737 738 if (!len || len & 0x1) 739 return (1); 740 741 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 742 743 tag = normal_memt; 744 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 745 return (1); 746 747 sd.sd_chip = C56_66; 748 sd.sd_tag = tag; 749 sd.sd_bsh = bsh; 750 sd.sd_regsize = 1; 751 sd.sd_control_offset = 0; 752 sd.sd_status_offset = 0; 753 sd.sd_dataout_offset = 0; 754 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 755 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 756 sd.sd_CK = 0x04; 757 sd.sd_CS = 0x02; 758 sd.sd_MS = 0; 759 sd.sd_RDY = 0; 760 761 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 762 return (1); 763 764 bus_space_unmap(t, bsh, 1); 765 766 return (0); 767 } 768 769 #define CHIP hpc 770 #define CHIP_MEM /* defined */ 771 #define CHIP_ALIGN_STRIDE 2 772 #define CHIP_ACCESS_SIZE 4 773 #define CHIP_W1_BUS_START(v) 0x00000000UL 774 #define CHIP_W1_BUS_END(v) 0xffffffffUL 775 #define CHIP_W1_SYS_START(v) 0x00000000UL 776 #define CHIP_W1_SYS_END(v) 0xffffffffUL 777 778 #include <mips/mips/bus_space_alignstride_chipdep.c> 779