1 /* $NetBSD: pci_gio.c,v 1.18 2021/04/24 23:36:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Stephen M. Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.18 2021/04/24 23:36:48 thorpej Exp $"); 29 30 /* 31 * Glue for PCI devices that are connected to the GIO bus by various little 32 * GIO<->PCI ASICs. 33 * 34 * We presently support the following boards: 35 * o Phobos G100/G130/G160 (if_tlp, lxtphy) 36 * o Set Engineering GFE (if_tl, nsphy) 37 */ 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <sys/bus.h> 48 #include <machine/machtype.h> 49 50 #include <sgimips/gio/giovar.h> 51 #include <sgimips/gio/gioreg.h> 52 #include <sgimips/gio/giodevs.h> 53 54 #include <sgimips/dev/imcvar.h> 55 56 #include <mips/cache.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 #include <dev/pci/pciconf.h> 62 63 int giopci_debug = 0; 64 #define DPRINTF(_x) if (giopci_debug) printf _x 65 66 struct giopci_softc { 67 struct sgimips_pci_chipset sc_pc; 68 int sc_slot; 69 int sc_gprid; 70 uint32_t sc_pci_len; 71 bus_space_tag_t sc_iot; 72 bus_space_handle_t sc_ioh; 73 }; 74 75 static int giopci_match(device_t, cfdata_t, void *); 76 static void giopci_attach(device_t, device_t, void *); 77 static int giopci_bus_maxdevs(pci_chipset_tag_t, int); 78 static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int); 79 static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 80 static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 81 static int giopci_intr_map(const struct pci_attach_args *, 82 pci_intr_handle_t *); 83 static const char * 84 giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 85 char *, size_t); 86 static void *giopci_intr_establish(int, int, int (*)(void *), void *); 87 static void giopci_intr_disestablish(void *); 88 89 #define PHOBOS_PCI_OFFSET 0x00100000 90 #define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */ 91 #define PHOBOS_TULIP_START 0x00101000 92 #define PHOBOS_TULIP_END 0x001fffff 93 94 #define SETENG_MAGIC_OFFSET 0x00020000 95 #define SETENG_MAGIC_VALUE 0x00001000 96 #define SETENG_PCI_OFFSET 0x00080000 97 #define SETENG_PCI_LENGTH 128 /* ~arbitrary */ 98 #define SETENG_TLAN_START 0x00100000 99 #define SETENG_TLAN_END 0x001fffff 100 101 CFATTACH_DECL_NEW(giopci, sizeof(struct giopci_softc), 102 giopci_match, giopci_attach, NULL, NULL); 103 104 static void pcimem_bus_mem_init(bus_space_tag_t, void *); 105 static struct mips_bus_space pcimem_mbst; 106 bus_space_tag_t gio_pci_memt = NULL; 107 108 static int 109 giopci_match(device_t parent, cfdata_t match, void *aux) 110 { 111 struct gio_attach_args *ga = aux; 112 int gprid; 113 114 /* 115 * I think that these cards are all GIO32-bis or GIO64. Thus 116 * they work in either Indigo2/Challenge M or 117 * Indy/Challenge S/Indigo R4k, according to form factor. However, 118 * there are some exceptions (e.g. my Indigo R4k won't power 119 * on with the Set Engineering card installed). 120 */ 121 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22) 122 return (0); 123 124 gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 125 if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 || 126 gprid == PHOBOS_G160 || gprid == SETENG_GFE) 127 return (1); 128 129 return (0); 130 } 131 132 static void 133 giopci_attach(device_t parent, device_t self, void *aux) 134 { 135 struct giopci_softc *sc = device_private(self); 136 pci_chipset_tag_t pc = &sc->sc_pc; 137 struct gio_attach_args *ga = aux; 138 uint32_t pci_off, pci_len, arb; 139 struct pcibus_attach_args pba; 140 u_long m_start, m_end; 141 #ifdef PCI_NETBSD_CONFIGURE 142 extern int pci_conf_debug; 143 144 pci_conf_debug = giopci_debug; 145 #endif 146 147 sc->sc_iot = ga->ga_iot; 148 sc->sc_slot = ga->ga_slot; 149 sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 150 151 pcimem_bus_mem_init(&pcimem_mbst, NULL); 152 gio_pci_memt = &pcimem_mbst; 153 154 if (mach_type == MACH_SGI_IP22 && 155 mach_subtype == MACH_SGI_IP22_FULLHOUSE) 156 arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE; 157 else 158 arb = GIO_ARB_RT | GIO_ARB_MST; 159 160 if (gio_arb_config(ga->ga_slot, arb)) { 161 printf(": failed to configure GIO bus arbiter\n"); 162 return; 163 } 164 165 #if (NIMC > 0) 166 imc_disable_sysad_parity(); 167 #endif 168 169 switch (sc->sc_gprid) { 170 case PHOBOS_G100: 171 case PHOBOS_G130: 172 case PHOBOS_G160: 173 pci_off = PHOBOS_PCI_OFFSET; 174 pci_len = PHOBOS_PCI_LENGTH; 175 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START); 176 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END); 177 break; 178 179 case SETENG_GFE: 180 /* 181 * NB: The SetEng board does not allow the ThunderLAN's DMA 182 * engine to properly transfer segments that span page 183 * boundaries. See sgimips/autoconf.c where we catch a 184 * tl(4) device attachment and create an appropriate 185 * proplib entry to enable the workaround. 186 */ 187 pci_off = SETENG_PCI_OFFSET; 188 pci_len = SETENG_PCI_LENGTH; 189 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START); 190 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END); 191 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 192 SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE); 193 break; 194 195 default: 196 panic("giopci_attach: unsupported GIO product id 0x%02x", 197 sc->sc_gprid); 198 } 199 200 if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len, 201 &sc->sc_ioh)) { 202 printf("%s: unable to map PCI registers\n", device_xname(self)); 203 return; 204 } 205 sc->sc_pci_len = pci_len; 206 207 pc->pc_bus_maxdevs = giopci_bus_maxdevs; 208 pc->pc_conf_read = giopci_conf_read; 209 pc->pc_conf_write = giopci_conf_write; 210 pc->pc_conf_hook = giopci_conf_hook; 211 pc->pc_intr_map = giopci_intr_map; 212 pc->pc_intr_string = giopci_intr_string; 213 pc->intr_establish = giopci_intr_establish; 214 pc->intr_disestablish = giopci_intr_disestablish; 215 pc->iot = ga->ga_iot; 216 pc->ioh = ga->ga_ioh; 217 pc->cookie = sc; 218 219 printf(": %s\n", gio_product_string(sc->sc_gprid)); 220 221 #ifdef PCI_NETBSD_CONFIGURE 222 struct pciconf_resources *pcires = pciconf_resource_init(); 223 224 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 225 m_start, (m_end - m_start) + 1); 226 227 pci_configure_bus(pc, pcires, 0, 228 mips_cache_info.mci_dcache_align); 229 230 pciconf_resource_fini(pcires); 231 #endif 232 233 memset(&pba, 0, sizeof(pba)); 234 pba.pba_memt = gio_pci_memt; 235 pba.pba_dmat = ga->ga_dmat; 236 pba.pba_pc = pc; 237 pba.pba_flags = PCI_FLAGS_MEM_OKAY; 238 /* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */ 239 240 config_found(self, &pba, pcibusprint, CFARG_EOL); 241 } 242 243 static int 244 giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 245 { 246 247 return (busno == 0); 248 } 249 250 static pcireg_t 251 giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 252 { 253 struct giopci_softc *sc = pc->cookie; 254 int bus, dev, func; 255 pcireg_t data; 256 257 if ((unsigned int)reg >= PCI_CONF_SIZE) 258 return (pcireg_t) -1; 259 260 pci_decompose_tag(pc, tag, &bus, &dev, &func); 261 if (bus != 0 || dev != 0 || func != 0) 262 return (0); 263 264 /* XXX - should just use bus_space_peek */ 265 if (reg >= sc->sc_pci_len) { 266 DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg)); 267 return (0); 268 } 269 270 DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg)); 271 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 272 DPRINTF(("%08x\n", data)); 273 274 return (data); 275 } 276 277 static void 278 giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 279 { 280 struct giopci_softc *sc = pc->cookie; 281 int bus, dev, func; 282 283 if ((unsigned int)reg >= PCI_CONF_SIZE) 284 return; 285 286 pci_decompose_tag(pc, tag, &bus, &dev, &func); 287 if (bus != 0 || dev != 0 || func != 0) 288 return; 289 290 /* XXX - should just use bus_space_poke */ 291 if (reg >= sc->sc_pci_len) { 292 DPRINTF(("giopci_conf_write: reg 0x%x out of bounds " 293 "(val = 0x%08x)\n", reg, data)); 294 return; 295 } 296 297 DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data)); 298 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data); 299 } 300 301 static int 302 giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, 303 pcireg_t id) 304 { 305 306 /* All devices use memory accesses only. */ 307 return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM); 308 } 309 310 static int 311 giopci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 312 { 313 struct giopci_softc *sc = pa->pa_pc->cookie; 314 315 *ihp = sc->sc_slot; 316 317 return (0); 318 } 319 320 static const char * 321 giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char * buf, 322 size_t len) 323 { 324 snprintf(buf, len, "slot %s", (ih == GIO_SLOT_EXP0) ? "EXP0" : 325 (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX"); 326 return buf; 327 } 328 329 static void * 330 giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg) 331 { 332 333 return (gio_intr_establish(slot, level, func, arg)); 334 } 335 336 static void 337 giopci_intr_disestablish(void *cookie) 338 { 339 340 panic("giopci_intr_disestablish: impossible."); 341 } 342 343 #define CHIP pcimem 344 #define CHIP_MEM /* defined */ 345 #define CHIP_WRONG_ENDIAN 346 347 #define CHIP_W1_BUS_START(v) 0x00000000UL 348 #define CHIP_W1_BUS_END(v) 0xffffffffUL 349 #define CHIP_W1_SYS_START(v) 0x00000000UL 350 #define CHIP_W1_SYS_END(v) 0xffffffffUL 351 352 #include <mips/mips/bus_space_alignstride_chipdep.c> 353