1 /* $NetBSD: zs.c,v 1.40 2021/04/24 23:36:47 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.40 2021/04/24 23:36:47 thorpej Exp $"); 41 42 #include "opt_ddb.h" 43 #include "opt_kgdb.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/conf.h> 48 #include <sys/device.h> 49 #include <sys/file.h> 50 #include <sys/ioctl.h> 51 #include <sys/kernel.h> 52 #include <sys/proc.h> 53 #include <sys/tty.h> 54 #include <sys/time.h> 55 #include <sys/syslog.h> 56 #include <sys/cpu.h> 57 #include <sys/intr.h> 58 59 #include <machine/machtype.h> 60 #include <machine/autoconf.h> 61 #include <machine/z8530var.h> 62 63 #include <dev/cons.h> 64 #include <dev/ic/z8530reg.h> 65 66 #include <sgimips/hpc/hpcvar.h> 67 #include <sgimips/hpc/hpcreg.h> 68 69 #include <dev/arcbios/arcbios.h> 70 #include <dev/arcbios/arcbiosvar.h> 71 72 #include "ioconf.h" 73 74 /* 75 * Some warts needed by z8530tty.c - 76 * The default parity REALLY needs to be the same as the PROM uses, 77 * or you can not see messages done with printf during boot-up... 78 */ 79 int zs_def_cflag = (CREAD | CS8 | HUPCL); 80 81 #define PCLK 3672000 /* PCLK pin input clock rate */ 82 83 #ifndef ZS_DEFSPEED 84 #define ZS_DEFSPEED 9600 85 #endif 86 87 /* 88 * Define interrupt levels. 89 */ 90 #define ZSHARD_PRI 64 91 92 /* SGI shouldn't need ZS_DELAY() as recovery time is done in hardware? */ 93 #define ZS_DELAY() delay(3) 94 95 /* The layout of this is hardware-dependent (padding, order). */ 96 struct zschan { 97 uint8_t pad1[3]; 98 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 99 uint8_t pad2[3]; 100 volatile uint8_t zc_data; /* data */ 101 }; 102 103 struct zsdevice { 104 struct zschan zs_chan_b; 105 struct zschan zs_chan_a; 106 }; 107 108 /* Return the byte offset of element within a structure */ 109 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 110 111 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 112 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 113 #define ZS_REG_CSR 0 114 #define ZS_REG_DATA 1 115 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 116 117 static void zscnprobe (struct consdev *); 118 static void zscninit (struct consdev *); 119 static int zscngetc (dev_t); 120 static void zscnputc (dev_t, int); 121 static void zscnpollc (dev_t, int); 122 123 static int cons_port; 124 125 struct consdev zs_cn = { 126 zscnprobe, 127 zscninit, 128 zscngetc, 129 zscnputc, 130 zscnpollc, 131 NULL, 132 NULL, 133 NULL, 134 NODEV, 135 CN_NORMAL 136 }; 137 138 /* Flags from cninit() */ 139 static int zs_consunit = -1; 140 static int zs_conschan = -1; 141 142 /* Default speed for all channels */ 143 static int zs_defspeed = ZS_DEFSPEED; 144 static volatile int zssoftpending; 145 146 static uint8_t zs_init_reg[16] = { 147 0, /* 0: CMD (reset, etc.) */ 148 0, /* 1: No interrupts yet. */ 149 ZSHARD_PRI, /* 2: IVECT */ 150 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 151 ZSWR4_CLK_X16 | ZSWR4_ONESB, 152 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 153 0, /* 6: TXSYNC/SYNCLO */ 154 0, /* 7: RXSYNC/SYNCHI */ 155 0, /* 8: alias for data port */ 156 ZSWR9_MASTER_IE, 157 0, /*10: Misc. TX/RX control bits */ 158 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 159 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 160 0, /*13: BAUDHI (default=9600) */ 161 ZSWR14_BAUD_ENA, 162 ZSWR15_BREAK_IE, 163 }; 164 165 166 /**************************************************************** 167 * Autoconfig 168 ****************************************************************/ 169 170 /* Definition of the driver for autoconfig. */ 171 static int zs_hpc_match(device_t, cfdata_t, void *); 172 static void zs_hpc_attach(device_t, device_t, void *); 173 static int zs_print(void *, const char *name); 174 175 CFATTACH_DECL_NEW(zsc_hpc, sizeof(struct zsc_softc), 176 zs_hpc_match, zs_hpc_attach, NULL, NULL); 177 178 static int zshard (void *); 179 void zssoft (void *); 180 static int zs_get_speed (struct zs_chanstate *); 181 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 182 int zs_getc (void *); 183 void zs_putc (void *, int); 184 185 /* 186 * Is the zs chip present? 187 */ 188 static int 189 zs_hpc_match(device_t parent, cfdata_t cf, void *aux) 190 { 191 struct hpc_attach_args *ha = aux; 192 193 if (strcmp(ha->ha_name, cf->cf_name) == 0) 194 return (1); 195 196 return (0); 197 } 198 199 /* 200 * Attach a found zs. 201 * 202 * Match slave number to zs unit number, so that misconfiguration will 203 * not set up the keyboard as ttya, etc. 204 */ 205 static void 206 zs_hpc_attach(device_t parent, device_t self, void *aux) 207 { 208 struct zsc_softc *zsc = device_private(self); 209 struct hpc_attach_args *haa = aux; 210 struct zsc_attach_args zsc_args; 211 struct zs_chanstate *cs; 212 struct zs_channel *ch; 213 int zs_unit, channel, err, s; 214 const char *promconsdev; 215 216 promconsdev = arcbios_GetEnvironmentVariable("ConsoleOut"); 217 218 zsc->zsc_dev = self; 219 zsc->zsc_bustag = haa->ha_st; 220 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 221 haa->ha_devoff, 0x10, 222 &zsc->zsc_base)) != 0) { 223 aprint_error(": unable to map 85c30 registers, error = %d\n", 224 err); 225 return; 226 } 227 228 zs_unit = device_unit(self); 229 aprint_normal("\n"); 230 231 /* 232 * Initialize software state for each channel. 233 * 234 * Done in reverse order of channels since the first serial port 235 * is actually attached to the *second* channel, and vice versa. 236 * Doing it this way should force a 'zstty*' to attach zstty0 to 237 * channel 1 and zstty1 to channel 0. They couldn't have wired 238 * it up in a more sensible fashion, could they? 239 */ 240 for (channel = 1; channel >= 0; channel--) { 241 zsc_args.channel = channel; 242 ch = &zsc->zsc_cs_store[channel]; 243 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 244 245 zs_lock_init(cs); 246 cs->cs_reg_csr = NULL; 247 cs->cs_reg_data = NULL; 248 cs->cs_channel = channel; 249 cs->cs_private = NULL; 250 cs->cs_ops = &zsops_null; 251 cs->cs_brg_clk = PCLK / 16; 252 253 if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base, 254 zs_chan_offset[channel], 255 sizeof(struct zschan), 256 &ch->cs_regs) != 0) { 257 aprint_error_dev(self, "cannot map regs\n"); 258 return; 259 } 260 ch->cs_bustag = zsc->zsc_bustag; 261 262 memcpy(cs->cs_creg, zs_init_reg, 16); 263 memcpy(cs->cs_preg, zs_init_reg, 16); 264 265 zsc_args.hwflags = 0; 266 zsc_args.consdev = NULL; 267 268 if (zs_consunit == -1 && zs_conschan == -1) { 269 /* 270 * If this channel is being used by the PROM console, 271 * pass the generic zs driver a 'no reset' flag so the 272 * channel gets left in the appropriate state after 273 * attach. 274 * 275 * Note: the channel mappings are swapped. 276 */ 277 if (promconsdev != NULL && 278 strlen(promconsdev) == 9 && 279 strncmp(promconsdev, "serial", 6) == 0 && 280 (promconsdev[7] == '0' || promconsdev[7] == '1')) { 281 if (promconsdev[7] == '1' && channel == 0) 282 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 283 else if (promconsdev[7] == '0' && channel == 1) 284 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 285 } 286 } 287 288 /* If console, don't stomp speed, let zstty know */ 289 if (zs_unit == zs_consunit && channel == zs_conschan) { 290 zsc_args.consdev = &zs_cn; 291 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 292 293 cs->cs_defspeed = zs_get_speed(cs); 294 } else 295 cs->cs_defspeed = zs_defspeed; 296 297 cs->cs_defcflag = zs_def_cflag; 298 299 /* Make these correspond to cs_defcflag (-crtscts) */ 300 cs->cs_rr0_dcd = ZSRR0_DCD; 301 cs->cs_rr0_cts = 0; 302 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 303 cs->cs_wr5_rts = 0; 304 305 /* 306 * Clear the master interrupt enable. 307 * The INTENA is common to both channels, 308 * so just do it on the A channel. 309 */ 310 if (channel == 0) { 311 zs_write_reg(cs, 9, 0); 312 } 313 /* 314 * Look for a child driver for this channel. 315 * The child attach will setup the hardware. 316 */ 317 if (!config_found(self, (void *)&zsc_args, zs_print, 318 CFARG_EOL)) { 319 /* No sub-driver. Just reset it. */ 320 uint8_t reset = (channel == 0) ? 321 ZSWR9_A_RESET : ZSWR9_B_RESET; 322 323 s = splhigh(); 324 zs_write_reg(cs, 9, reset); 325 splx(s); 326 } 327 } 328 329 330 zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc); 331 cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL); 332 333 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 334 device_xname(self), "intr"); 335 336 /* 337 * Set the master interrupt enable and interrupt vector. 338 * (common to both channels, do it on A) 339 */ 340 cs = zsc->zsc_cs[0]; 341 s = splhigh(); 342 /* interrupt vector */ 343 zs_write_reg(cs, 2, zs_init_reg[2]); 344 /* master interrupt control (enable) */ 345 zs_write_reg(cs, 9, zs_init_reg[9]); 346 splx(s); 347 } 348 349 static int 350 zs_print(void *aux, const char *name) 351 { 352 struct zsc_attach_args *args = aux; 353 354 if (name != NULL) 355 aprint_normal("%s: ", name); 356 357 if (args->channel != -1) 358 aprint_normal(" channel %d", args->channel); 359 360 return UNCONF; 361 } 362 363 /* 364 * Our ZS chips all share a common, autovectored interrupt, 365 * so we have to look at all of them on each interrupt. 366 */ 367 static int 368 zshard(void *arg) 369 { 370 register struct zsc_softc *zsc; 371 register int rr3, unit, rval, softreq; 372 373 rval = 0; 374 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 375 zsc = device_lookup_private(&zsc_cd, unit); 376 if (zsc == NULL) 377 continue; 378 379 zsc->zsc_intrcnt.ev_count++; 380 while ((rr3 = zsc_intr_hard(zsc))) { 381 rval |= rr3; 382 } 383 384 softreq = zsc->zsc_cs[0]->cs_softreq; 385 softreq |= zsc->zsc_cs[1]->cs_softreq; 386 if (softreq && (zssoftpending == 0)) { 387 zssoftpending = 1; 388 softint_schedule(zsc->sc_si); 389 } 390 } 391 return rval; 392 } 393 394 /* 395 * Similar scheme as for zshard (look at all of them) 396 */ 397 void 398 zssoft(void *arg) 399 { 400 register struct zsc_softc *zsc; 401 register int s, unit; 402 403 /* This is not the only ISR on this IPL. */ 404 if (zssoftpending == 0) 405 return; 406 407 /* 408 * The soft intr. bit will be set by zshard only if 409 * the variable zssoftpending is zero. The order of 410 * these next two statements prevents our clearing 411 * the soft intr bit just after zshard has set it. 412 */ 413 /*isr_soft_clear(ZSSOFT_PRI);*/ 414 zssoftpending = 0; 415 416 /* Make sure we call the tty layer at spltty. */ 417 s = spltty(); 418 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 419 zsc = device_lookup_private(&zsc_cd, unit); 420 if (zsc == NULL) 421 continue; 422 (void) zsc_intr_soft(zsc); 423 } 424 splx(s); 425 return; 426 } 427 428 429 /* 430 * Compute the current baud rate given a ZS channel. 431 */ 432 static int 433 zs_get_speed(struct zs_chanstate *cs) 434 { 435 int tconst; 436 437 tconst = zs_read_reg(cs, 12); 438 tconst |= zs_read_reg(cs, 13) << 8; 439 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 440 } 441 442 /* 443 * MD functions for setting the baud rate and control modes. 444 */ 445 int 446 zs_set_speed(struct zs_chanstate *cs, int bps) 447 { 448 int tconst; 449 450 #if 0 451 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 452 {/*nop*/} 453 #endif 454 /* Wait for transmit buffer to empty */ 455 if (bps == 0) { 456 return (0); 457 } 458 459 #ifdef DIAGNOSTIC 460 if (cs->cs_brg_clk == 0) 461 panic("zs_set_speed"); 462 #endif 463 464 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 465 if (tconst < 0) 466 return (EINVAL); 467 468 #if 0 469 /* Convert back to make sure we can do it. */ 470 int real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 471 472 /* XXX - Allow some tolerance here? */ 473 if (real_bps != bps) 474 return (EINVAL); 475 #endif 476 477 cs->cs_preg[12] = tconst; 478 cs->cs_preg[13] = tconst >> 8; 479 480 /* Caller will stuff the pending registers. */ 481 return (0); 482 } 483 484 int 485 zs_set_modes(struct zs_chanstate *cs, int cflag) 486 { 487 int s; 488 489 /* 490 * Output hardware flow control on the chip is horrendous: 491 * if carrier detect drops, the receiver is disabled, and if 492 * CTS drops, the transmitter is stoped IN MID CHARACTER! 493 * Therefore, NEVER set the HFC bit, and instead use the 494 * status interrupt to detect CTS changes. 495 */ 496 s = splzs(); 497 cs->cs_rr0_pps = 0; 498 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 499 cs->cs_rr0_dcd = 0; 500 if ((cflag & MDMBUF) == 0) 501 cs->cs_rr0_pps = ZSRR0_DCD; 502 } else 503 cs->cs_rr0_dcd = ZSRR0_DCD; 504 if ((cflag & CRTSCTS) != 0) { 505 cs->cs_wr5_dtr = ZSWR5_DTR; 506 cs->cs_wr5_rts = ZSWR5_RTS; 507 cs->cs_rr0_cts = ZSRR0_CTS; 508 } else if ((cflag & MDMBUF) != 0) { 509 cs->cs_wr5_dtr = 0; 510 cs->cs_wr5_rts = ZSWR5_DTR; 511 cs->cs_rr0_cts = ZSRR0_DCD; 512 } else { 513 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 514 cs->cs_wr5_rts = 0; 515 cs->cs_rr0_cts = 0; 516 } 517 splx(s); 518 519 /* Caller will stuff the pending registers. */ 520 return (0); 521 } 522 523 524 /* 525 * Read or write the chip with suitable delays. 526 */ 527 528 uint8_t 529 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 530 { 531 uint8_t val; 532 struct zs_channel *zsc = (struct zs_channel *)cs; 533 534 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, 535 (ZS_REG_CSR << 2) + 3, reg); 536 ZS_DELAY(); 537 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, 538 (ZS_REG_CSR << 2) + 3); 539 ZS_DELAY(); 540 return val; 541 } 542 543 void 544 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 545 { 546 struct zs_channel *zsc = (struct zs_channel *)cs; 547 548 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, 549 (ZS_REG_CSR << 2) + 3, reg); 550 ZS_DELAY(); 551 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, 552 (ZS_REG_CSR << 2) + 3, val); 553 ZS_DELAY(); 554 } 555 556 uint8_t 557 zs_read_csr(struct zs_chanstate *cs) 558 { 559 struct zs_channel *zsc = (struct zs_channel *)cs; 560 uint8_t val; 561 562 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, 563 (ZS_REG_CSR << 2) + 3); 564 ZS_DELAY(); 565 return val; 566 } 567 568 void 569 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 570 { 571 struct zs_channel *zsc = (struct zs_channel *)cs; 572 573 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, 574 (ZS_REG_CSR << 2) + 3, val); 575 ZS_DELAY(); 576 } 577 578 uint8_t 579 zs_read_data(struct zs_chanstate *cs) 580 { 581 struct zs_channel *zsc = (struct zs_channel *)cs; 582 uint8_t val; 583 584 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, 585 (ZS_REG_DATA << 2) + 3); 586 ZS_DELAY(); 587 return val; 588 } 589 590 void 591 zs_write_data(struct zs_chanstate *cs, uint8_t val) 592 { 593 struct zs_channel *zsc = (struct zs_channel *)cs; 594 595 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, 596 (ZS_REG_DATA << 2) + 3, val); 597 ZS_DELAY(); 598 } 599 600 void 601 zs_abort(struct zs_chanstate *cs) 602 { 603 #if defined(KGDB) 604 zskgdb(cs); 605 #elif defined(DDB) 606 Debugger(); 607 #endif 608 } 609 610 611 /*********************************************************/ 612 /* Polled character I/O functions for console and KGDB */ 613 /*********************************************************/ 614 615 struct zschan * 616 zs_get_chan_addr(int zs_unit, int channel) 617 { 618 static int dumped_addr = 0; 619 struct zsdevice *addr; 620 struct zschan *zc; 621 622 switch (mach_type) { 623 case MACH_SGI_IP12: 624 if (zs_unit == 2 && (mach_subtype == MACH_SGI_IP12_4D_3X || 625 mach_subtype == MACH_SGI_IP12_VIP12)) { 626 addr = (struct zsdevice *) 627 MIPS_PHYS_TO_KSEG1(0x1fb80d20); 628 break; 629 } 630 631 /* FALLTHROUGH */ 632 case MACH_SGI_IP20: 633 if (zs_unit == 0) { 634 addr = (struct zsdevice *) 635 MIPS_PHYS_TO_KSEG1(0x1fb80d00); 636 } else if (zs_unit == 1) { 637 addr = (struct zsdevice *) 638 MIPS_PHYS_TO_KSEG1(0x1fb80d10); 639 } else { 640 panic("zs_get_chan_addr: bad zs_unit %d\n", zs_unit); 641 } 642 break; 643 644 case MACH_SGI_IP22: 645 if (zs_unit != 0) 646 panic("zs_get_chan_addr zs_unit != 0 on IP%d", 647 mach_type); 648 649 addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830); 650 break; 651 652 default: 653 panic("zs_get_chan_addr: unsupported IP%d", mach_type); 654 } 655 656 /* 657 * We need to swap serial ports to match reality on 658 * non-keyboard channels. 659 */ 660 if (mach_type == MACH_SGI_IP22) { 661 if (channel == 0) 662 zc = &addr->zs_chan_b; 663 else 664 zc = &addr->zs_chan_a; 665 } else { 666 if (zs_unit == 0) { 667 if (channel == 0) 668 zc = &addr->zs_chan_a; 669 else 670 zc = &addr->zs_chan_b; 671 } else { 672 if (channel == 0) 673 zc = &addr->zs_chan_b; 674 else 675 zc = &addr->zs_chan_a; 676 } 677 } 678 679 if (dumped_addr == 0) { 680 dumped_addr++; 681 aprint_debug("zs unit %d, channel %d had address %p\n", 682 zs_unit, channel, zc); 683 } 684 685 return (zc); 686 } 687 688 int 689 zs_getc(void *arg) 690 { 691 register volatile struct zschan *zc = arg; 692 register int s, c, rr0; 693 694 s = splzs(); 695 /* Wait for a character to arrive. */ 696 do { 697 rr0 = zc->zc_csr; 698 ZS_DELAY(); 699 } while ((rr0 & ZSRR0_RX_READY) == 0); 700 701 c = zc->zc_data; 702 ZS_DELAY(); 703 splx(s); 704 705 return (c); 706 } 707 708 /* 709 * Polled output char. 710 */ 711 void 712 zs_putc(void *arg, int c) 713 { 714 register volatile struct zschan *zc = arg; 715 register int s, rr0; 716 717 s = splzs(); 718 /* Wait for transmitter to become ready. */ 719 do { 720 rr0 = zc->zc_csr; 721 ZS_DELAY(); 722 } while ((rr0 & ZSRR0_TX_READY) == 0); 723 724 zc->zc_data = c; 725 wbflush(); 726 ZS_DELAY(); 727 splx(s); 728 } 729 730 /***************************************************************/ 731 void 732 zscnprobe(struct consdev *cn) 733 { 734 } 735 736 void 737 zscninit(struct consdev *cn) 738 { 739 extern const struct cdevsw zstty_cdevsw; 740 const char* consdev; 741 742 if ((consdev = arcbios_GetEnvironmentVariable("ConsoleOut")) == NULL) 743 panic("zscninit without valid ARCS ConsoleOut setting!"); 744 745 if (strlen(consdev) != 9 || 746 strncmp(consdev, "serial", 6) != 0) 747 panic("zscninit with ARCS console not set to serial!"); 748 749 cons_port = consdev[7] - '0'; 750 751 #if 0 752 /* 753 * If your IP12 serial console goes missing after consinit(), 754 * try flipping this the other way 'round. If there are some 755 * IP12 machines that actually require this, we'll be in for 756 * a lot of funnies once again... 757 */ 758 if (mach_type == MACH_SGI_IP12) 759 cons_port = 1 - cons_port; 760 #endif 761 762 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 763 cn->cn_pri = CN_REMOTE; 764 765 /* Mark this unit as the console */ 766 zs_consunit = 0; 767 768 /* SGI hardware wires serial port 1 to channel B, port 2 to A */ 769 if (cons_port == 0) 770 zs_conschan = 1; 771 else 772 zs_conschan = 0; 773 } 774 775 int 776 zscngetc(dev_t dev) 777 { 778 struct zschan *zs; 779 780 switch (mach_type) { 781 case MACH_SGI_IP12: 782 case MACH_SGI_IP20: 783 zs = zs_get_chan_addr(1, cons_port); 784 break; 785 786 case MACH_SGI_IP22: 787 default: 788 zs = zs_get_chan_addr(0, cons_port); 789 break; 790 } 791 792 return zs_getc(zs); 793 } 794 795 void 796 zscnputc(dev_t dev, int c) 797 { 798 struct zschan *zs; 799 800 switch (mach_type) { 801 case MACH_SGI_IP12: 802 case MACH_SGI_IP20: 803 zs = zs_get_chan_addr(1, cons_port); 804 break; 805 806 case MACH_SGI_IP22: 807 default: 808 zs = zs_get_chan_addr(0, cons_port); 809 break; 810 } 811 812 zs_putc(zs, c); 813 } 814 815 void 816 zscnpollc(dev_t dev, int on) 817 { 818 } 819