xref: /netbsd-src/sys/arch/sgimips/dev/zs.c (revision 404fbe5fb94ca1e054339640cabb2801ce52dd30) 
1 /*	$NetBSD: zs.c,v 1.35 2008/06/13 12:27:26 cegger Exp $	*/
2 
3 /*-
4  * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Gordon W. Ross and Wayne Knowles
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Zilog Z8530 Dual UART driver (machine-dependent part)
34  *
35  * Runs two serial lines per chip using slave drivers.
36  * Plain tty/async lines use the zs_async slave.
37  */
38 
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.35 2008/06/13 12:27:26 cegger Exp $");
41 
42 #include "opt_ddb.h"
43 #include "opt_kgdb.h"
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/intr.h>
58 
59 #include <machine/machtype.h>
60 #include <machine/autoconf.h>
61 #include <machine/z8530var.h>
62 
63 #include <dev/cons.h>
64 #include <dev/ic/z8530reg.h>
65 
66 #include <sgimips/hpc/hpcvar.h>
67 #include <sgimips/hpc/hpcreg.h>
68 
69 #include <dev/arcbios/arcbios.h>
70 #include <dev/arcbios/arcbiosvar.h>
71 
72 #include "ioconf.h"
73 
74 /*
75  * Some warts needed by z8530tty.c -
76  * The default parity REALLY needs to be the same as the PROM uses,
77  * or you can not see messages done with printf during boot-up...
78  */
79 int zs_def_cflag = (CREAD | CS8 | HUPCL);
80 
81 #define PCLK		3672000	 /* PCLK pin input clock rate */
82 
83 #ifndef ZS_DEFSPEED
84 #define ZS_DEFSPEED	9600
85 #endif
86 
87 /*
88  * Define interrupt levels.
89  */
90 #define ZSHARD_PRI 64
91 
92 /* SGI shouldn't need ZS_DELAY() as recovery time is done in hardware? */
93 #define ZS_DELAY()	delay(3)
94 
95 /* The layout of this is hardware-dependent (padding, order). */
96 struct zschan {
97 	uint8_t pad1[3];
98 	volatile uint8_t zc_csr;	/* ctrl,status, and indirect access */
99 	uint8_t pad2[3];
100 	volatile uint8_t zc_data;	/* data */
101 };
102 
103 struct zsdevice {
104 	struct	zschan zs_chan_b;
105 	struct	zschan zs_chan_a;
106 };
107 
108 /* Return the byte offset of element within a structure */
109 #define OFFSET(struct_def, el)		((size_t)&((struct_def *)0)->el)
110 
111 #define ZS_CHAN_A	OFFSET(struct zsdevice, zs_chan_a)
112 #define ZS_CHAN_B	OFFSET(struct zsdevice, zs_chan_b)
113 #define ZS_REG_CSR	0
114 #define ZS_REG_DATA	1
115 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B};
116 
117 static void zscnprobe (struct consdev *);
118 static void zscninit (struct consdev *);
119 static int  zscngetc (dev_t);
120 static void zscnputc (dev_t, int);
121 static void zscnpollc (dev_t, int);
122 
123 static int  cons_port;
124 
125 struct consdev zs_cn = {
126 	zscnprobe,
127 	zscninit,
128 	zscngetc,
129 	zscnputc,
130 	zscnpollc
131 };
132 
133 /* Flags from cninit() */
134 static int zs_consunit = -1;
135 static int zs_conschan = -1;
136 
137 /* Default speed for all channels */
138 static int zs_defspeed = ZS_DEFSPEED;
139 static volatile int zssoftpending;
140 
141 static uint8_t zs_init_reg[16] = {
142 	0,				/* 0: CMD (reset, etc.) */
143 	0,				/* 1: No interrupts yet. */
144 	ZSHARD_PRI,			/* 2: IVECT */
145 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
146 	ZSWR4_CLK_X16 | ZSWR4_ONESB,
147 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
148 	0,				/* 6: TXSYNC/SYNCLO */
149 	0,				/* 7: RXSYNC/SYNCHI */
150 	0,				/* 8: alias for data port */
151 	ZSWR9_MASTER_IE,
152 	0,				/*10: Misc. TX/RX control bits */
153 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA,
154 	BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
155 	0,				/*13: BAUDHI (default=9600) */
156 	ZSWR14_BAUD_ENA,
157 	ZSWR15_BREAK_IE,
158 };
159 
160 
161 /****************************************************************
162  * Autoconfig
163  ****************************************************************/
164 
165 /* Definition of the driver for autoconfig. */
166 static int	zs_hpc_match(device_t, cfdata_t, void *);
167 static void	zs_hpc_attach(device_t, device_t, void *);
168 static int	zs_print(void *, const char *name);
169 
170 CFATTACH_DECL_NEW(zsc_hpc, sizeof(struct zsc_softc),
171     zs_hpc_match, zs_hpc_attach, NULL, NULL);
172 
173 static int	zshard (void *);
174 void		zssoft (void *);
175 static int	zs_get_speed (struct zs_chanstate *);
176 struct		zschan *zs_get_chan_addr (int zs_unit, int channel);
177 int		zs_getc (void *);
178 void		zs_putc (void *, int);
179 
180 /*
181  * Is the zs chip present?
182  */
183 static int
184 zs_hpc_match(device_t parent, cfdata_t cf, void *aux)
185 {
186 	struct hpc_attach_args *ha = aux;
187 
188 	if (strcmp(ha->ha_name, cf->cf_name) == 0)
189 		return (1);
190 
191 	return (0);
192 }
193 
194 /*
195  * Attach a found zs.
196  *
197  * Match slave number to zs unit number, so that misconfiguration will
198  * not set up the keyboard as ttya, etc.
199  */
200 static void
201 zs_hpc_attach(device_t parent, device_t self, void *aux)
202 {
203 	struct zsc_softc *zsc = device_private(self);
204 	struct hpc_attach_args *haa = aux;
205 	struct zsc_attach_args zsc_args;
206 	struct zs_chanstate *cs;
207 	struct zs_channel *ch;
208 	int    zs_unit, channel, err, s;
209 	const char  *promconsdev;
210 
211 	promconsdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut");
212 
213 	zsc->zsc_dev = self;
214 	zsc->zsc_bustag = haa->ha_st;
215 	if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
216 				       haa->ha_devoff, 0x10,
217 				       &zsc->zsc_base)) != 0) {
218 		aprint_error(": unable to map 85c30 registers, error = %d\n",
219 		    err);
220 		return;
221 	}
222 
223 	zs_unit = device_unit(self);
224 	aprint_normal("\n");
225 
226 	/*
227 	 * Initialize software state for each channel.
228 	 *
229 	 * Done in reverse order of channels since the first serial port
230 	 * is actually attached to the *second* channel, and vice versa.
231 	 * Doing it this way should force a 'zstty*' to attach zstty0 to
232 	 * channel 1 and zstty1 to channel 0.  They couldn't have wired
233 	 * it up in a more sensible fashion, could they?
234 	 */
235 	for (channel = 1; channel >= 0; channel--) {
236 		zsc_args.channel = channel;
237 		ch = &zsc->zsc_cs_store[channel];
238 		cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
239 
240 		zs_lock_init(cs);
241 		cs->cs_reg_csr = NULL;
242 		cs->cs_reg_data = NULL;
243 		cs->cs_channel = channel;
244 		cs->cs_private = NULL;
245 		cs->cs_ops = &zsops_null;
246 		cs->cs_brg_clk = PCLK / 16;
247 
248 		if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base,
249 					zs_chan_offset[channel],
250 					sizeof(struct zschan),
251 					&ch->cs_regs) != 0) {
252 			aprint_error_dev(self, "cannot map regs\n");
253 			return;
254 		}
255 		ch->cs_bustag = zsc->zsc_bustag;
256 
257 		memcpy(cs->cs_creg, zs_init_reg, 16);
258 		memcpy(cs->cs_preg, zs_init_reg, 16);
259 
260 		zsc_args.hwflags = 0;
261 		zsc_args.consdev = NULL;
262 
263 		if (zs_consunit == -1 && zs_conschan == -1) {
264 		    /*
265 		     * If this channel is being used by the PROM console,
266 		     * pass the generic zs driver a 'no reset' flag so the
267 		     * channel gets left in the appropriate state after
268 		     * attach.
269 		     *
270 		     * Note: the channel mappings are swapped.
271 		     */
272 		    if (promconsdev != NULL &&
273 			strlen(promconsdev) == 9 &&
274 			strncmp(promconsdev, "serial", 6) == 0 &&
275 			(promconsdev[7] == '0' || promconsdev[7] == '1')) {
276 			if (promconsdev[7] == '1' && channel == 0)
277 			    zsc_args.hwflags |= ZS_HWFLAG_NORESET;
278 			else if (promconsdev[7] == '0' && channel == 1)
279 			    zsc_args.hwflags |= ZS_HWFLAG_NORESET;
280 		    }
281 		}
282 
283 		/* If console, don't stomp speed, let zstty know */
284 		if (zs_unit == zs_consunit && channel == zs_conschan) {
285 			zsc_args.consdev = &zs_cn;
286 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
287 
288 			cs->cs_defspeed = zs_get_speed(cs);
289 		} else
290 			cs->cs_defspeed = zs_defspeed;
291 
292 		cs->cs_defcflag = zs_def_cflag;
293 
294 		/* Make these correspond to cs_defcflag (-crtscts) */
295 		cs->cs_rr0_dcd = ZSRR0_DCD;
296 		cs->cs_rr0_cts = 0;
297 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
298 		cs->cs_wr5_rts = 0;
299 
300 		/*
301 		 * Clear the master interrupt enable.
302 		 * The INTENA is common to both channels,
303 		 * so just do it on the A channel.
304 		 */
305 		if (channel == 0) {
306 			zs_write_reg(cs, 9, 0);
307 		}
308 		/*
309 		 * Look for a child driver for this channel.
310 		 * The child attach will setup the hardware.
311 		 */
312 		if (!config_found(self, (void *)&zsc_args, zs_print)) {
313 			/* No sub-driver.  Just reset it. */
314 			uint8_t reset = (channel == 0) ?
315 				ZSWR9_A_RESET : ZSWR9_B_RESET;
316 
317 			s = splhigh();
318 			zs_write_reg(cs, 9, reset);
319 			splx(s);
320 		}
321 	}
322 
323 
324 	zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
325 	cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL);
326 
327 	evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
328 			     device_xname(self), "intr");
329 
330 	/*
331 	 * Set the master interrupt enable and interrupt vector.
332 	 * (common to both channels, do it on A)
333 	 */
334 	cs = zsc->zsc_cs[0];
335 	s = splhigh();
336 	/* interrupt vector */
337 	zs_write_reg(cs, 2, zs_init_reg[2]);
338 	/* master interrupt control (enable) */
339 	zs_write_reg(cs, 9, zs_init_reg[9]);
340 	splx(s);
341 }
342 
343 static int
344 zs_print(void *aux, const char *name)
345 {
346 	struct zsc_attach_args *args = aux;
347 
348 	if (name != NULL)
349 		aprint_normal("%s: ", name);
350 
351 	if (args->channel != -1)
352 		aprint_normal(" channel %d", args->channel);
353 
354 	return UNCONF;
355 }
356 
357 /*
358  * Our ZS chips all share a common, autovectored interrupt,
359  * so we have to look at all of them on each interrupt.
360  */
361 static int
362 zshard(void *arg)
363 {
364 	register struct zsc_softc *zsc;
365 	register int rr3, unit, rval, softreq;
366 
367 	rval = 0;
368 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
369 		zsc = device_lookup_private(&zsc_cd, unit);
370 		if (zsc == NULL)
371 			continue;
372 
373 		zsc->zsc_intrcnt.ev_count++;
374 		while ((rr3 = zsc_intr_hard(zsc))) {
375 			rval |= rr3;
376 		}
377 
378 		softreq = zsc->zsc_cs[0]->cs_softreq;
379 		softreq |= zsc->zsc_cs[1]->cs_softreq;
380 		if (softreq && (zssoftpending == 0)) {
381 			zssoftpending = 1;
382 			softint_schedule(zsc->sc_si);
383 		}
384 	}
385 	return rval;
386 }
387 
388 /*
389  * Similar scheme as for zshard (look at all of them)
390  */
391 void
392 zssoft(void *arg)
393 {
394 	register struct zsc_softc *zsc;
395 	register int s, unit;
396 
397 	/* This is not the only ISR on this IPL. */
398 	if (zssoftpending == 0)
399 		return;
400 
401 	/*
402 	 * The soft intr. bit will be set by zshard only if
403 	 * the variable zssoftpending is zero.  The order of
404 	 * these next two statements prevents our clearing
405 	 * the soft intr bit just after zshard has set it.
406 	 */
407 	/*isr_soft_clear(ZSSOFT_PRI);*/
408 	zssoftpending = 0;
409 
410 	/* Make sure we call the tty layer at spltty. */
411 	s = spltty();
412 	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
413 		zsc = device_lookup_private(&zsc_cd, unit);
414 		if (zsc == NULL)
415 			continue;
416 		(void) zsc_intr_soft(zsc);
417 	}
418 	splx(s);
419 	return;
420 }
421 
422 
423 /*
424  * Compute the current baud rate given a ZS channel.
425  */
426 static int
427 zs_get_speed(struct zs_chanstate *cs)
428 {
429 	int tconst;
430 
431 	tconst = zs_read_reg(cs, 12);
432 	tconst |= zs_read_reg(cs, 13) << 8;
433 	return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
434 }
435 
436 /*
437  * MD functions for setting the baud rate and control modes.
438  */
439 int
440 zs_set_speed(struct zs_chanstate *cs, int bps)
441 {
442 	int tconst, real_bps;
443 
444 #if 0
445 	while (!(zs_read_csr(cs) & ZSRR0_TX_READY))
446 		{/*nop*/}
447 #endif
448 	/* Wait for transmit buffer to empty */
449 	if (bps == 0) {
450 		return (0);
451 	}
452 
453 #ifdef	DIAGNOSTIC
454 	if (cs->cs_brg_clk == 0)
455 		panic("zs_set_speed");
456 #endif
457 
458 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
459 	if (tconst < 0)
460 		return (EINVAL);
461 
462 	/* Convert back to make sure we can do it. */
463 	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
464 
465 	/* XXX - Allow some tolerance here? */
466 #if 0
467 	if (real_bps != bps)
468 		return (EINVAL);
469 #endif
470 
471 	cs->cs_preg[12] = tconst;
472 	cs->cs_preg[13] = tconst >> 8;
473 
474 	/* Caller will stuff the pending registers. */
475 	return (0);
476 }
477 
478 int
479 zs_set_modes(struct zs_chanstate *cs, int cflag)
480 {
481 	int s;
482 
483 	/*
484 	 * Output hardware flow control on the chip is horrendous:
485 	 * if carrier detect drops, the receiver is disabled, and if
486 	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
487 	 * Therefore, NEVER set the HFC bit, and instead use the
488 	 * status interrupt to detect CTS changes.
489 	 */
490 	s = splzs();
491 	cs->cs_rr0_pps = 0;
492 	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
493 		cs->cs_rr0_dcd = 0;
494 		if ((cflag & MDMBUF) == 0)
495 			cs->cs_rr0_pps = ZSRR0_DCD;
496 	} else
497 		cs->cs_rr0_dcd = ZSRR0_DCD;
498 	if ((cflag & CRTSCTS) != 0) {
499 		cs->cs_wr5_dtr = ZSWR5_DTR;
500 		cs->cs_wr5_rts = ZSWR5_RTS;
501 		cs->cs_rr0_cts = ZSRR0_CTS;
502 	} else if ((cflag & MDMBUF) != 0) {
503 		cs->cs_wr5_dtr = 0;
504 		cs->cs_wr5_rts = ZSWR5_DTR;
505 		cs->cs_rr0_cts = ZSRR0_DCD;
506 	} else {
507 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
508 		cs->cs_wr5_rts = 0;
509 		cs->cs_rr0_cts = 0;
510 	}
511 	splx(s);
512 
513 	/* Caller will stuff the pending registers. */
514 	return (0);
515 }
516 
517 
518 /*
519  * Read or write the chip with suitable delays.
520  */
521 
522 uint8_t
523 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
524 {
525 	uint8_t val;
526 	struct zs_channel *zsc = (struct zs_channel *)cs;
527 
528 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
529 	ZS_DELAY();
530 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
531 	ZS_DELAY();
532 	return val;
533 }
534 
535 void
536 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
537 {
538 	struct zs_channel *zsc = (struct zs_channel *)cs;
539 
540 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
541 	ZS_DELAY();
542 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
543 	ZS_DELAY();
544 }
545 
546 uint8_t
547 zs_read_csr(struct zs_chanstate *cs)
548 {
549 	struct zs_channel *zsc = (struct zs_channel *)cs;
550 	uint8_t val;
551 
552 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
553 	ZS_DELAY();
554 	return val;
555 }
556 
557 void
558 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
559 {
560 	struct zs_channel *zsc = (struct zs_channel *)cs;
561 
562 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val);
563 	ZS_DELAY();
564 }
565 
566 uint8_t
567 zs_read_data(struct zs_chanstate *cs)
568 {
569 	struct zs_channel *zsc = (struct zs_channel *)cs;
570 	uint8_t val;
571 
572 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA);
573 	ZS_DELAY();
574 	return val;
575 }
576 
577 void
578 zs_write_data(struct zs_chanstate *cs, uint8_t val)
579 {
580 	struct zs_channel *zsc = (struct zs_channel *)cs;
581 
582 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val);
583 	ZS_DELAY();
584 }
585 
586 void
587 zs_abort(struct zs_chanstate *cs)
588 {
589 #if defined(KGDB)
590 	zskgdb(cs);
591 #elif defined(DDB)
592 	Debugger();
593 #endif
594 }
595 
596 
597 /*********************************************************/
598 /*  Polled character I/O functions for console and KGDB  */
599 /*********************************************************/
600 
601 struct zschan *
602 zs_get_chan_addr(int zs_unit, int channel)
603 {
604 	static int dumped_addr = 0;
605 	struct zsdevice *addr;
606 	struct zschan *zc;
607 
608 	switch (mach_type) {
609 	case MACH_SGI_IP12:
610 		if (zs_unit == 2 && (mach_subtype == MACH_SGI_IP12_4D_3X ||
611 		    		     mach_subtype == MACH_SGI_IP12_VIP12)) {
612 			addr = (struct zsdevice *)
613 						MIPS_PHYS_TO_KSEG1(0x1fb80d20);
614 			break;
615 		}
616 
617 		/* FALLTHROUGH */
618 	case MACH_SGI_IP20:
619 		if (zs_unit == 0) {
620 			addr = (struct zsdevice *)
621 						MIPS_PHYS_TO_KSEG1(0x1fb80d00);
622 		} else if (zs_unit == 1) {
623 			addr = (struct zsdevice *)
624 						MIPS_PHYS_TO_KSEG1(0x1fb80d10);
625 		} else {
626 			panic("zs_get_chan_addr: bad zs_unit %d\n", zs_unit);
627 		}
628 		break;
629 
630 	case MACH_SGI_IP22:
631 		if (zs_unit != 0)
632 			panic("zs_get_chan_addr zs_unit != 0 on IP%d",
633 								mach_type);
634 
635 		addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830);
636 		break;
637 
638 	default:
639 		panic("zs_get_chan_addr: unsupported IP%d", mach_type);
640 	}
641 
642 	/*
643 	 * We need to swap serial ports to match reality on
644 	 * non-keyboard channels.
645 	 */
646 	if (mach_type == MACH_SGI_IP22) {
647 		if (channel == 0)
648 			zc = &addr->zs_chan_b;
649 		else
650 			zc = &addr->zs_chan_a;
651 	} else {
652 		if (zs_unit == 0) {
653 			if (channel == 0)
654 				zc = &addr->zs_chan_a;
655 			else
656 				zc = &addr->zs_chan_b;
657 		} else {
658 			if (channel == 0)
659 				zc = &addr->zs_chan_b;
660 			else
661 				zc = &addr->zs_chan_a;
662 		}
663 	}
664 
665 	if (dumped_addr == 0) {
666 		dumped_addr++;
667 		aprint_debug("zs unit %d, channel %d had address %p\n",
668 						zs_unit, channel, zc);
669 	}
670 
671 	return (zc);
672 }
673 
674 int
675 zs_getc(void *arg)
676 {
677 	register volatile struct zschan *zc = arg;
678 	register int s, c, rr0;
679 
680 	s = splzs();
681 	/* Wait for a character to arrive. */
682 	do {
683 		rr0 = zc->zc_csr;
684 		ZS_DELAY();
685 	} while ((rr0 & ZSRR0_RX_READY) == 0);
686 
687 	c = zc->zc_data;
688 	ZS_DELAY();
689 	splx(s);
690 
691 	return (c);
692 }
693 
694 /*
695  * Polled output char.
696  */
697 void
698 zs_putc(void *arg, int c)
699 {
700 	register volatile struct zschan *zc = arg;
701 	register int s, rr0;
702 
703 	s = splzs();
704 	/* Wait for transmitter to become ready. */
705 	do {
706 		rr0 = zc->zc_csr;
707 		ZS_DELAY();
708 	} while ((rr0 & ZSRR0_TX_READY) == 0);
709 
710 	zc->zc_data = c;
711 	wbflush();
712 	ZS_DELAY();
713 	splx(s);
714 }
715 
716 /***************************************************************/
717 void
718 zscnprobe(struct consdev *cn)
719 {
720 }
721 
722 void
723 zscninit(struct consdev *cn)
724 {
725 	extern const struct cdevsw zstty_cdevsw;
726 	const char* consdev;
727 
728 	if ((consdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut")) == NULL)
729 		panic("zscninit without valid ARCS ConsoleOut setting!");
730 
731 	if (strlen(consdev) != 9 ||
732 	    strncmp(consdev, "serial", 6) != 0)
733 		panic("zscninit with ARCS console not set to serial!");
734 
735 	cons_port = consdev[7] - '0';
736 
737 #if 0
738 	/*
739 	 * If your IP12 serial console goes missing after consinit(),
740 	 * try flipping this the other way 'round.  If there are some
741 	 * IP12 machines that actually require this, we'll be in for
742 	 * a lot of funnies once again...
743 	 */
744 	if (mach_type == MACH_SGI_IP12)
745 		cons_port = 1 - cons_port;
746 #endif
747 
748 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port);
749 	cn->cn_pri = CN_REMOTE;
750 
751 	/* Mark this unit as the console */
752 	zs_consunit = 0;
753 
754 	/* SGI hardware wires serial port 1 to channel B, port 2 to A */
755 	if (cons_port == 0)
756 		zs_conschan = 1;
757 	else
758 		zs_conschan = 0;
759 }
760 
761 int
762 zscngetc(dev_t dev)
763 {
764 	struct zschan *zs;
765 
766 	switch (mach_type) {
767 	case MACH_SGI_IP12:
768 	case MACH_SGI_IP20:
769 		zs = zs_get_chan_addr(1, cons_port);
770 		break;
771 
772 	case MACH_SGI_IP22:
773 	default:
774 		zs = zs_get_chan_addr(0, cons_port);
775 		break;
776 	}
777 
778 	return zs_getc(zs);
779 }
780 
781 void
782 zscnputc(dev_t dev, int c)
783 {
784 	struct zschan *zs;
785 
786 	switch (mach_type) {
787 	case MACH_SGI_IP12:
788 	case MACH_SGI_IP20:
789 		zs = zs_get_chan_addr(1, cons_port);
790 		break;
791 
792 	case MACH_SGI_IP22:
793 	default:
794 		zs = zs_get_chan_addr(0, cons_port);
795 		break;
796 	}
797 
798 	zs_putc(zs, c);
799 }
800 
801 void
802 zscnpollc(dev_t dev, int on)
803 {
804 }
805