1 /* $NetBSD: zs.c,v 1.25 2004/09/29 04:06:51 sekiya Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.25 2004/09/29 04:06:51 sekiya Exp $"); 48 49 #include "opt_ddb.h" 50 #include "opt_kgdb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/cpu.h> 65 #include <machine/intr.h> 66 #include <machine/machtype.h> 67 #include <machine/autoconf.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include <sgimips/hpc/hpcvar.h> 74 #include <sgimips/hpc/hpcreg.h> 75 76 #include <dev/arcbios/arcbios.h> 77 #include <dev/arcbios/arcbiosvar.h> 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 #define PCLK 3672000 /* PCLK pin input clock rate */ 87 88 #ifndef ZS_DEFSPEED 89 #define ZS_DEFSPEED 9600 90 #endif 91 92 /* 93 * Define interrupt levels. 94 */ 95 #define ZSHARD_PRI 64 96 97 /* SGI shouldn't need ZS_DELAY() as recovery time is done in hardware? */ 98 #define ZS_DELAY() delay(3) 99 100 /* The layout of this is hardware-dependent (padding, order). */ 101 struct zschan { 102 u_char pad1[3]; 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 u_char pad2[3]; 105 volatile u_char zc_data; /* data */ 106 }; 107 108 struct zsdevice { 109 struct zschan zs_chan_b; 110 struct zschan zs_chan_a; 111 }; 112 113 /* Return the byte offset of element within a structure */ 114 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 115 116 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 117 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 118 #define ZS_REG_CSR 0 119 #define ZS_REG_DATA 1 120 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 121 122 static void zscnprobe (struct consdev *); 123 static void zscninit (struct consdev *); 124 static int zscngetc (dev_t); 125 static void zscnputc (dev_t, int); 126 static void zscnpollc (dev_t, int); 127 128 static int cons_port; 129 130 struct consdev zs_cn = { 131 zscnprobe, 132 zscninit, 133 zscngetc, 134 zscnputc, 135 zscnpollc 136 }; 137 138 /* Flags from cninit() */ 139 static int zs_consunit = -1; 140 static int zs_conschan = -1; 141 142 /* Default speed for all channels */ 143 static int zs_defspeed = ZS_DEFSPEED; 144 static volatile int zssoftpending; 145 146 static u_char zs_init_reg[16] = { 147 0, /* 0: CMD (reset, etc.) */ 148 0, /* 1: No interrupts yet. */ 149 ZSHARD_PRI, /* 2: IVECT */ 150 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 151 ZSWR4_CLK_X16 | ZSWR4_ONESB, 152 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 153 0, /* 6: TXSYNC/SYNCLO */ 154 0, /* 7: RXSYNC/SYNCHI */ 155 0, /* 8: alias for data port */ 156 ZSWR9_MASTER_IE, 157 0, /*10: Misc. TX/RX control bits */ 158 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 159 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 160 0, /*13: BAUDHI (default=9600) */ 161 ZSWR14_BAUD_ENA, 162 ZSWR15_BREAK_IE, 163 }; 164 165 166 /**************************************************************** 167 * Autoconfig 168 ****************************************************************/ 169 170 /* Definition of the driver for autoconfig. */ 171 static int zs_hpc_match (struct device *, struct cfdata *, void *); 172 static void zs_hpc_attach (struct device *, struct device *, void *); 173 static int zs_print (void *, const char *name); 174 175 CFATTACH_DECL(zsc_hpc, sizeof(struct zsc_softc), 176 zs_hpc_match, zs_hpc_attach, NULL, NULL); 177 178 extern struct cfdriver zsc_cd; 179 180 static int zshard (void *); 181 void zssoft (void *); 182 static int zs_get_speed (struct zs_chanstate *); 183 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 184 int zs_getc (void *); 185 void zs_putc (void *, int); 186 187 /* 188 * Is the zs chip present? 189 */ 190 static int 191 zs_hpc_match(struct device *parent, struct cfdata *cf, void *aux) 192 { 193 struct hpc_attach_args *ha = aux; 194 195 if (strcmp(ha->ha_name, cf->cf_name) == 0) 196 return (1); 197 198 return (0); 199 } 200 201 /* 202 * Attach a found zs. 203 * 204 * Match slave number to zs unit number, so that misconfiguration will 205 * not set up the keyboard as ttya, etc. 206 */ 207 static void 208 zs_hpc_attach(struct device *parent, struct device *self, void *aux) 209 { 210 struct zsc_softc *zsc = (void *) self; 211 struct hpc_attach_args *haa = aux; 212 struct zsc_attach_args zsc_args; 213 struct zs_chanstate *cs; 214 struct zs_channel *ch; 215 int zs_unit, channel, err, s; 216 char *promconsdev; 217 218 promconsdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut"); 219 220 zsc->zsc_bustag = haa->ha_st; 221 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 222 haa->ha_devoff, 0x10, 223 &zsc->zsc_base)) != 0) { 224 printf(": unable to map 85c30 registers, error = %d\n", err); 225 return; 226 } 227 228 zs_unit = zsc->zsc_dev.dv_unit; 229 printf("\n"); 230 231 /* 232 * Initialize software state for each channel. 233 * 234 * Done in reverse order of channels since the first serial port 235 * is actually attached to the *second* channel, and vice versa. 236 * Doing it this way should force a 'zstty*' to attach zstty0 to 237 * channel 1 and zstty1 to channel 0. They couldn't have wired 238 * it up in a more sensible fashion, could they? 239 */ 240 for (channel = 1; channel >= 0; channel--) { 241 zsc_args.channel = channel; 242 ch = &zsc->zsc_cs_store[channel]; 243 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 244 245 simple_lock_init(&cs->cs_lock); 246 cs->cs_reg_csr = NULL; 247 cs->cs_reg_data = NULL; 248 cs->cs_channel = channel; 249 cs->cs_private = NULL; 250 cs->cs_ops = &zsops_null; 251 cs->cs_brg_clk = PCLK / 16; 252 253 if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base, 254 zs_chan_offset[channel], 255 sizeof(struct zschan), 256 &ch->cs_regs) != 0) { 257 printf(": cannot map regs\n"); 258 return; 259 } 260 ch->cs_bustag = zsc->zsc_bustag; 261 262 memcpy(cs->cs_creg, zs_init_reg, 16); 263 memcpy(cs->cs_preg, zs_init_reg, 16); 264 265 zsc_args.hwflags = 0; 266 zsc_args.consdev = NULL; 267 268 if (zs_consunit == -1 && zs_conschan == -1) { 269 /* 270 * If this channel is being used by the PROM console, 271 * pass the generic zs driver a 'no reset' flag so the 272 * channel gets left in the appropriate state after 273 * attach. 274 * 275 * Note: the channel mappings are swapped. 276 */ 277 if (promconsdev != NULL && 278 strlen(promconsdev) == 9 && 279 strncmp(promconsdev, "serial", 6) == 0 && 280 (promconsdev[7] == '0' || promconsdev[7] == '1')) { 281 if (promconsdev[7] == '1' && channel == 0) 282 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 283 else if (promconsdev[7] == '0' && channel == 1) 284 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 285 } 286 } 287 288 /* If console, don't stomp speed, let zstty know */ 289 if (zs_unit == zs_consunit && channel == zs_conschan) { 290 zsc_args.consdev = &zs_cn; 291 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 292 293 cs->cs_defspeed = zs_get_speed(cs); 294 } else 295 cs->cs_defspeed = zs_defspeed; 296 297 cs->cs_defcflag = zs_def_cflag; 298 299 /* Make these correspond to cs_defcflag (-crtscts) */ 300 cs->cs_rr0_dcd = ZSRR0_DCD; 301 cs->cs_rr0_cts = 0; 302 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 303 cs->cs_wr5_rts = 0; 304 305 /* 306 * Clear the master interrupt enable. 307 * The INTENA is common to both channels, 308 * so just do it on the A channel. 309 */ 310 if (channel == 0) { 311 zs_write_reg(cs, 9, 0); 312 } 313 /* 314 * Look for a child driver for this channel. 315 * The child attach will setup the hardware. 316 */ 317 if (!config_found(self, (void *)&zsc_args, zs_print)) { 318 /* No sub-driver. Just reset it. */ 319 u_char reset = (channel == 0) ? 320 ZSWR9_A_RESET : ZSWR9_B_RESET; 321 322 s = splhigh(); 323 zs_write_reg(cs, 9, reset); 324 splx(s); 325 } 326 } 327 328 329 zsc->sc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc); 330 cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL); 331 332 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 333 self->dv_xname, "intr"); 334 335 /* 336 * Set the master interrupt enable and interrupt vector. 337 * (common to both channels, do it on A) 338 */ 339 cs = zsc->zsc_cs[0]; 340 s = splhigh(); 341 /* interrupt vector */ 342 zs_write_reg(cs, 2, zs_init_reg[2]); 343 /* master interrupt control (enable) */ 344 zs_write_reg(cs, 9, zs_init_reg[9]); 345 splx(s); 346 } 347 348 static int 349 zs_print(void *aux, const char *name) 350 { 351 struct zsc_attach_args *args = aux; 352 353 if (name != NULL) 354 aprint_normal("%s: ", name); 355 356 if (args->channel != -1) 357 aprint_normal(" channel %d", args->channel); 358 359 return UNCONF; 360 } 361 362 /* 363 * Our ZS chips all share a common, autovectored interrupt, 364 * so we have to look at all of them on each interrupt. 365 */ 366 static int 367 zshard(void *arg) 368 { 369 register struct zsc_softc *zsc; 370 register int rr3, unit, rval, softreq; 371 372 rval = 0; 373 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 374 zsc = zsc_cd.cd_devs[unit]; 375 if (zsc == NULL) 376 continue; 377 378 zsc->zsc_intrcnt.ev_count++; 379 while ((rr3 = zsc_intr_hard(zsc))) { 380 rval |= rr3; 381 } 382 383 softreq = zsc->zsc_cs[0]->cs_softreq; 384 softreq |= zsc->zsc_cs[1]->cs_softreq; 385 if (softreq && (zssoftpending == 0)) { 386 zssoftpending = 1; 387 softintr_schedule(zsc->sc_si); 388 } 389 } 390 return rval; 391 } 392 393 /* 394 * Similar scheme as for zshard (look at all of them) 395 */ 396 void 397 zssoft(void *arg) 398 { 399 register struct zsc_softc *zsc; 400 register int s, unit; 401 402 /* This is not the only ISR on this IPL. */ 403 if (zssoftpending == 0) 404 return; 405 406 /* 407 * The soft intr. bit will be set by zshard only if 408 * the variable zssoftpending is zero. The order of 409 * these next two statements prevents our clearing 410 * the soft intr bit just after zshard has set it. 411 */ 412 /*isr_soft_clear(ZSSOFT_PRI);*/ 413 zssoftpending = 0; 414 415 /* Make sure we call the tty layer at spltty. */ 416 s = spltty(); 417 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 418 zsc = zsc_cd.cd_devs[unit]; 419 if (zsc == NULL) 420 continue; 421 (void) zsc_intr_soft(zsc); 422 } 423 splx(s); 424 return; 425 } 426 427 428 /* 429 * Compute the current baud rate given a ZS channel. 430 */ 431 static int 432 zs_get_speed(struct zs_chanstate *cs) 433 { 434 int tconst; 435 436 tconst = zs_read_reg(cs, 12); 437 tconst |= zs_read_reg(cs, 13) << 8; 438 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 439 } 440 441 /* 442 * MD functions for setting the baud rate and control modes. 443 */ 444 int 445 zs_set_speed(struct zs_chanstate *cs, int bps) 446 { 447 int tconst, real_bps; 448 449 #if 0 450 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 451 {/*nop*/} 452 #endif 453 /* Wait for transmit buffer to empty */ 454 if (bps == 0) { 455 return (0); 456 } 457 458 #ifdef DIAGNOSTIC 459 if (cs->cs_brg_clk == 0) 460 panic("zs_set_speed"); 461 #endif 462 463 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 464 if (tconst < 0) 465 return (EINVAL); 466 467 /* Convert back to make sure we can do it. */ 468 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 469 470 /* XXX - Allow some tolerance here? */ 471 #if 0 472 if (real_bps != bps) 473 return (EINVAL); 474 #endif 475 476 cs->cs_preg[12] = tconst; 477 cs->cs_preg[13] = tconst >> 8; 478 479 /* Caller will stuff the pending registers. */ 480 return (0); 481 } 482 483 int 484 zs_set_modes(struct zs_chanstate *cs, int cflag) 485 { 486 int s; 487 488 /* 489 * Output hardware flow control on the chip is horrendous: 490 * if carrier detect drops, the receiver is disabled, and if 491 * CTS drops, the transmitter is stoped IN MID CHARACTER! 492 * Therefore, NEVER set the HFC bit, and instead use the 493 * status interrupt to detect CTS changes. 494 */ 495 s = splzs(); 496 cs->cs_rr0_pps = 0; 497 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 498 cs->cs_rr0_dcd = 0; 499 if ((cflag & MDMBUF) == 0) 500 cs->cs_rr0_pps = ZSRR0_DCD; 501 } else 502 cs->cs_rr0_dcd = ZSRR0_DCD; 503 if ((cflag & CRTSCTS) != 0) { 504 cs->cs_wr5_dtr = ZSWR5_DTR; 505 cs->cs_wr5_rts = ZSWR5_RTS; 506 cs->cs_rr0_cts = ZSRR0_CTS; 507 } else if ((cflag & MDMBUF) != 0) { 508 cs->cs_wr5_dtr = 0; 509 cs->cs_wr5_rts = ZSWR5_DTR; 510 cs->cs_rr0_cts = ZSRR0_DCD; 511 } else { 512 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 513 cs->cs_wr5_rts = 0; 514 cs->cs_rr0_cts = 0; 515 } 516 splx(s); 517 518 /* Caller will stuff the pending registers. */ 519 return (0); 520 } 521 522 523 /* 524 * Read or write the chip with suitable delays. 525 */ 526 527 u_char 528 zs_read_reg(struct zs_chanstate *cs, u_char reg) 529 { 530 u_char val; 531 struct zs_channel *zsc = (struct zs_channel *)cs; 532 533 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 534 ZS_DELAY(); 535 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 536 ZS_DELAY(); 537 return val; 538 } 539 540 void 541 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 542 { 543 struct zs_channel *zsc = (struct zs_channel *)cs; 544 545 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 546 ZS_DELAY(); 547 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 548 ZS_DELAY(); 549 } 550 551 u_char 552 zs_read_csr(struct zs_chanstate *cs) 553 { 554 struct zs_channel *zsc = (struct zs_channel *)cs; 555 register u_char val; 556 557 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 558 ZS_DELAY(); 559 return val; 560 } 561 562 void 563 zs_write_csr(struct zs_chanstate *cs, u_char val) 564 { 565 struct zs_channel *zsc = (struct zs_channel *)cs; 566 567 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 568 ZS_DELAY(); 569 } 570 571 u_char 572 zs_read_data(struct zs_chanstate *cs) 573 { 574 struct zs_channel *zsc = (struct zs_channel *)cs; 575 register u_char val; 576 577 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 578 ZS_DELAY(); 579 return val; 580 } 581 582 void 583 zs_write_data(struct zs_chanstate *cs, u_char val) 584 { 585 struct zs_channel *zsc = (struct zs_channel *)cs; 586 587 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 588 ZS_DELAY(); 589 } 590 591 void 592 zs_abort(struct zs_chanstate *cs) 593 { 594 #if defined(KGDB) 595 zskgdb(cs); 596 #elif defined(DDB) 597 Debugger(); 598 #endif 599 } 600 601 602 /*********************************************************/ 603 /* Polled character I/O functions for console and KGDB */ 604 /*********************************************************/ 605 606 struct zschan * 607 zs_get_chan_addr(int zs_unit, int channel) 608 { 609 static int dumped_addr = 0; 610 struct zsdevice *addr; 611 struct zschan *zc; 612 613 switch (mach_type) { 614 case MACH_SGI_IP12: 615 if (zs_unit == 2 && (mach_subtype == MACH_SGI_IP12_4D_3X || 616 mach_subtype == MACH_SGI_IP12_VIP12)) { 617 addr = (struct zsdevice *) 618 MIPS_PHYS_TO_KSEG1(0x1fb80d20); 619 break; 620 } 621 622 /* FALLTHROUGH */ 623 case MACH_SGI_IP20: 624 if (zs_unit == 0) { 625 addr = (struct zsdevice *) 626 MIPS_PHYS_TO_KSEG1(0x1fb80d00); 627 } else if (zs_unit == 1) { 628 addr = (struct zsdevice *) 629 MIPS_PHYS_TO_KSEG1(0x1fb80d10); 630 } else { 631 panic("zs_get_chan_addr: bad zs_unit %d\n", zs_unit); 632 } 633 break; 634 635 case MACH_SGI_IP22: 636 if (zs_unit != 0) 637 panic("zs_get_chan_addr zs_unit != 0 on IP%d", 638 mach_type); 639 640 addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830); 641 break; 642 643 default: 644 panic("zs_get_chan_addr: unsupported IP%d", mach_type); 645 } 646 647 /* 648 * We need to swap serial ports to match reality on 649 * non-keyboard channels. 650 */ 651 if (mach_type == MACH_SGI_IP22) { 652 if (channel == 0) 653 zc = &addr->zs_chan_b; 654 else 655 zc = &addr->zs_chan_a; 656 } else { 657 if (zs_unit == 0) { 658 if (channel == 0) 659 zc = &addr->zs_chan_a; 660 else 661 zc = &addr->zs_chan_b; 662 } else { 663 if (channel == 0) 664 zc = &addr->zs_chan_b; 665 else 666 zc = &addr->zs_chan_a; 667 } 668 } 669 670 if (dumped_addr == 0) { 671 dumped_addr++; 672 aprint_debug("zs unit %d, channel %d had address %p\n", 673 zs_unit, channel, zc); 674 } 675 676 return (zc); 677 } 678 679 int 680 zs_getc(void *arg) 681 { 682 register volatile struct zschan *zc = arg; 683 register int s, c, rr0; 684 685 s = splzs(); 686 /* Wait for a character to arrive. */ 687 do { 688 rr0 = zc->zc_csr; 689 ZS_DELAY(); 690 } while ((rr0 & ZSRR0_RX_READY) == 0); 691 692 c = zc->zc_data; 693 ZS_DELAY(); 694 splx(s); 695 696 return (c); 697 } 698 699 /* 700 * Polled output char. 701 */ 702 void 703 zs_putc(void *arg, int c) 704 { 705 register volatile struct zschan *zc = arg; 706 register int s, rr0; 707 708 s = splzs(); 709 /* Wait for transmitter to become ready. */ 710 do { 711 rr0 = zc->zc_csr; 712 ZS_DELAY(); 713 } while ((rr0 & ZSRR0_TX_READY) == 0); 714 715 zc->zc_data = c; 716 wbflush(); 717 ZS_DELAY(); 718 splx(s); 719 } 720 721 /***************************************************************/ 722 void 723 zscnprobe(struct consdev *cn) 724 { 725 } 726 727 void 728 zscninit(struct consdev *cn) 729 { 730 extern const struct cdevsw zstty_cdevsw; 731 char* consdev; 732 733 if ((consdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut")) == NULL) 734 panic("zscninit without valid ARCS ConsoleOut setting!"); 735 736 if (strlen(consdev) != 9 || 737 strncmp(consdev, "serial", 6) != 0) 738 panic("zscninit with ARCS console not set to serial!"); 739 740 cons_port = consdev[7] - '0'; 741 742 #if 0 743 /* 744 * If your IP12 serial console goes missing after consinit(), 745 * try flipping this the other way 'round. If there are some 746 * IP12 machines that actually require this, we'll be in for 747 * a lot of funnies once again... 748 */ 749 if (mach_type == MACH_SGI_IP12) 750 cons_port = 1 - cons_port; 751 #endif 752 753 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 754 cn->cn_pri = CN_REMOTE; 755 756 /* Mark this unit as the console */ 757 zs_consunit = 0; 758 759 /* SGI hardware wires serial port 1 to channel B, port 2 to A */ 760 if (cons_port == 0) 761 zs_conschan = 1; 762 else 763 zs_conschan = 0; 764 } 765 766 int 767 zscngetc(dev_t dev) 768 { 769 struct zschan *zs; 770 771 switch (mach_type) { 772 case MACH_SGI_IP12: 773 case MACH_SGI_IP20: 774 zs = zs_get_chan_addr(1, cons_port); 775 break; 776 777 case MACH_SGI_IP22: 778 default: 779 zs = zs_get_chan_addr(0, cons_port); 780 break; 781 } 782 783 return zs_getc(zs); 784 } 785 786 void 787 zscnputc(dev_t dev, int c) 788 { 789 struct zschan *zs; 790 791 switch (mach_type) { 792 case MACH_SGI_IP12: 793 case MACH_SGI_IP20: 794 zs = zs_get_chan_addr(1, cons_port); 795 break; 796 797 case MACH_SGI_IP22: 798 default: 799 zs = zs_get_chan_addr(0, cons_port); 800 break; 801 } 802 803 zs_putc(zs, c); 804 } 805 806 void 807 zscnpollc(dev_t dev, int on) 808 { 809 } 810