1 /* $NetBSD: scn.c,v 1.6 2014/03/24 19:10:34 christos Exp $ */ 2 3 /* 4 * Resurrected from the old pc532 port 1/18/2009. 5 * 6 * XXX- The locking in this is probably totally broken. I haven't attempted 7 * to get it right, but it seems to work okay anyhow. 8 */ 9 10 /* 11 * Copyright (c) 1991, 1992, 1993 12 * The Regents of the University of California. All rights reserved. 13 * 14 * Portions of this software were developed by the Computer Systems 15 * Engineering group at Lawrence Berkeley Laboratory under DARPA 16 * contract BG 91-66 and contributed to Berkeley. 17 * 18 * All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Lawrence Berkeley Laboratory. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 48 */ 49 50 /* 51 * Copyright (c) 1996, 1997 Philip L. Budne. 52 * Copyright (c) 1993 Philip A. Nelson. 53 * 54 * Portions of this software were developed by the Computer Systems 55 * Engineering group at Lawrence Berkeley Laboratory under DARPA 56 * contract BG 91-66 and contributed to Berkeley. 57 * 58 * All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Lawrence Berkeley Laboratory. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 3. All advertising materials mentioning features or use of this software 72 * must display the following acknowledgement: 73 * This product includes software developed by the University of 74 * California, Berkeley and its contributors. 75 * 4. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 #include <sys/cdefs.h> 95 __KERNEL_RCSID(0, "$NetBSD: scn.c,v 1.6 2014/03/24 19:10:34 christos Exp $"); 96 97 #include "opt_ddb.h" 98 #include "opt_kgdb.h" 99 #include "scn.h" 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/file.h> 108 #include <sys/uio.h> 109 #include <sys/kernel.h> 110 #include <sys/syslog.h> 111 #include <sys/types.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/conf.h> 115 #include <sys/intr.h> 116 #ifdef KGDB 117 #include <sys/kgdb.h> 118 #endif 119 #include <sys/kauth.h> 120 121 #include <dev/cons.h> 122 123 #include <machine/autoconf.h> 124 #include <machine/machtype.h> 125 126 #include <sgimips/dev/scnreg.h> 127 #include <sgimips/dev/scnvar.h> 128 129 int scn_match(device_t, struct cfdata *, void *); 130 void scn_attach(device_t, device_t, void *); 131 int scnparam(struct tty *, struct termios *); 132 void scnstart(struct tty *); 133 int scnhwiflow(struct tty *, int); 134 135 void scncnprobe(struct consdev *); 136 void scncninit(struct consdev *); 137 int scncngetc(dev_t); 138 void scncnputc(dev_t, int); 139 void scncnpollc(dev_t, int); 140 int scninit(dev_t, int); 141 void scncnreinit(void *); 142 143 CFATTACH_DECL_NEW(scn, sizeof(struct scn_softc), 144 scn_match, scn_attach, NULL, NULL); 145 146 extern struct cfdriver scn_cd; 147 148 dev_type_open(scnopen); 149 dev_type_close(scnclose); 150 dev_type_read(scnread); 151 dev_type_write(scnwrite); 152 dev_type_ioctl(scnioctl); 153 dev_type_stop(scnstop); 154 dev_type_tty(scntty); 155 dev_type_poll(scnpoll); 156 157 const struct cdevsw scn_cdevsw = { 158 .d_open = scnopen, 159 .d_close = scnclose, 160 .d_read = scnread, 161 .d_write = scnwrite, 162 .d_ioctl = scnioctl, 163 .d_stop = scnstop, 164 .d_tty = scntty, 165 .d_poll = scnpoll, 166 .d_mmap = nommap, 167 .d_kqfilter = ttykqfilter, 168 .d_flag = D_TTY 169 }; 170 171 struct consdev scn_cn = { 172 scncnprobe, 173 scncninit, 174 scncngetc, 175 scncnputc, 176 scncnpollc, 177 NULL, 178 NULL, 179 NULL, 180 NODEV, 181 CN_NORMAL 182 }; 183 184 #ifndef CONSOLE_SPEED 185 #define CONSOLE_SPEED TTYDEF_SPEED 186 #endif 187 188 #ifndef SCNDEF_CFLAG 189 #define SCNDEF_CFLAG TTYDEF_CFLAG 190 #endif 191 192 #ifdef CPU30MHZ 193 #define RECOVER() __asm volatile("bispsrw 0x800" : : : "cc") 194 #else 195 #define RECOVER() 196 #endif 197 198 int scndefaultrate = TTYDEF_SPEED; 199 int scnconsrate = CONSOLE_SPEED; 200 201 static inline struct scn_softc * 202 SOFTC(int unit) 203 { 204 if (unit < 0 || unit >= scn_cd.cd_ndevs) 205 return (NULL); 206 return device_private(scn_cd.cd_devs[unit]); 207 } 208 209 static int scnintr(void *); 210 static void scnrxintr(void *); 211 static int scn_rxintr(struct scn_softc *); 212 static void scnsoft(void *); 213 static void scn_setchip(struct scn_softc *sc); 214 static int scniter(int *, int, int*, int*, struct chan *, int); 215 static int scn_config(int, int, int, int, u_char, u_char); 216 static void scn_rxenable(struct scn_softc *); 217 static void scn_rxdisable(struct scn_softc *); 218 static void dcd_int(struct scn_softc *, struct tty *, u_char); 219 static void scnoverrun(int, long *, const char *); 220 static u_char opbits(struct scn_softc *, int); 221 222 static void *scnsir = NULL; /* s/w intr cookie */ 223 #define setsoftscn() softint_schedule(scnsir) 224 225 #ifdef SCN_TIMING 226 /* 227 * Keep timing info on latency of software interrupt used by 228 * the ringbuf code to empty ring buffer. 229 * "getinfo" program reads data from /dev/kmem. 230 */ 231 static struct timeval tstart; 232 #define NJITTER 100 233 int scn_njitter = NJITTER; 234 int scn_jitter[NJITTER]; 235 #endif 236 237 #define SCN_CLOCK 3686400 /* input clock */ 238 239 /* speed table groups ACR[7] */ 240 #define GRP_A 0 241 #define GRP_B ACR_BRG 242 243 /* combo of MR0[2:0] and ACR[7] */ 244 #define MODE0A MR0_MODE_0 245 #define MODE0B (MR0_MODE_0|ACR_BRG) 246 #define MODE1A MR0_MODE_1 247 #define MODE1B (MR0_MODE_1|ACR_BRG) 248 #define MODE2A MR0_MODE_2 249 #define MODE2B (MR0_MODE_2|ACR_BRG) 250 251 #define ANYMODE -1 252 #define DEFMODE(C92) MODE0A /* use MODE4A if 26c92? */ 253 254 /* speed code for Counter/Timer (all modes, groups) */ 255 #define USE_CT 0xd 256 257 /* 258 * Rate table, ordered by speed, then mode. 259 * NOTE: ordering of modes must be done carefully! 260 */ 261 struct tabent { 262 int32_t speed; 263 int16_t code; 264 int16_t mode; 265 } table[] = { 266 { 50, 0x0, MODE0A }, 267 { 75, 0x0, MODE0B }, 268 { 110, 0x1, MODE0A }, 269 { 110, 0x1, MODE0B }, 270 { 110, 0x1, MODE1A }, 271 { 110, 0x1, MODE1B }, 272 { 134, 0x2, MODE0A }, /* 134.5 */ 273 { 134, 0x2, MODE0B }, /* 134.5 */ 274 { 134, 0x2, MODE1A }, /* 134.5 */ 275 { 134, 0x2, MODE1B }, /* 134.5 */ 276 { 150, 0x3, MODE0A }, 277 { 150, 0x3, MODE0A }, 278 { 200, 0x3, MODE0A }, 279 { 300, 0x4, MODE0A }, 280 { 300, 0x4, MODE0B }, 281 { 300, 0x0, MODE1A }, 282 { 450, 0x0, MODE1B }, 283 { 600, 0x5, MODE0A }, 284 { 600, 0x5, MODE0B }, 285 { 880, 0x1, MODE2A }, 286 { 880, 0x1, MODE2B }, 287 { 900, 0x3, MODE1B }, 288 { 1050, 0x7, MODE0A }, 289 { 1050, 0x7, MODE1A }, 290 { 1076, 0x2, MODE2A }, 291 { 1076, 0x2, MODE2B }, 292 { 1200, 0x6, MODE0A }, 293 { 1200, 0x6, MODE0B }, 294 { 1200, 0x3, MODE1A }, 295 { 1800, 0xa, MODE0B }, 296 { 1800, 0x4, MODE1A }, 297 { 1800, 0x4, MODE1B }, 298 { 2000, 0x7, MODE0B }, 299 { 2000, 0x7, MODE1B }, 300 { 2400, 0x8, MODE0A }, 301 { 2400, 0x8, MODE0B }, 302 { 3600, 0x5, MODE1A }, 303 { 3600, 0x5, MODE1B }, 304 { 4800, 0x9, MODE2A }, 305 { 4800, 0x9, MODE2B }, 306 { 4800, 0x9, MODE0A }, 307 { 4800, 0x9, MODE0B }, 308 { 7200, 0xa, MODE0A }, 309 { 7200, 0x0, MODE2B }, 310 { 7200, 0x6, MODE1A }, 311 { 7200, 0x6, MODE1B }, 312 { 9600, 0xb, MODE2A }, 313 { 9600, 0xb, MODE2B }, 314 { 9600, 0xb, MODE0A }, 315 { 9600, 0xb, MODE0B }, 316 { 9600, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 317 { 9600, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 318 { 14400, 0x3, MODE2B }, 319 { 14400, 0x8, MODE1A }, 320 { 14400, 0x8, MODE1B }, 321 { 19200, 0x3, MODE2A }, 322 { 19200, 0xc, MODE2B }, 323 { 19200, 0xc, MODE0B }, 324 { 19200, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 325 { 19200, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 326 { 28800, 0x4, MODE2A }, 327 { 28800, 0x4, MODE2B }, 328 { 28800, 0x9, MODE1A }, 329 { 28800, 0x9, MODE1B }, 330 { 38400, 0xc, MODE2A }, 331 { 38400, 0xc, MODE0A }, 332 { 57600, 0x5, MODE2A }, 333 { 57600, 0x5, MODE2B }, 334 { 57600, 0xb, MODE1A }, 335 { 57600, 0xb, MODE1B }, 336 { 115200, 0x6, MODE2A }, 337 { 115200, 0x6, MODE2B }, 338 { 115200, 0xc, MODE1B }, 339 { 230400, 0xc, MODE1A } 340 }; 341 #define TABENTRIES (sizeof(table)/sizeof(table[0])) 342 343 /* 344 * boolean for speed codes which are identical in both A/B BRG groups 345 * in all modes 346 */ 347 static u_char bothgroups[16] = { 348 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1 349 }; 350 351 /* 352 * Manually constructed divisors table 353 * for minimum error (from some of Dave Rand's code) 354 */ 355 const struct { 356 uint16_t speed; 357 uint16_t div; 358 } divs[] = { 359 { 50, 2303 }, /* 2304 is exact?? */ 360 { 110, 1047 }, /* Should be 1047.27 */ 361 { 134, 857 }, /* Should be 856.505576 */ 362 { 1050, 110 }, /* Should be 109.7142857 */ 363 { 2000, 57 } /* Should be 57.6 */ 364 }; 365 #define DIVS (sizeof(divs)/sizeof(divs[0])) 366 367 /* 368 * minor unit bit decode: 369 * CxxxUUU 370 * 371 * C - carrier 372 * 0 - delay open until carrier high 373 * 1 - allow open with carrier low 374 * UUU - unit 0-7 375 */ 376 377 #define DEV_UNIT(x) (minor(x) & 0x7) 378 #define DEV_DIALOUT(x) (minor(x) & 0x80) 379 380 extern struct tty *constty; 381 382 #define SCN_MAXDUART 4 383 static struct duart scn_duart[SCN_MAXDUART]; 384 385 #ifdef KGDB 386 extern int kgdb_dev; 387 extern int kgdb_rate; 388 extern int kgdb_debug_init; 389 #endif 390 391 /* XXXXX - fix this */ 392 #define splrtty() spltty() 393 394 /* RS-232 configuration routines */ 395 396 /* 397 * set chip parameters, or mark for delayed change. 398 * called at spltty() or on TxEMPTY interrupt. 399 * 400 * Reads current values to avoid glitches from redundant sets. 401 * Perhaps should save last value set to avoid read/write? NOTE: 402 * Would still need to do read if write not needed to advance MR 403 * pointer. 404 * 405 * new 2/97 -plb 406 */ 407 408 static void 409 scn_setchip(struct scn_softc *sc) 410 { 411 struct duart *dp; 412 u_char acr, csr, mr1, mr2; 413 int chan; 414 415 if (sc->sc_tty && (sc->sc_tty->t_state & TS_BUSY)) { 416 sc->sc_heldchanges = 1; 417 return; 418 } 419 420 chan = sc->sc_channel; 421 dp = sc->sc_duart; 422 if (dp->type == SC26C92) { 423 u_char nmr0a, mr0a; 424 425 /* input rate high enough so 64 bit time watchdog not 426 * onerous? */ 427 if (dp->chan[chan].ispeed >= 1200) { 428 /* set FIFO threshold at 6 for other 429 * thresholds we could have to set MR1_FFULL 430 */ 431 dp->chan[chan].mr0 |= MR0_RXWD | MR0_RXINT; 432 } else { 433 dp->chan[chan].mr0 &= ~(MR0_RXWD | MR0_RXINT); 434 } 435 436 /* select BRG mode (MR0A only) */ 437 nmr0a = dp->chan[0].mr0 | (dp->mode & MR0_MODE); 438 439 dp->base[CH_CR] = CR_CMD_MR0; 440 RECOVER(); 441 442 mr0a = dp->base[CH_MR]; 443 if (mr0a != nmr0a) { 444 dp->base[CH_CR] = CR_CMD_MR0; 445 RECOVER(); 446 dp->base[CH_MR] = nmr0a; 447 } 448 449 if (chan) { /* channel B? */ 450 u_char mr0b; 451 452 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 453 RECOVER(); 454 mr0b = dp->base[CH_MR]; 455 456 if (dp->chan[chan].mr0 != mr0b) { 457 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 458 RECOVER(); 459 sc->sc_chbase[CH_MR] = dp->chan[chan].mr0; 460 } 461 } 462 } else { 463 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 464 RECOVER(); 465 } 466 467 mr1 = sc->sc_chbase[CH_MR]; 468 mr2 = sc->sc_chbase[CH_MR]; 469 if (mr1 != dp->chan[chan].new_mr1 || 470 mr2 != dp->chan[chan].new_mr2) { 471 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 472 RECOVER(); 473 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr1; 474 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr2; 475 } 476 477 acr = dp->acr | (dp->mode & ACR_BRG); 478 dp->base[DU_ACR] = acr; /* write-only reg! */ 479 480 /* set speed codes */ 481 csr = (dp->chan[chan].icode<<4) | dp->chan[chan].ocode; 482 if (sc->sc_chbase[CH_CSR] != csr) { 483 sc->sc_chbase[CH_CSR] = csr; 484 } 485 486 /* see if counter/timer in use */ 487 if (dp->counter && 488 (dp->chan[0].icode == USE_CT || dp->chan[0].ocode == USE_CT || 489 dp->chan[1].icode == USE_CT || dp->chan[1].ocode == USE_CT)) { 490 491 /* program counter/timer only if necessary */ 492 if (dp->counter != dp->ocounter) { 493 uint16_t div; 494 #ifdef DIVS 495 int i; 496 497 /* look for precalculated rate, for minimum error */ 498 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { 499 if (divs[i].speed == dp->counter) { 500 div = divs[i].div; 501 goto found; 502 } 503 } 504 #endif 505 506 /* not found in table; calculate a value (rounding up) */ 507 div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter; 508 509 found: 510 /* halt before loading? may ALWAYS glitch? 511 * reload race may only sometimes glitch?? 512 */ 513 dp->base[DU_CTUR] = div >> 8; 514 dp->base[DU_CTLR] = div & 255; 515 if (dp->ocounter == 0) { 516 /* not previously used? */ 517 u_char temp; 518 /* start C/T running */ 519 temp = dp->base[DU_CSTRT]; 520 __USE(temp); 521 } 522 dp->ocounter = dp->counter; 523 } 524 } else { 525 /* counter not in use; mark as free */ 526 dp->counter = 0; 527 } 528 sc->sc_heldchanges = 0; 529 530 /* 531 * delay a tiny bit to try and avoid tx glitching. 532 * I know we're at spltty(), but this is much better than the 533 * old version used DELAY((96000 / out_speed) * 10000) 534 * -plb 535 */ 536 DELAY(10); 537 } 538 539 /* 540 * iterator function for speeds. 541 * (could be called "findnextcode") 542 * Returns sequence of possible speed codes for a given rate. 543 * should set index to zero before first call. 544 * 545 * Could be implemented as a "checkspeed()" function called 546 * to evaluate table entries, BUT this allows more variety in 547 * use of C/T with fewer table entries. 548 */ 549 550 static int 551 scniter(int *index, int wanted, int *counter, int *mode, struct chan *other, 552 int c92) 553 { 554 555 while (*index < TABENTRIES) { 556 struct tabent *tp; 557 558 tp = table + (*index)++; 559 if (tp->speed != wanted) 560 continue; 561 562 /* if not a 26C92 only look at MODE0 entries */ 563 if (!c92 && (tp->mode & MR0_MODE) != MR0_MODE_0) 564 continue; 565 566 /* 567 * check mode; 568 * OK if this table entry for current mode, or mode not 569 * yet set, or other channel's rates are available in both 570 * A and B groups. 571 */ 572 573 if (tp->mode == *mode || *mode == ANYMODE || 574 (other != NULL && (tp->mode & MR0_MODE) == (*mode & MR0_MODE) && 575 bothgroups[other->icode] && bothgroups[other->ocode])) { 576 /* 577 * for future table entries specifying 578 * use of counter/timer 579 */ 580 if (tp->code == USE_CT) { 581 if (*counter != wanted && *counter != 0) 582 continue; /* counter busy */ 583 *counter = wanted; 584 } 585 *mode = tp->mode; 586 return tp->code; 587 } 588 } 589 590 /* here after returning all applicable table entries */ 591 /* XXX return sequence of USE_CT with all possible modes?? */ 592 if ((*index)++ == TABENTRIES) { 593 /* Max C/T rate (even on 26C92?) is 57600 */ 594 if (wanted <= 57600 && (*counter == wanted || *counter == 0)) { 595 *counter = wanted; 596 return USE_CT; 597 } 598 } 599 600 return -1; /* FAIL */ 601 } 602 603 /* 604 * calculate configuration 605 * rewritten 2/97 -plb 606 */ 607 static int 608 scn_config(int unit, int chan, int ispeed, int ospeed, u_char mr1, u_char mr2) 609 { 610 struct scn_softc *sc; 611 struct duart *dp; 612 int other; /* opposite of chan */ 613 int mode; 614 int counter; 615 int i, o; /* input, output iterator indexes */ 616 int ic, oc; /* input, output codes */ 617 struct chan *ocp; /* other duart channel */ 618 struct tty *otp; /* other channel tty struct */ 619 int c92; /* true if duart is sc26c92 */ 620 int s; 621 622 /* Set up softc pointer. */ 623 if (unit >= scn_cd.cd_ndevs) 624 return ENXIO; 625 sc = SOFTC(unit); 626 chan = sc->sc_channel; 627 other = chan ^ 1; 628 dp = sc->sc_duart; 629 ocp = &dp->chan[other]; 630 otp = ocp->tty; 631 c92 = (dp->type == SC26C92); 632 633 /* 634 * Right now the first combination that works is used. 635 * Perhaps it should search entire solution space for "best" 636 * combination. For example, use heuristic weighting of mode 637 * preferences, and use of counter timer? 638 * 639 * For example right now with 2681/2692 when default rate is 640 * 9600 and other channel is closed setting 19200 will pick 641 * mode 0a and use counter/timer. Better solution might be 642 * mode 0b, leaving counter/timer free! 643 * 644 * When other channel is open might want to prefer 645 * leaving counter timer free, or not flipping A/B group? 646 */ 647 if (otp && (otp->t_state & TS_ISOPEN)) { 648 649 /* 650 * Other channel open; 651 * Find speed codes compatible with current mode/counter. 652 */ 653 654 i = 0; 655 for (;;) { 656 mode = dp->mode; 657 counter = dp->counter; 658 659 /* NOTE: pass other chan pointer to allow group flipping */ 660 ic = scniter(&i, ispeed, &counter, &mode, ocp, c92); 661 if (ic == -1) 662 break; 663 664 o = 0; 665 if ((oc = scniter(&o, ospeed, &counter, 666 &mode, NULL, c92)) != -1) { 667 /* 668 * take first match 669 * 670 * Perhaps calculate heuristic "score", 671 * save score,codes,mode,counter if score 672 * better than previous best? 673 */ 674 goto gotit; 675 } 676 } 677 /* XXX try looping for ospeed? */ 678 } else { 679 /* other channel closed */ 680 int oo, oi; /* other input, output iterators */ 681 int oic, ooc; /* other input, output codes */ 682 683 /* 684 * Here when other channel closed. Finds first 685 * combination that will allow other channel to be opened 686 * (with defaults) and fits our needs. 687 */ 688 oi = 0; 689 for (;;) { 690 mode = ANYMODE; 691 counter = 0; 692 693 oic = scniter(&oi, ocp->ispeed, &counter, &mode, NULL, c92); 694 if (oic == -1) 695 break; 696 697 oo = 0; 698 while ((ooc = scniter(&oo, ocp->ospeed, &counter, 699 &mode, NULL, c92)) != -1) { 700 i = 0; 701 while ((ic = scniter(&i, ispeed, &counter, 702 &mode, NULL, c92)) != -1) { 703 o = 0; 704 if ((oc = scniter(&o, ospeed, &counter, 705 &mode, NULL, c92)) != -1) { 706 /* 707 * take first match 708 * 709 * Perhaps calculate heuristic 710 * "score", save 711 * score,codes,mode,counter 712 * if score better than 713 * previous best? 714 */ 715 s = spltty(); 716 dp->chan[other].icode = oic; 717 dp->chan[other].ocode = ooc; 718 goto gotit2; 719 } 720 } 721 } 722 } 723 } 724 return EINVAL; 725 726 gotit: 727 s = spltty(); 728 gotit2: 729 dp->chan[chan].new_mr1 = mr1; 730 dp->chan[chan].new_mr2 = mr2; 731 dp->chan[chan].ispeed = ispeed; 732 dp->chan[chan].ospeed = ospeed; 733 dp->chan[chan].icode = ic; 734 dp->chan[chan].ocode = oc; 735 if (mode == ANYMODE) /* no mode selected?? */ 736 mode = DEFMODE(c92); 737 dp->mode = mode; 738 dp->counter = counter; 739 740 scn_setchip(sc); /* set chip now, if possible */ 741 splx(s); 742 return (0); 743 } 744 745 int 746 scn_match(device_t parent, struct cfdata *cf, void *aux) 747 { 748 struct mainbus_attach_args *ma = aux; 749 750 if ((mach_type == MACH_SGI_IP6 || mach_type == MACH_SGI_IP10) && 751 ma->ma_addr == 0x1fb80004) 752 return (1); 753 754 return (0); 755 } 756 757 /* 758 * No need to make scn_rx{en,dis}able too efficient, 759 * they're only called on setup, open & close! 760 */ 761 static inline void 762 scn_rxenable(struct scn_softc *sc) 763 { 764 struct duart *dp; 765 int channel; 766 767 dp = sc->sc_duart; 768 channel = sc->sc_channel; 769 770 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 771 if (channel == 0) 772 dp->opcr |= OPCR_OP4_RXRDYA; 773 else 774 dp->opcr |= OPCR_OP5_RXRDYB; 775 dp->base[DU_OPCR] = dp->opcr; 776 dp->imr |= sc->sc_rx_int; 777 dp->base[DU_IMR] = dp->imr; 778 } 779 780 static inline void 781 scn_rxdisable(struct scn_softc *sc) 782 { 783 struct duart *dp; 784 int channel; 785 786 dp = sc->sc_duart; 787 channel = sc->sc_channel; 788 789 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 790 if (channel == 0) 791 dp->opcr &= ~OPCR_OP4_RXRDYA; 792 else 793 dp->opcr &= ~OPCR_OP5_RXRDYB; 794 dp->base[DU_OPCR] = dp->opcr; 795 dp->imr &= ~sc->sc_rx_int; 796 dp->base[DU_IMR] = dp->imr; 797 } 798 799 void 800 scn_attach(device_t parent, device_t self, void *aux) 801 { 802 struct mainbus_attach_args *ma = aux; 803 struct scn_softc *sc; 804 struct duart *duart; 805 volatile u_char *ch_base; 806 volatile u_char *duart_base; 807 int channel; 808 int speed; 809 int s; 810 int maj __diagused; 811 u_char unit; 812 u_char duartno; 813 u_char delim = ':'; 814 u_char mr1, mr2; 815 enum scntype scntype = SCNUNK; 816 const char *duart_type = "Unknown"; 817 char *intrname; 818 bool console, first; 819 devmajor_t major; 820 821 (void)major; 822 823 sc = device_private(self); 824 unit = device_unit(self); 825 826 /* XXX - hard-coded */ 827 if (ma->ma_addr == 0x1fb80004) 828 duartno = 1; 829 else 830 duartno = 0; 831 channel = 0; 832 console = 1; 833 834 duart = sc->sc_duart = &scn_duart[duartno]; 835 duart->chan[channel].sc = sc; 836 first = (duart->base == NULL); 837 838 if (console) { 839 sc->sc_isconsole = 1; 840 sc->sc_swflags |= SCN_SW_SOFTCAR; /* ignore carrier */ 841 } 842 843 duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr); 844 ch_base = duart_base; /* XXX */ 845 846 if (first) { 847 /* Probe DUART type */ 848 s = spltty(); 849 if (console) { 850 ch_base[CH_CR] = CR_DIS_TX; 851 delay(5 * 10000); 852 } 853 ch_base[CH_CR] = CR_CMD_MR1; 854 RECOVER(); 855 mr1 = ch_base[CH_MR]; 856 mr2 = ch_base[CH_MR]; 857 ch_base[CH_CR] = CR_CMD_MR1; 858 RECOVER(); 859 ch_base[CH_MR] = 1; 860 ch_base[CH_MR] = 0; 861 ch_base[CH_CR] = CR_CMD_MR1; 862 RECOVER(); 863 if (ch_base[CH_MR] == 1) { 864 /* MR 2 selected */ 865 ch_base[CH_CR] = CR_CMD_MR0; 866 RECOVER(); 867 /* if 2681, MR2 still selected */ 868 ch_base[CH_MR] = 1; 869 ch_base[CH_CR] = CR_CMD_MR1; 870 RECOVER(); 871 ch_base[CH_MR] = 0; /* MR1 */ 872 ch_base[CH_MR] = 0; /* MR2 */ 873 ch_base[CH_CR] = CR_CMD_MR0; 874 RECOVER(); 875 /* if 2681, MR2 still selected */ 876 if((ch_base[CH_MR] & 1) == 1) { 877 duart_type = "sc26c92"; 878 scntype = SC26C92; 879 } else { 880 /* 2681 treats as MR1 Select */ 881 ch_base[CH_CR] = CR_CMD_RTS_OFF; 882 RECOVER(); 883 ch_base[CH_MR] = 1; 884 ch_base[CH_MR] = 0; 885 ch_base[CH_CR] = CR_CMD_RTS_OFF; 886 RECOVER(); 887 if (ch_base[CH_MR] == 1) { 888 duart_type = "scn2681"; 889 scntype = SCN2681; 890 } else { 891 duart_type = "scn2692"; 892 scntype = SCN2692; 893 } 894 } 895 } 896 897 /* If a 2681, the CR_CMD_MR0 is interpreted as a TX_RESET */ 898 if (console) { 899 ch_base[CH_CR] = CR_ENA_TX; 900 RECOVER(); 901 } 902 ch_base[CH_CR] = CR_CMD_MR1; 903 RECOVER(); 904 ch_base[CH_MR] = mr1; 905 ch_base[CH_MR] = mr2; 906 splx(s); 907 908 intrname = malloc(sizeof("scnXX"), M_DEVBUF, M_NOWAIT); 909 snprintf(intrname, sizeof("scnXX"), "scn%d", unit); 910 911 /* 912 * On IP6 the console chip is duart1. The keyboard/mouse 913 * is duart0. Each chip has two channels and the channels 914 * share an interrupt. Duart0 is interrupt 0, duart1 is 915 * interrupt 1. 916 */ 917 if (duartno != 0 && duartno != 1) 918 panic("scn_attach: bad duartno: %d", duartno); 919 cpu_intr_establish(duartno, IPL_TTY, scnintr, duart); 920 921 printf("%c %s", delim, duart_type); 922 delim = ','; 923 924 duart->base = duart_base; 925 duart->type = scntype; 926 } 927 /* Record channel, uart */ 928 sc->sc_channel = channel; 929 sc->sc_chbase = ch_base; 930 931 /* Initialize modem/interrupt bit masks */ 932 if (channel == 0) { 933 sc->sc_op_rts = OP_RTSA; 934 sc->sc_op_dtr = OP_DTRA; 935 sc->sc_ip_cts = IP_CTSA; 936 sc->sc_ip_dcd = IP_DCDA; 937 938 sc->sc_tx_int = INT_TXA; 939 sc->sc_rx_int = INT_RXA; 940 } else { 941 sc->sc_op_rts = OP_RTSB; 942 sc->sc_op_dtr = OP_DTRB; 943 sc->sc_ip_cts = IP_CTSB; 944 sc->sc_ip_dcd = IP_DCDB; 945 946 sc->sc_tx_int = INT_TXB; 947 sc->sc_rx_int = INT_RXB; 948 } 949 950 /* Initialize counters */ 951 sc->sc_framing_errors = 0; 952 sc->sc_fifo_overruns = 0; 953 sc->sc_parity_errors = 0; 954 sc->sc_breaks = 0; 955 956 if (console) { 957 DELAY(5 * 10000); /* Let the output go out.... */ 958 } 959 960 /* 961 * Set up the hardware to a base state, in particular: 962 * o reset transmitter and receiver 963 * o set speeds and configurations 964 * o receiver interrupts only (RxRDY and BREAK) 965 */ 966 967 s = spltty(); 968 /* RTS off... */ 969 SCN_OP_BIC(sc, sc->sc_op_rts); /* "istop" */ 970 971 ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX; 972 RECOVER(); 973 ch_base[CH_CR] = CR_CMD_RESET_RX; 974 RECOVER(); 975 ch_base[CH_CR] = CR_CMD_RESET_TX; 976 RECOVER(); 977 ch_base[CH_CR] = CR_CMD_RESET_ERR; 978 RECOVER(); 979 ch_base[CH_CR] = CR_CMD_RESET_BRK; 980 RECOVER(); 981 ch_base[CH_CR] = CR_CMD_MR1; 982 RECOVER(); 983 984 /* No receiver control of RTS. */ 985 ch_base[CH_MR] = 0; 986 ch_base[CH_MR] = 0; 987 988 /* Initialize the uart structure if this is channel A. */ 989 if (first) { 990 /* Disable all interrupts. */ 991 duart_base[DU_IMR] = duart->imr = 0; 992 993 /* Output port config */ 994 duart_base[DU_OPCR] = duart->opcr = 0; 995 996 /* Speeds... */ 997 duart->mode = 0; 998 999 /* 1000 * Set initial speed to an illegal code that can be changed to 1001 * any other baud. 1002 */ 1003 duart->chan[0].icode = duart->chan[0].ocode = 0x2f; 1004 duart->chan[1].icode = duart->chan[1].ocode = 0x2f; 1005 duart->chan[0].ispeed = duart->chan[0].ospeed = 0; 1006 duart->chan[1].ispeed = duart->chan[1].ospeed = 0; 1007 1008 duart->acr = 0; 1009 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */ 1010 } 1011 1012 if (channel == 0) { 1013 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */ 1014 } else { 1015 duart->acr |= ACR_DELTA_DCDB; /* Set CD int */ 1016 } 1017 1018 if (scnsir == NULL) { 1019 /* software intr: calls tty code, hence IPL_TTY */ 1020 scnsir = softint_establish(SOFTINT_SERIAL, scnsoft, NULL); 1021 } 1022 1023 duart_base[DU_ACR] = (duart->mode & ACR_BRG) | duart->acr; 1024 1025 if (console) 1026 speed = scnconsrate; 1027 else 1028 speed = scndefaultrate; 1029 1030 scn_config(unit, channel, speed, speed, MR1_PNONE | MR1_CS8, MR2_STOP1); 1031 if (console) { 1032 maj = cdevsw_lookup_major(&scn_cdevsw); 1033 KASSERT(maj != NODEVMAJOR); 1034 shutdownhook_establish(scncnreinit, NULL); 1035 /* Make sure console can do scncngetc */ 1036 duart_base[DU_OPSET] = channel ? (OP_RTSB | OP_DTRB) : 1037 (OP_RTSA | OP_DTRA); 1038 } 1039 1040 /* Turn on the receiver and transmitters */ 1041 ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX; 1042 1043 /* Set up the interrupts. */ 1044 duart->imr |= INT_IP; 1045 scn_rxdisable(sc); 1046 splx(s); 1047 1048 if (sc->sc_swflags) { 1049 printf("%c flags %d", delim, sc->sc_swflags); 1050 delim = ','; 1051 } 1052 1053 #ifdef KGDB 1054 major = cdevsw_lookup_major(&scn_cdevsw); 1055 KASSERT(major != NODEVMAJOR); 1056 if (kgdb_dev == makedev(major, unit)) { 1057 if (console) 1058 kgdb_dev = NODEV; /* can't debug over console port */ 1059 else { 1060 scninit(kgdb_dev, kgdb_rate); 1061 scn_rxenable(sc); 1062 scn->sc_iskgdb = 1; 1063 kgdb_attach(scncngetc, scncnputc, kgdb_dev); 1064 if (kgdb_debug_init) { 1065 printf("%c ", delim); 1066 kgdb_connect(1); 1067 } else 1068 printf("%c kgdb enabled", delim); 1069 delim = ','; 1070 } 1071 } 1072 #endif 1073 printf("\n"); 1074 } 1075 1076 /* ARGSUSED */ 1077 int 1078 scnopen(dev_t dev, int flags, int mode, struct lwp *l) 1079 { 1080 struct tty *tp; 1081 int unit = DEV_UNIT(dev); 1082 struct scn_softc *sc; 1083 int error = 0; 1084 1085 if (unit >= scn_cd.cd_ndevs) 1086 return ENXIO; 1087 sc = SOFTC(unit); 1088 if (!sc) 1089 return ENXIO; 1090 1091 tp = sc->sc_tty; 1092 if (!tp) { 1093 tp = tty_alloc(); 1094 sc->sc_tty = sc->sc_duart->chan[sc->sc_channel].tty = tp; 1095 tty_attach(tp); 1096 } 1097 1098 tp->t_oproc = scnstart; 1099 tp->t_param = scnparam; 1100 tp->t_hwiflow = scnhwiflow; 1101 tp->t_dev = dev; 1102 1103 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1104 return (EBUSY); 1105 1106 mutex_spin_enter(&tty_lock); 1107 1108 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1109 ttychars(tp); 1110 tp->t_iflag = TTYDEF_IFLAG; 1111 tp->t_oflag = TTYDEF_OFLAG; 1112 tp->t_cflag = SCNDEF_CFLAG; 1113 1114 sc->sc_rx_blocked = 0; 1115 1116 if (sc->sc_swflags & SCN_SW_CLOCAL) 1117 tp->t_cflag |= CLOCAL; 1118 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1119 tp->t_cflag |= CCTS_OFLOW | CRTS_IFLOW; 1120 tp->t_lflag = TTYDEF_LFLAG; 1121 if (sc->sc_isconsole) 1122 tp->t_ispeed = tp->t_ospeed = scnconsrate; 1123 else 1124 tp->t_ispeed = tp->t_ospeed = scndefaultrate; 1125 scnparam(tp, &tp->t_termios); 1126 ttsetwater(tp); 1127 1128 /* Turn on DTR and RTS. */ 1129 SCN_OP_BIS(sc, sc->sc_op_rts | sc->sc_op_dtr); 1130 1131 /* enable receiver interrupts */ 1132 scn_rxenable(sc); 1133 1134 /* set carrier state; */ 1135 if ((sc->sc_swflags & SCN_SW_SOFTCAR) || /* check ttyflags */ 1136 SCN_DCD(sc) || /* check h/w */ 1137 DEV_DIALOUT(dev)) 1138 tp->t_state |= TS_CARR_ON; 1139 else 1140 tp->t_state &= ~TS_CARR_ON; 1141 } 1142 1143 mutex_spin_exit(&tty_lock); 1144 1145 error = ttyopen(tp, SCN_DIALOUT(sc), flags & O_NONBLOCK); 1146 if (error) printf("ttyopen failed line %d, error %d\n", __LINE__, error); 1147 if (error) 1148 goto bad; 1149 1150 error = (*tp->t_linesw->l_open) (dev, tp); 1151 if (error) printf("l_open failed line %d, error %d\n", __LINE__, error); 1152 if (error) 1153 goto bad; 1154 1155 return (0); 1156 1157 bad: 1158 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1159 scn_rxdisable(sc); 1160 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1161 } 1162 1163 return (error); 1164 } 1165 1166 1167 /*ARGSUSED*/ 1168 int 1169 scnclose(dev_t dev, int flags, int mode, struct lwp *l) 1170 { 1171 int unit = DEV_UNIT(dev); 1172 struct scn_softc *sc = SOFTC(unit); 1173 struct tty *tp = sc->sc_tty; 1174 devmajor_t major; 1175 1176 (void)major; 1177 1178 if ((tp->t_state & TS_ISOPEN) == 0) 1179 return 0; 1180 1181 (*tp->t_linesw->l_close) (tp, flags); 1182 1183 #ifdef KGDB 1184 /* do not disable interrupts if debugging */ 1185 major = cdevsw_lookup_major(&scn_devsw); 1186 KASSERT(major != cdevsw_lookup_major); 1187 if (kgdb_dev != makedev(major, unit)) 1188 #endif 1189 if ((tp->t_state & TS_ISOPEN) == 0) { 1190 scn_rxdisable(sc); 1191 } 1192 if ((tp->t_cflag & HUPCL) && (sc->sc_swflags & SCN_SW_SOFTCAR) == 0) { 1193 SCN_OP_BIC(sc, sc->sc_op_dtr); 1194 /* hold low for 1 second */ 1195 tsleep(sc, TTIPRI, ttclos, hz); 1196 } 1197 SCN_CLRDIALOUT(sc); 1198 ttyclose(tp); 1199 1200 #if 0 1201 if ((tp->t_state & TS_ISOPEN) == 0) { 1202 tty_free(tp); 1203 sc->sc_tty = (struct tty *) NULL; 1204 } 1205 #endif 1206 1207 return (0); 1208 } 1209 1210 int 1211 scnread(dev_t dev, struct uio *uio, int flags) 1212 { 1213 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1214 struct tty *tp = sc->sc_tty; 1215 1216 return ((*tp->t_linesw->l_read) (tp, uio, flags)); 1217 } 1218 1219 int 1220 scnwrite(dev_t dev, struct uio *uio, int flags) 1221 { 1222 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1223 struct tty *tp = sc->sc_tty; 1224 1225 return ((*tp->t_linesw->l_write) (tp, uio, flags)); 1226 } 1227 1228 int 1229 scnpoll(dev_t dev, int events, struct lwp *l) 1230 { 1231 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1232 struct tty *tp = sc->sc_tty; 1233 1234 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1235 } 1236 1237 struct tty * 1238 scntty(dev_t dev) 1239 { 1240 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1241 1242 return sc->sc_tty; 1243 } 1244 1245 /* Worker routines for interrupt processing */ 1246 static inline void 1247 dcd_int(struct scn_softc *sc, struct tty *tp, u_char new) 1248 { 1249 1250 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1251 return; 1252 1253 #if 0 1254 printf("scn%d: dcd_int ip %x SCN_DCD %x new %x ipcr %x\n", 1255 sc->unit, 1256 sc->sc_duart->base[DU_IP], 1257 SCN_DCD(sc), 1258 new, 1259 sc->sc_duart->base[DU_IPCR] 1260 ); 1261 #endif 1262 1263 /* XXX set some flag to have some lower (soft) int call line discipline? */ 1264 if (!(*tp->t_linesw->l_modem) (tp, new == 0? 1: 0)) { 1265 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1266 } 1267 } 1268 1269 /* 1270 * Print out a ring or fifo overrun error message. 1271 */ 1272 static void 1273 scnoverrun(int unit, long *ptime, const char *what) 1274 { 1275 1276 if (*ptime != time_second) { 1277 *ptime = time_second; 1278 log(LOG_WARNING, "scn%d: %s overrun\n", unit, what); 1279 } 1280 } 1281 1282 /* 1283 * Try to block or unblock input using hardware flow-control. 1284 * This is called by kern/tty.c if MDMBUF|CRTSCTS is set, and 1285 * if this function returns non-zero, the TS_TBLOCK flag will 1286 * be set or cleared according to the "stop" arg passed. 1287 */ 1288 int 1289 scnhwiflow(struct tty *tp, int stop) 1290 { 1291 int unit = DEV_UNIT(tp->t_dev); 1292 struct scn_softc *sc = SOFTC(unit); 1293 int s; 1294 1295 s = splrtty(); 1296 if (!stop) { 1297 if (sc->sc_rbput - sc->sc_rbget - 1) { 1298 setsoftscn(); 1299 } 1300 } 1301 splx(s); 1302 return 1; 1303 } 1304 1305 static int 1306 scnintr(void *arg) 1307 { 1308 struct duart *duart = arg; 1309 struct scn_softc *sc0 = duart->chan[0].sc; 1310 struct scn_softc *sc1 = duart->chan[1].sc; 1311 1312 struct tty *tp0 = (sc0 != NULL) ? sc0->sc_tty : NULL; 1313 struct tty *tp1 = (sc1 != NULL) ? sc1->sc_tty : NULL; 1314 1315 char rs_work; 1316 u_char rs_stat; 1317 u_char rs_ipcr; 1318 1319 /* Check for RX interrupts first, since we cannot distinguish by irq. */ 1320 scnrxintr(duart); 1321 1322 do { 1323 /* Loop to pick up ALL pending interrupts for device. */ 1324 rs_work = false; 1325 rs_stat = duart->base[DU_ISR]; 1326 1327 /* channel a */ 1328 if (tp0 != NULL) { 1329 if ((rs_stat & INT_TXA) && (tp0->t_state & TS_BUSY)) { 1330 /* output char done. */ 1331 tp0->t_state &= ~(TS_BUSY | TS_FLUSH); 1332 1333 /* disable tx ints */ 1334 duart->imr &= ~sc0->sc_tx_int; 1335 duart->base[DU_IMR] = duart->imr; 1336 1337 if (sc0->sc_heldchanges) { 1338 scn_setchip(sc0); 1339 } 1340 1341 (*tp0->t_linesw->l_start) (tp0); 1342 rs_work = true; 1343 } 1344 } 1345 /* channel b */ 1346 if (tp1 != NULL) { 1347 if ((rs_stat & INT_TXB) && (tp1->t_state & TS_BUSY)) { 1348 /* output char done. */ 1349 tp1->t_state &= ~(TS_BUSY | TS_FLUSH); 1350 1351 /* disable tx ints */ 1352 duart->imr &= ~sc1->sc_tx_int; 1353 duart->base[DU_IMR] = duart->imr; 1354 1355 if (sc1->sc_heldchanges) { 1356 scn_setchip(sc1); 1357 } 1358 1359 (*tp1->t_linesw->l_start) (tp1); 1360 rs_work = true; 1361 } 1362 } 1363 if (rs_stat & INT_IP) { 1364 rs_work = true; 1365 rs_ipcr = duart->base[DU_IPCR]; 1366 1367 if (rs_ipcr & IPCR_DELTA_DCDA && tp0 != NULL) { 1368 dcd_int(sc0, tp0, rs_ipcr & IPCR_DCDA); 1369 } 1370 if (rs_ipcr & IPCR_DELTA_DCDB && tp1 != NULL) { 1371 dcd_int(sc1, tp1, rs_ipcr & IPCR_DCDB); 1372 } 1373 } 1374 } while (rs_work); 1375 1376 return (1); /* ? */ 1377 } 1378 1379 /* 1380 * Handle rxrdy/ffull interrupt: QUICKLY poll both channels (checking 1381 * status first) and stash data in a ring buffer. Ring buffer scheme 1382 * borowed from sparc/zs.c requires NO interlock on data! 1383 * 1384 * This interrupt should NOT be included in spltty() mask since it 1385 * invokes NO tty code! The whole point is to allow tty input as much 1386 * of the time as possible, while deferring "heavy" character 1387 * processing until later. 1388 * 1389 * see scn.hw.README and scnsoft() for more info. 1390 * 1391 * THIS ROUTINE SHOULD BE KEPT AS CLEAN AS POSSIBLE!! 1392 * IT'S A CANDIDATE FOR RECODING IN ASSEMBLER!! 1393 */ 1394 static inline int 1395 scn_rxintr(struct scn_softc *sc) 1396 { 1397 char sr; 1398 int i, n; 1399 int work; 1400 1401 work = 0; 1402 i = sc->sc_rbput; 1403 while (work <= 10) { 1404 #define SCN_GETCH(SC) \ 1405 sr = (SC)->sc_chbase[CH_SR]; \ 1406 if ((sr & SR_RX_RDY) == 0) \ 1407 break; \ 1408 if (sr & (SR_PARITY | SR_FRAME | SR_BREAK | SR_OVERRUN)) \ 1409 goto exception; \ 1410 work++; \ 1411 (SC)->sc_rbuf[i++ & SCN_RING_MASK] = (SC)->sc_chbase[CH_DAT] 1412 1413 SCN_GETCH(sc); SCN_GETCH(sc); SCN_GETCH(sc); 1414 /* XXX more here if 26C92? -plb */ 1415 continue; 1416 exception: 1417 #if defined(DDB) 1418 if (sc->sc_isconsole && (sr & SR_BREAK)) { 1419 Debugger(); 1420 sr = sc->sc_chbase[CH_SR]; 1421 } 1422 #endif 1423 #if defined(KGDB) 1424 if (sc->sc_iskgdb && (sr & SR_RX_RDY)) { 1425 kgdb_connect(1); 1426 sr = sc->sc_chbase[CH_SR]; 1427 } 1428 #endif 1429 work++; 1430 sc->sc_rbuf[i++ & SCN_RING_MASK] = (sr << 8) | sc->sc_chbase[CH_DAT]; 1431 sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */ 1432 RECOVER(); 1433 } 1434 /* 1435 * If ring is getting too full, try to block input. 1436 */ 1437 n = i - sc->sc_rbget; 1438 if (sc->sc_rbhiwat && (n > sc->sc_rbhiwat)) { 1439 /* If not CRTSCTS sc_rbhiwat is such that this 1440 * never happens. 1441 * Clear RTS 1442 */ 1443 SCN_OP_BIC(sc, sc->sc_op_rts); 1444 sc->sc_rx_blocked = 1; 1445 } 1446 sc->sc_rbput = i; 1447 1448 return work; 1449 } 1450 1451 static void 1452 scnrxintr(void *arg) 1453 { 1454 struct duart *duart = arg; 1455 int work = 0; 1456 1457 if (duart->chan[0].sc != NULL) 1458 work += scn_rxintr(duart->chan[0].sc); 1459 if (duart->chan[1].sc != NULL) 1460 work += scn_rxintr(duart->chan[1].sc); 1461 if (work > 0) { 1462 setsoftscn(); /* trigger s/w intr */ 1463 #ifdef SCN_TIMING 1464 microtime(&tstart); 1465 #endif 1466 } 1467 } 1468 1469 /* 1470 * Here on soft interrupt (at spltty) to empty ring buffers. 1471 * 1472 * Dave's original scheme was to use the DUART receiver timeout 1473 * interrupt. This requires 2692's (which my board doesn't have), and 1474 * I also liked the idea of using the C/T to generate alternate and/or 1475 * arbitrary bauds. -plb 1476 * 1477 * The ringbuffer code comes from Chris Torek's SPARC 44bsd zs driver 1478 * (hence the LBL notice on top of this file), DOES NOT require 1479 * interlocking with interrupt levels! 1480 * 1481 * The 44bsd sparc/zs driver reads the ring buffer from a separate 1482 * zssoftint, while the SunOS 4.x zs driver appears to use 1483 * timeout()'s. timeouts seem to be too slow to deal with high data 1484 * rates. I know, I tried them. 1485 * -plb. 1486 */ 1487 static void 1488 scnsoft(void *arg) 1489 { 1490 int s, unit; 1491 #ifdef SCN_TIMING 1492 struct timeval tend; 1493 u_long t; 1494 1495 microtime(&tend); 1496 t = (tend.tv_sec - tstart.tv_sec) * 1000000 + (tend.tv_usec - tstart.tv_usec); 1497 t = (t + tick / 20) / (tick / 10); 1498 if (t >= NJITTER - 1) { 1499 t = NJITTER - 1; 1500 } 1501 scn_jitter[t]++; 1502 #endif 1503 1504 for (unit = 0; unit < scn_cd.cd_ndevs; unit++) { 1505 struct scn_softc *sc; 1506 struct tty *tp; 1507 int n, get; 1508 1509 sc = SOFTC(unit); 1510 if (sc == NULL) { 1511 continue; 1512 } 1513 tp = sc->sc_tty; 1514 #ifdef KGDB 1515 if (tp == NULL) { 1516 sc->sc_rbget = sc->sc_rbput; 1517 continue; 1518 } 1519 #endif 1520 if (tp == NULL || tp->t_state & TS_TBLOCK) { 1521 continue; 1522 } 1523 1524 1525 get = sc->sc_rbget; 1526 1527 /* NOTE: fetch from rbput is atomic */ 1528 while (get != (n = sc->sc_rbput)) { 1529 /* 1530 * Compute the number of interrupts in the receive ring. 1531 * If the count is overlarge, we lost some events, and 1532 * must advance to the first valid one. It may get 1533 * overwritten if more data are arriving, but this is 1534 * too expensive to check and gains nothing (we already 1535 * lost out; all we can do at this point is trade one 1536 * kind of loss for another). 1537 */ 1538 n -= get; 1539 if (n > SCN_RING_SIZE) { 1540 scnoverrun(unit, &sc->sc_rotime, "ring"); 1541 get += n - SCN_RING_SIZE; 1542 n = SCN_RING_SIZE; 1543 sc->sc_ring_overruns++; 1544 } 1545 while (--n >= 0) { 1546 int c, sr; 1547 1548 if (tp->t_state & TS_TBLOCK) { 1549 sc->sc_rbget = get; 1550 goto done; 1551 } 1552 /* Race to keep ahead of incoming interrupts. */ 1553 c = sc->sc_rbuf[get++ & SCN_RING_MASK]; 1554 1555 sr = c >> 8; /* extract status */ 1556 c &= 0xff; /* leave just character */ 1557 1558 if (sr & SR_OVERRUN) { 1559 scnoverrun(unit, &sc->sc_fotime, "fifo"); 1560 sc->sc_fifo_overruns++; 1561 } 1562 if (sr & SR_PARITY) { 1563 c |= TTY_PE; 1564 sc->sc_parity_errors++; 1565 } 1566 if (sr & SR_FRAME) { 1567 c |= TTY_FE; 1568 sc->sc_framing_errors++; 1569 } 1570 if (sr & SR_BREAK) { 1571 #if 0 1572 /* 1573 * See DDB_CHECK() comments in 1574 * scnrxintr() 1575 */ 1576 if (sc->sc_isconsole) 1577 Debugger(); 1578 #endif 1579 c = TTY_FE | 0; 1580 sc->sc_breaks++; 1581 } 1582 1583 (*tp->t_linesw->l_rint) (c, tp); 1584 1585 if (sc->sc_rx_blocked && n < SCN_RING_THRESH) { 1586 s = splrtty(); 1587 sc->sc_rx_blocked = 0; 1588 SCN_OP_BIS(sc, sc->sc_op_rts); 1589 splx(s); 1590 } 1591 1592 } 1593 sc->sc_rbget = get; 1594 } 1595 done: ; 1596 } 1597 } 1598 1599 /* Convert TIOCM_xxx bits to output port bits. */ 1600 static unsigned char 1601 opbits(struct scn_softc *sc, int tioc_bits) 1602 { 1603 1604 return ((((tioc_bits) & TIOCM_DTR) ? sc->sc_op_dtr : 0) | 1605 (((tioc_bits) & TIOCM_RTS) ? sc->sc_op_rts : 0)); 1606 } 1607 1608 int 1609 scnioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1610 { 1611 int unit = DEV_UNIT(dev); 1612 struct scn_softc *sc = SOFTC(unit); 1613 struct tty *tp = sc->sc_tty; 1614 int error; 1615 1616 error = (*tp->t_linesw->l_ioctl) (tp, cmd, data, flags, l); 1617 if (error != EPASSTHROUGH) 1618 return (error); 1619 1620 error = ttioctl(tp, cmd, data, flags, l); 1621 if (error != EPASSTHROUGH) 1622 return (error); 1623 1624 switch (cmd) { 1625 case TIOCSBRK: 1626 sc->sc_chbase[CH_CR] = CR_CMD_START_BRK; 1627 break; 1628 1629 case TIOCCBRK: 1630 sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK; 1631 break; 1632 1633 case TIOCSDTR: 1634 SCN_OP_BIS(sc, sc->sc_op_dtr | sc->sc_op_rts); 1635 break; 1636 1637 case TIOCCDTR: 1638 SCN_OP_BIC(sc, sc->sc_op_dtr | sc->sc_op_rts); 1639 break; 1640 1641 case TIOCMSET: { 1642 int s; 1643 unsigned char sbits, cbits; 1644 1645 /* set bits */ 1646 sbits = opbits(sc, *(int *) data); 1647 1648 /* get bits to clear */ 1649 cbits = ~sbits & (sc->sc_op_dtr | sc->sc_op_rts); 1650 1651 s = spltty(); 1652 if (sbits) { 1653 SCN_OP_BIS(sc, sbits); 1654 } 1655 if (cbits) { 1656 SCN_OP_BIC(sc, cbits); 1657 } 1658 splx(s); 1659 break; 1660 } 1661 1662 case TIOCMBIS: 1663 SCN_OP_BIS(sc, opbits(sc, *(int *) data)); 1664 break; 1665 1666 case TIOCMBIC: 1667 SCN_OP_BIC(sc, opbits(sc, *(int *) data)); 1668 break; 1669 1670 case TIOCMGET: { 1671 int bits; 1672 unsigned char ip; 1673 1674 /* s = spltty(); */ 1675 ip = sc->sc_duart->base[DU_IP]; 1676 /* splx(s); */ 1677 1678 bits = 0; 1679 if (ip & sc->sc_ip_dcd) 1680 bits |= TIOCM_CD; 1681 if (ip & sc->sc_ip_cts) 1682 bits |= TIOCM_CTS; 1683 1684 #if 0 1685 /* 1686 * XXX sigh; cannot get op current state!! even if 1687 * maintained in private, RTS is done in h/w!! 1688 */ 1689 unsigned char op = 0; 1690 if (op & sc->sc_op_dtr) 1691 bits |= TIOCM_DTR; 1692 if (op & sc->sc_op_rts) 1693 bits |= TIOCM_RTS; 1694 #endif 1695 1696 *(int *) data = bits; 1697 break; 1698 } 1699 1700 case TIOCGFLAGS:{ 1701 int bits = 0; 1702 1703 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1704 bits |= TIOCFLAG_SOFTCAR; 1705 if (sc->sc_swflags & SCN_SW_CLOCAL) 1706 bits |= TIOCFLAG_CLOCAL; 1707 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1708 bits |= TIOCFLAG_CRTSCTS; 1709 if (sc->sc_swflags & SCN_SW_MDMBUF) 1710 bits |= TIOCFLAG_MDMBUF; 1711 1712 *(int *) data = bits; 1713 break; 1714 } 1715 case TIOCSFLAGS:{ 1716 int userbits, driverbits = 0; 1717 1718 error = kauth_authorize_device_tty(l->l_cred, 1719 KAUTH_DEVICE_TTY_PRIVSET, tp); 1720 if (error != 0) 1721 return (EPERM); 1722 1723 userbits = *(int *) data; 1724 if (userbits & TIOCFLAG_SOFTCAR) 1725 driverbits |= SCN_SW_SOFTCAR; 1726 if (userbits & TIOCFLAG_CLOCAL) 1727 driverbits |= SCN_SW_CLOCAL; 1728 if (userbits & TIOCFLAG_CRTSCTS) 1729 driverbits |= SCN_SW_CRTSCTS; 1730 if (userbits & TIOCFLAG_MDMBUF) 1731 driverbits |= SCN_SW_MDMBUF; 1732 1733 sc->sc_swflags = driverbits; 1734 1735 break; 1736 } 1737 1738 default: 1739 return (EPASSTHROUGH); 1740 } 1741 return (0); 1742 } 1743 1744 int 1745 scnparam(struct tty *tp, struct termios *t) 1746 { 1747 int cflag = t->c_cflag; 1748 int unit = DEV_UNIT(tp->t_dev); 1749 char mr1, mr2; 1750 int error; 1751 struct scn_softc *sc = SOFTC(unit); 1752 1753 /* Is this a hang up? */ 1754 if (t->c_ospeed == B0) { 1755 SCN_OP_BIC(sc, sc->sc_op_dtr); 1756 /* leave DTR down. see comment in scnclose() -plb */ 1757 return (0); 1758 } 1759 mr1 = mr2 = 0; 1760 1761 /* Parity? */ 1762 if (cflag & PARENB) { 1763 if ((cflag & PARODD) == 0) 1764 mr1 |= MR1_PEVEN; 1765 else 1766 mr1 |= MR1_PODD; 1767 } else 1768 mr1 |= MR1_PNONE; 1769 1770 /* Stop bits. */ 1771 if (cflag & CSTOPB) 1772 mr2 |= MR2_STOP2; 1773 else 1774 mr2 |= MR2_STOP1; 1775 1776 /* Data bits. */ 1777 switch (cflag & CSIZE) { 1778 case CS5: 1779 mr1 |= MR1_CS5; 1780 break; 1781 case CS6: 1782 mr1 |= MR1_CS6; 1783 break; 1784 case CS7: 1785 mr1 |= MR1_CS7; 1786 break; 1787 case CS8: 1788 default: 1789 mr1 |= MR1_CS8; 1790 break; 1791 } 1792 1793 if (cflag & CCTS_OFLOW) 1794 mr2 |= MR2_TXCTS; 1795 1796 if (cflag & CRTS_IFLOW) { 1797 mr1 |= MR1_RXRTS; 1798 sc->sc_rbhiwat = SCN_RING_HIWAT; 1799 } else { 1800 sc->sc_rbhiwat = 0; 1801 } 1802 1803 error = scn_config(unit, sc->sc_channel, t->c_ispeed, 1804 t->c_ospeed, mr1, mr2); 1805 1806 /* If successful, copy to tty */ 1807 if (!error) { 1808 tp->t_ispeed = t->c_ispeed; 1809 tp->t_ospeed = t->c_ospeed; 1810 tp->t_cflag = cflag; 1811 } 1812 return (error); 1813 } 1814 1815 /* 1816 * Start or restart a transmission. 1817 */ 1818 void 1819 scnstart(struct tty *tp) 1820 { 1821 int s, c; 1822 int unit = DEV_UNIT(tp->t_dev); 1823 struct scn_softc *sc = SOFTC(unit); 1824 1825 s = spltty(); 1826 if (tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1827 goto out; 1828 if (!ttypull(tp)) 1829 goto out; 1830 1831 tp->t_state |= TS_BUSY; 1832 1833 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) { 1834 if ((c = getc(&tp->t_outq)) == -1) 1835 break; 1836 sc->sc_chbase[CH_DAT] = c; 1837 } 1838 sc->sc_duart->imr |= (sc->sc_tx_int | sc->sc_rx_int); 1839 sc->sc_duart->base[DU_IMR] = sc->sc_duart->imr; 1840 1841 out: 1842 splx(s); 1843 } 1844 1845 /* 1846 * Stop output on a line. 1847 */ 1848 /*ARGSUSED*/ 1849 void 1850 scnstop(struct tty *tp, int flags) 1851 { 1852 int s; 1853 1854 s = spltty(); 1855 if (tp->t_state & TS_BUSY) { 1856 if ((tp->t_state & TS_TTSTOP) == 0) 1857 tp->t_state |= TS_FLUSH; 1858 } 1859 splx(s); 1860 } 1861 1862 /* 1863 * Following are all routines needed for SCN to act as console. 1864 */ 1865 1866 void 1867 scncnprobe(struct consdev *cn) 1868 { 1869 } 1870 1871 void 1872 scncnreinit(void *v) 1873 { 1874 volatile u_char *du_base = 1875 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1876 1877 du_base[DU_OPSET] = 1878 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1879 } 1880 1881 void 1882 scncninit(struct consdev *cn) 1883 { 1884 devmajor_t major; 1885 1886 /* initialize required fields */ 1887 major = cdevsw_lookup_major(&scn_cdevsw); 1888 KASSERT(major != NODEV); 1889 cn->cn_dev = makedev(major, SCN_CONSOLE); 1890 cn->cn_pri = CN_REMOTE; 1891 1892 scninit(cn->cn_dev, scnconsrate); 1893 } 1894 1895 /* Used by scncninit and kgdb startup. */ 1896 int 1897 scninit(dev_t dev, int rate) 1898 { 1899 /* XXX - maintain PROM's settings */ 1900 #if 0 1901 volatile u_char *du_base = 1902 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1903 int unit = DEV_UNIT(dev); 1904 1905 du_base[DU_OPSET] = 1906 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1907 scn_config(unit, SCN_CONSCHAN, rate, rate, 1908 MR1_PNONE | MR1_CS8, MR2_STOP1); 1909 #endif 1910 return (0); 1911 } 1912 1913 /* 1914 * Console kernel input character routine. 1915 */ 1916 int 1917 scncngetc(dev_t dev) 1918 { 1919 volatile u_char *ch_base = 1920 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1921 char c; 1922 int s; 1923 1924 s = spltty(); 1925 1926 while ((ch_base[CH_SR] & SR_RX_RDY) == 0) 1927 ; 1928 c = ch_base[CH_DAT]; 1929 1930 splx(s); 1931 return c; 1932 } 1933 1934 void 1935 scncnpollc(dev_t dev, int on) 1936 { 1937 } 1938 1939 /* 1940 * Console kernel output character routine. 1941 */ 1942 void 1943 scncnputc(dev_t dev, int c) 1944 { 1945 volatile u_char *ch_base = 1946 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1947 volatile u_char *du_base = 1948 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1949 int s; 1950 1951 s = spltty(); 1952 1953 if (c == '\n') 1954 scncnputc(dev, '\r'); 1955 1956 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1957 ; 1958 ch_base[CH_DAT] = c; 1959 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1960 ; 1961 du_base[DU_ISR]; 1962 1963 splx(s); 1964 } 1965