1 /* $NetBSD: scn.c,v 1.1 2009/02/10 06:04:56 rumble Exp $ */ 2 3 /* 4 * Resurrected from the old pc532 port 1/18/2009. 5 * 6 * XXX- The locking in this is probably totally broken. I haven't attempted 7 * to get it right, but it seems to work okay anyhow. 8 */ 9 10 /* 11 * Copyright (c) 1991, 1992, 1993 12 * The Regents of the University of California. All rights reserved. 13 * 14 * Portions of this software were developed by the Computer Systems 15 * Engineering group at Lawrence Berkeley Laboratory under DARPA 16 * contract BG 91-66 and contributed to Berkeley. 17 * 18 * All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Lawrence Berkeley Laboratory. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 48 */ 49 50 /* 51 * Copyright (c) 1996, 1997 Philip L. Budne. 52 * Copyright (c) 1993 Philip A. Nelson. 53 * 54 * Portions of this software were developed by the Computer Systems 55 * Engineering group at Lawrence Berkeley Laboratory under DARPA 56 * contract BG 91-66 and contributed to Berkeley. 57 * 58 * All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Lawrence Berkeley Laboratory. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 3. All advertising materials mentioning features or use of this software 72 * must display the following acknowledgement: 73 * This product includes software developed by the University of 74 * California, Berkeley and its contributors. 75 * 4. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 #include <sys/cdefs.h> 95 __KERNEL_RCSID(0, "$NetBSD: scn.c,v 1.1 2009/02/10 06:04:56 rumble Exp $"); 96 97 #include "opt_ddb.h" 98 #include "opt_kgdb.h" 99 #include "scn.h" 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/user.h> 108 #include <sys/file.h> 109 #include <sys/uio.h> 110 #include <sys/kernel.h> 111 #include <sys/syslog.h> 112 #include <sys/types.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/conf.h> 116 #include <sys/intr.h> 117 #ifdef KGDB 118 #include <sys/kgdb.h> 119 #endif 120 #include <sys/kauth.h> 121 122 #include <dev/cons.h> 123 124 #include <machine/autoconf.h> 125 #include <machine/machtype.h> 126 127 #include <sgimips/dev/scnreg.h> 128 #include <sgimips/dev/scnvar.h> 129 130 int scn_match(device_t, struct cfdata *, void *); 131 void scn_attach(device_t, device_t, void *); 132 int scnparam(struct tty *, struct termios *); 133 void scnstart(struct tty *); 134 int scnhwiflow(struct tty *, int); 135 136 void scncnprobe(struct consdev *); 137 void scncninit(struct consdev *); 138 int scncngetc(dev_t); 139 void scncnputc(dev_t, int); 140 void scncnpollc(dev_t, int); 141 int scninit(dev_t, int); 142 void scncnreinit(void *); 143 144 CFATTACH_DECL(scn, sizeof(struct scn_softc), 145 scn_match, scn_attach, NULL, NULL); 146 147 extern struct cfdriver scn_cd; 148 149 dev_type_open(scnopen); 150 dev_type_close(scnclose); 151 dev_type_read(scnread); 152 dev_type_write(scnwrite); 153 dev_type_ioctl(scnioctl); 154 dev_type_stop(scnstop); 155 dev_type_tty(scntty); 156 dev_type_poll(scnpoll); 157 158 const struct cdevsw scn_cdevsw = { 159 scnopen, scnclose, scnread, scnwrite, scnioctl, 160 scnstop, scntty, scnpoll, nommap, ttykqfilter, D_TTY 161 }; 162 163 struct consdev scn_cn = { 164 scncnprobe, 165 scncninit, 166 scncngetc, 167 scncnputc, 168 scncnpollc, 169 NULL, 170 NULL, 171 NULL, 172 NODEV, 173 CN_NORMAL 174 }; 175 176 #ifndef CONSOLE_SPEED 177 #define CONSOLE_SPEED TTYDEF_SPEED 178 #endif 179 180 #ifndef SCNDEF_CFLAG 181 #define SCNDEF_CFLAG TTYDEF_CFLAG 182 #endif 183 184 #ifdef CPU30MHZ 185 #define RECOVER() __asm volatile("bispsrw 0x800" : : : "cc") 186 #else 187 #define RECOVER() 188 #endif 189 190 int scndefaultrate = TTYDEF_SPEED; 191 int scnconsrate = CONSOLE_SPEED; 192 193 static inline struct scn_softc * 194 SOFTC(int unit) 195 { 196 if (unit < 0 || unit >= scn_cd.cd_ndevs) 197 return (NULL); 198 return ((struct scn_softc *)scn_cd.cd_devs[unit]); 199 } 200 201 static int scnintr(void *); 202 static void scnrxintr(void *); 203 static int scn_rxintr(struct scn_softc *); 204 static void scnsoft(void *); 205 static void scn_setchip(struct scn_softc *sc); 206 static int scniter(int *, int, int*, int*, struct chan *, int); 207 static int scn_config(int, int, int, int, u_char, u_char); 208 static void scn_rxenable(struct scn_softc *); 209 static void scn_rxdisable(struct scn_softc *); 210 static void dcd_int(struct scn_softc *, struct tty *, u_char); 211 static void scnoverrun(int, long *, const char *); 212 static u_char opbits(struct scn_softc *, int); 213 214 static void *scnsir = NULL; /* s/w intr cookie */ 215 #define setsoftscn() softint_schedule(scnsir) 216 217 #ifdef SCN_TIMING 218 /* 219 * Keep timing info on latency of software interrupt used by 220 * the ringbuf code to empty ring buffer. 221 * "getinfo" program reads data from /dev/kmem. 222 */ 223 static struct timeval tstart; 224 #define NJITTER 100 225 int scn_njitter = NJITTER; 226 int scn_jitter[NJITTER]; 227 #endif 228 229 #define SCN_CLOCK 3686400 /* input clock */ 230 231 /* speed table groups ACR[7] */ 232 #define GRP_A 0 233 #define GRP_B ACR_BRG 234 235 /* combo of MR0[2:0] and ACR[7] */ 236 #define MODE0A MR0_MODE_0 237 #define MODE0B (MR0_MODE_0|ACR_BRG) 238 #define MODE1A MR0_MODE_1 239 #define MODE1B (MR0_MODE_1|ACR_BRG) 240 #define MODE2A MR0_MODE_2 241 #define MODE2B (MR0_MODE_2|ACR_BRG) 242 243 #define ANYMODE -1 244 #define DEFMODE(C92) MODE0A /* use MODE4A if 26c92? */ 245 246 /* speed code for Counter/Timer (all modes, groups) */ 247 #define USE_CT 0xd 248 249 /* 250 * Rate table, ordered by speed, then mode. 251 * NOTE: ordering of modes must be done carefully! 252 */ 253 struct tabent { 254 int32_t speed; 255 int16_t code; 256 int16_t mode; 257 } table[] = { 258 { 50, 0x0, MODE0A }, 259 { 75, 0x0, MODE0B }, 260 { 110, 0x1, MODE0A }, 261 { 110, 0x1, MODE0B }, 262 { 110, 0x1, MODE1A }, 263 { 110, 0x1, MODE1B }, 264 { 134, 0x2, MODE0A }, /* 134.5 */ 265 { 134, 0x2, MODE0B }, /* 134.5 */ 266 { 134, 0x2, MODE1A }, /* 134.5 */ 267 { 134, 0x2, MODE1B }, /* 134.5 */ 268 { 150, 0x3, MODE0A }, 269 { 150, 0x3, MODE0A }, 270 { 200, 0x3, MODE0A }, 271 { 300, 0x4, MODE0A }, 272 { 300, 0x4, MODE0B }, 273 { 300, 0x0, MODE1A }, 274 { 450, 0x0, MODE1B }, 275 { 600, 0x5, MODE0A }, 276 { 600, 0x5, MODE0B }, 277 { 880, 0x1, MODE2A }, 278 { 880, 0x1, MODE2B }, 279 { 900, 0x3, MODE1B }, 280 { 1050, 0x7, MODE0A }, 281 { 1050, 0x7, MODE1A }, 282 { 1076, 0x2, MODE2A }, 283 { 1076, 0x2, MODE2B }, 284 { 1200, 0x6, MODE0A }, 285 { 1200, 0x6, MODE0B }, 286 { 1200, 0x3, MODE1A }, 287 { 1800, 0xa, MODE0B }, 288 { 1800, 0x4, MODE1A }, 289 { 1800, 0x4, MODE1B }, 290 { 2000, 0x7, MODE0B }, 291 { 2000, 0x7, MODE1B }, 292 { 2400, 0x8, MODE0A }, 293 { 2400, 0x8, MODE0B }, 294 { 3600, 0x5, MODE1A }, 295 { 3600, 0x5, MODE1B }, 296 { 4800, 0x9, MODE2A }, 297 { 4800, 0x9, MODE2B }, 298 { 4800, 0x9, MODE0A }, 299 { 4800, 0x9, MODE0B }, 300 { 7200, 0xa, MODE0A }, 301 { 7200, 0x0, MODE2B }, 302 { 7200, 0x6, MODE1A }, 303 { 7200, 0x6, MODE1B }, 304 { 9600, 0xb, MODE2A }, 305 { 9600, 0xb, MODE2B }, 306 { 9600, 0xb, MODE0A }, 307 { 9600, 0xb, MODE0B }, 308 { 9600, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 309 { 9600, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 310 { 14400, 0x3, MODE2B }, 311 { 14400, 0x8, MODE1A }, 312 { 14400, 0x8, MODE1B }, 313 { 19200, 0x3, MODE2A }, 314 { 19200, 0xc, MODE2B }, 315 { 19200, 0xc, MODE0B }, 316 { 19200, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 317 { 19200, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 318 { 28800, 0x4, MODE2A }, 319 { 28800, 0x4, MODE2B }, 320 { 28800, 0x9, MODE1A }, 321 { 28800, 0x9, MODE1B }, 322 { 38400, 0xc, MODE2A }, 323 { 38400, 0xc, MODE0A }, 324 { 57600, 0x5, MODE2A }, 325 { 57600, 0x5, MODE2B }, 326 { 57600, 0xb, MODE1A }, 327 { 57600, 0xb, MODE1B }, 328 { 115200, 0x6, MODE2A }, 329 { 115200, 0x6, MODE2B }, 330 { 115200, 0xc, MODE1B }, 331 { 230400, 0xc, MODE1A } 332 }; 333 #define TABENTRIES (sizeof(table)/sizeof(table[0])) 334 335 /* 336 * boolean for speed codes which are identical in both A/B BRG groups 337 * in all modes 338 */ 339 static u_char bothgroups[16] = { 340 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1 341 }; 342 343 /* 344 * Manually constructed divisors table 345 * for minimum error (from some of Dave Rand's code) 346 */ 347 const struct { 348 uint16_t speed; 349 uint16_t div; 350 } divs[] = { 351 { 50, 2303 }, /* 2304 is exact?? */ 352 { 110, 1047 }, /* Should be 1047.27 */ 353 { 134, 857 }, /* Should be 856.505576 */ 354 { 1050, 110 }, /* Should be 109.7142857 */ 355 { 2000, 57 } /* Should be 57.6 */ 356 }; 357 #define DIVS (sizeof(divs)/sizeof(divs[0])) 358 359 /* 360 * minor unit bit decode: 361 * CxxxUUU 362 * 363 * C - carrier 364 * 0 - delay open until carrier high 365 * 1 - allow open with carrier low 366 * UUU - unit 0-7 367 */ 368 369 #define DEV_UNIT(x) (minor(x) & 0x7) 370 #define DEV_DIALOUT(x) (minor(x) & 0x80) 371 372 extern struct tty *constty; 373 374 #define SCN_MAXDUART 4 375 static struct duart scn_duart[SCN_MAXDUART]; 376 377 #ifdef KGDB 378 extern int kgdb_dev; 379 extern int kgdb_rate; 380 extern int kgdb_debug_init; 381 #endif 382 383 /* XXXXX - fix this */ 384 #define splrtty() spltty() 385 386 /* RS-232 configuration routines */ 387 388 /* 389 * set chip parameters, or mark for delayed change. 390 * called at spltty() or on TxEMPTY interrupt. 391 * 392 * Reads current values to avoid glitches from redundant sets. 393 * Perhaps should save last value set to avoid read/write? NOTE: 394 * Would still need to do read if write not needed to advance MR 395 * pointer. 396 * 397 * new 2/97 -plb 398 */ 399 400 static void 401 scn_setchip(struct scn_softc *sc) 402 { 403 struct duart *dp; 404 u_char acr, csr, mr1, mr2; 405 int chan; 406 407 if (sc->sc_tty && (sc->sc_tty->t_state & TS_BUSY)) { 408 sc->sc_heldchanges = 1; 409 return; 410 } 411 412 chan = sc->sc_channel; 413 dp = sc->sc_duart; 414 if (dp->type == SC26C92) { 415 u_char nmr0a, mr0a; 416 417 /* input rate high enough so 64 bit time watchdog not 418 * onerous? */ 419 if (dp->chan[chan].ispeed >= 1200) { 420 /* set FIFO threshold at 6 for other 421 * thresholds we could have to set MR1_FFULL 422 */ 423 dp->chan[chan].mr0 |= MR0_RXWD | MR0_RXINT; 424 } else { 425 dp->chan[chan].mr0 &= ~(MR0_RXWD | MR0_RXINT); 426 } 427 428 /* select BRG mode (MR0A only) */ 429 nmr0a = dp->chan[0].mr0 | (dp->mode & MR0_MODE); 430 431 dp->base[CH_CR] = CR_CMD_MR0; 432 RECOVER(); 433 434 mr0a = dp->base[CH_MR]; 435 if (mr0a != nmr0a) { 436 dp->base[CH_CR] = CR_CMD_MR0; 437 RECOVER(); 438 dp->base[CH_MR] = nmr0a; 439 } 440 441 if (chan) { /* channel B? */ 442 u_char mr0b; 443 444 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 445 RECOVER(); 446 mr0b = dp->base[CH_MR]; 447 448 if (dp->chan[chan].mr0 != mr0b) { 449 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 450 RECOVER(); 451 sc->sc_chbase[CH_MR] = dp->chan[chan].mr0; 452 } 453 } 454 } else { 455 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 456 RECOVER(); 457 } 458 459 mr1 = sc->sc_chbase[CH_MR]; 460 mr2 = sc->sc_chbase[CH_MR]; 461 if (mr1 != dp->chan[chan].new_mr1 || 462 mr2 != dp->chan[chan].new_mr2) { 463 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 464 RECOVER(); 465 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr1; 466 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr2; 467 } 468 469 acr = dp->acr | (dp->mode & ACR_BRG); 470 dp->base[DU_ACR] = acr; /* write-only reg! */ 471 472 /* set speed codes */ 473 csr = (dp->chan[chan].icode<<4) | dp->chan[chan].ocode; 474 if (sc->sc_chbase[CH_CSR] != csr) { 475 sc->sc_chbase[CH_CSR] = csr; 476 } 477 478 /* see if counter/timer in use */ 479 if (dp->counter && 480 (dp->chan[0].icode == USE_CT || dp->chan[0].ocode == USE_CT || 481 dp->chan[1].icode == USE_CT || dp->chan[1].ocode == USE_CT)) { 482 483 /* program counter/timer only if necessary */ 484 if (dp->counter != dp->ocounter) { 485 uint16_t div; 486 #ifdef DIVS 487 int i; 488 489 /* look for precalculated rate, for minimum error */ 490 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { 491 if (divs[i].speed == dp->counter) { 492 div = divs[i].div; 493 goto found; 494 } 495 } 496 #endif 497 498 /* not found in table; calculate a value (rounding up) */ 499 div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter; 500 501 found: 502 /* halt before loading? may ALWAYS glitch? 503 * reload race may only sometimes glitch?? 504 */ 505 dp->base[DU_CTUR] = div >> 8; 506 dp->base[DU_CTLR] = div & 255; 507 if (dp->ocounter == 0) { 508 /* not previously used? */ 509 u_char temp; 510 /* start C/T running */ 511 temp = dp->base[DU_CSTRT]; 512 } 513 dp->ocounter = dp->counter; 514 } 515 } else { 516 /* counter not in use; mark as free */ 517 dp->counter = 0; 518 } 519 sc->sc_heldchanges = 0; 520 521 /* 522 * delay a tiny bit to try and avoid tx glitching. 523 * I know we're at spltty(), but this is much better than the 524 * old version used DELAY((96000 / out_speed) * 10000) 525 * -plb 526 */ 527 DELAY(10); 528 } 529 530 /* 531 * iterator function for speeds. 532 * (could be called "findnextcode") 533 * Returns sequence of possible speed codes for a given rate. 534 * should set index to zero before first call. 535 * 536 * Could be implemented as a "checkspeed()" function called 537 * to evaluate table entries, BUT this allows more variety in 538 * use of C/T with fewer table entries. 539 */ 540 541 static int 542 scniter(int *index, int wanted, int *counter, int *mode, struct chan *other, 543 int c92) 544 { 545 546 while (*index < TABENTRIES) { 547 struct tabent *tp; 548 549 tp = table + (*index)++; 550 if (tp->speed != wanted) 551 continue; 552 553 /* if not a 26C92 only look at MODE0 entries */ 554 if (!c92 && (tp->mode & MR0_MODE) != MR0_MODE_0) 555 continue; 556 557 /* 558 * check mode; 559 * OK if this table entry for current mode, or mode not 560 * yet set, or other channel's rates are available in both 561 * A and B groups. 562 */ 563 564 if (tp->mode == *mode || *mode == ANYMODE || 565 (other != NULL && (tp->mode & MR0_MODE) == (*mode & MR0_MODE) && 566 bothgroups[other->icode] && bothgroups[other->ocode])) { 567 /* 568 * for future table entries specifying 569 * use of counter/timer 570 */ 571 if (tp->code == USE_CT) { 572 if (*counter != wanted && *counter != 0) 573 continue; /* counter busy */ 574 *counter = wanted; 575 } 576 *mode = tp->mode; 577 return tp->code; 578 } 579 } 580 581 /* here after returning all applicable table entries */ 582 /* XXX return sequence of USE_CT with all possible modes?? */ 583 if ((*index)++ == TABENTRIES) { 584 /* Max C/T rate (even on 26C92?) is 57600 */ 585 if (wanted <= 57600 && (*counter == wanted || *counter == 0)) { 586 *counter = wanted; 587 return USE_CT; 588 } 589 } 590 591 return -1; /* FAIL */ 592 } 593 594 /* 595 * calculate configuration 596 * rewritten 2/97 -plb 597 */ 598 static int 599 scn_config(int unit, int chan, int ispeed, int ospeed, u_char mr1, u_char mr2) 600 { 601 struct scn_softc *sc; 602 struct duart *dp; 603 int other; /* opposite of chan */ 604 int mode; 605 int counter; 606 int i, o; /* input, output iterator indexes */ 607 int ic, oc; /* input, output codes */ 608 struct chan *ocp; /* other duart channel */ 609 struct tty *otp; /* other channel tty struct */ 610 int c92; /* true if duart is sc26c92 */ 611 int s; 612 613 /* Set up softc pointer. */ 614 if (unit >= scn_cd.cd_ndevs) 615 return ENXIO; 616 sc = SOFTC(unit); 617 chan = sc->sc_channel; 618 other = chan ^ 1; 619 dp = sc->sc_duart; 620 ocp = &dp->chan[other]; 621 otp = ocp->tty; 622 c92 = (dp->type == SC26C92); 623 624 /* 625 * Right now the first combination that works is used. 626 * Perhaps it should search entire solution space for "best" 627 * combination. For example, use heuristic weighting of mode 628 * preferences, and use of counter timer? 629 * 630 * For example right now with 2681/2692 when default rate is 631 * 9600 and other channel is closed setting 19200 will pick 632 * mode 0a and use counter/timer. Better solution might be 633 * mode 0b, leaving counter/timer free! 634 * 635 * When other channel is open might want to prefer 636 * leaving counter timer free, or not flipping A/B group? 637 */ 638 if (otp && (otp->t_state & TS_ISOPEN)) { 639 640 /* 641 * Other channel open; 642 * Find speed codes compatible with current mode/counter. 643 */ 644 645 i = 0; 646 for (;;) { 647 mode = dp->mode; 648 counter = dp->counter; 649 650 /* NOTE: pass other chan pointer to allow group flipping */ 651 ic = scniter(&i, ispeed, &counter, &mode, ocp, c92); 652 if (ic == -1) 653 break; 654 655 o = 0; 656 if ((oc = scniter(&o, ospeed, &counter, 657 &mode, NULL, c92)) != -1) { 658 /* 659 * take first match 660 * 661 * Perhaps calculate heuristic "score", 662 * save score,codes,mode,counter if score 663 * better than previous best? 664 */ 665 goto gotit; 666 } 667 } 668 /* XXX try looping for ospeed? */ 669 } else { 670 /* other channel closed */ 671 int oo, oi; /* other input, output iterators */ 672 int oic, ooc; /* other input, output codes */ 673 674 /* 675 * Here when other channel closed. Finds first 676 * combination that will allow other channel to be opened 677 * (with defaults) and fits our needs. 678 */ 679 oi = 0; 680 for (;;) { 681 mode = ANYMODE; 682 counter = 0; 683 684 oic = scniter(&oi, ocp->ispeed, &counter, &mode, NULL, c92); 685 if (oic == -1) 686 break; 687 688 oo = 0; 689 while ((ooc = scniter(&oo, ocp->ospeed, &counter, 690 &mode, NULL, c92)) != -1) { 691 i = 0; 692 while ((ic = scniter(&i, ispeed, &counter, 693 &mode, NULL, c92)) != -1) { 694 o = 0; 695 if ((oc = scniter(&o, ospeed, &counter, 696 &mode, NULL, c92)) != -1) { 697 /* 698 * take first match 699 * 700 * Perhaps calculate heuristic 701 * "score", save 702 * score,codes,mode,counter 703 * if score better than 704 * previous best? 705 */ 706 s = spltty(); 707 dp->chan[other].icode = oic; 708 dp->chan[other].ocode = ooc; 709 goto gotit2; 710 } 711 } 712 } 713 } 714 } 715 return EINVAL; 716 717 gotit: 718 s = spltty(); 719 gotit2: 720 dp->chan[chan].new_mr1 = mr1; 721 dp->chan[chan].new_mr2 = mr2; 722 dp->chan[chan].ispeed = ispeed; 723 dp->chan[chan].ospeed = ospeed; 724 dp->chan[chan].icode = ic; 725 dp->chan[chan].ocode = oc; 726 if (mode == ANYMODE) /* no mode selected?? */ 727 mode = DEFMODE(c92); 728 dp->mode = mode; 729 dp->counter = counter; 730 731 scn_setchip(sc); /* set chip now, if possible */ 732 splx(s); 733 return (0); 734 } 735 736 int 737 scn_match(device_t parent, struct cfdata *cf, void *aux) 738 { 739 struct mainbus_attach_args *ma = aux; 740 741 if ((mach_type == MACH_SGI_IP6 || mach_type == MACH_SGI_IP10) && 742 ma->ma_addr == 0x1fb80004) 743 return (1); 744 745 return (0); 746 } 747 748 /* 749 * No need to make scn_rx{en,dis}able too efficient, 750 * they're only called on setup, open & close! 751 */ 752 static inline void 753 scn_rxenable(struct scn_softc *sc) 754 { 755 struct duart *dp; 756 int channel; 757 758 dp = sc->sc_duart; 759 channel = sc->sc_channel; 760 761 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 762 if (channel == 0) 763 dp->opcr |= OPCR_OP4_RXRDYA; 764 else 765 dp->opcr |= OPCR_OP5_RXRDYB; 766 dp->base[DU_OPCR] = dp->opcr; 767 dp->imr |= sc->sc_rx_int; 768 dp->base[DU_IMR] = dp->imr; 769 } 770 771 static inline void 772 scn_rxdisable(struct scn_softc *sc) 773 { 774 struct duart *dp; 775 int channel; 776 777 dp = sc->sc_duart; 778 channel = sc->sc_channel; 779 780 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 781 if (channel == 0) 782 dp->opcr &= ~OPCR_OP4_RXRDYA; 783 else 784 dp->opcr &= ~OPCR_OP5_RXRDYB; 785 dp->base[DU_OPCR] = dp->opcr; 786 dp->imr &= ~sc->sc_rx_int; 787 dp->base[DU_IMR] = dp->imr; 788 } 789 790 void 791 scn_attach(device_t parent, device_t self, void *aux) 792 { 793 struct mainbus_attach_args *ma = aux; 794 struct scn_softc *sc; 795 struct duart *duart; 796 volatile u_char *ch_base; 797 volatile u_char *duart_base; 798 int channel; 799 int speed; 800 int s; 801 int maj; 802 u_char unit; 803 u_char duartno; 804 u_char delim = ':'; 805 u_char mr1, mr2; 806 enum scntype scntype = SCNUNK; 807 const char *duart_type = "Unknown"; 808 char *intrname; 809 bool console, first; 810 devmajor_t major; 811 812 (void)major; 813 814 sc = device_private(self); 815 unit = device_unit(self); 816 817 /* XXX - hard-coded */ 818 if (ma->ma_addr == 0x1fb80004) 819 duartno = 1; 820 else 821 duartno = 0; 822 channel = 0; 823 console = 1; 824 825 duart = sc->sc_duart = &scn_duart[duartno]; 826 duart->chan[channel].sc = sc; 827 first = (duart->base == NULL); 828 829 if (console) { 830 sc->sc_isconsole = 1; 831 sc->sc_swflags |= SCN_SW_SOFTCAR; /* ignore carrier */ 832 } 833 834 duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr); 835 ch_base = duart_base; /* XXX */ 836 837 if (first) { 838 /* Probe DUART type */ 839 s = spltty(); 840 if (console) { 841 ch_base[CH_CR] = CR_DIS_TX; 842 delay(5 * 10000); 843 } 844 ch_base[CH_CR] = CR_CMD_MR1; 845 RECOVER(); 846 mr1 = ch_base[CH_MR]; 847 mr2 = ch_base[CH_MR]; 848 ch_base[CH_CR] = CR_CMD_MR1; 849 RECOVER(); 850 ch_base[CH_MR] = 1; 851 ch_base[CH_MR] = 0; 852 ch_base[CH_CR] = CR_CMD_MR1; 853 RECOVER(); 854 if (ch_base[CH_MR] == 1) { 855 /* MR 2 selected */ 856 ch_base[CH_CR] = CR_CMD_MR0; 857 RECOVER(); 858 /* if 2681, MR2 still selected */ 859 ch_base[CH_MR] = 1; 860 ch_base[CH_CR] = CR_CMD_MR1; 861 RECOVER(); 862 ch_base[CH_MR] = 0; /* MR1 */ 863 ch_base[CH_MR] = 0; /* MR2 */ 864 ch_base[CH_CR] = CR_CMD_MR0; 865 RECOVER(); 866 /* if 2681, MR2 still selected */ 867 if((ch_base[CH_MR] & 1) == 1) { 868 duart_type = "sc26c92"; 869 scntype = SC26C92; 870 } else { 871 /* 2681 treats as MR1 Select */ 872 ch_base[CH_CR] = CR_CMD_RTS_OFF; 873 RECOVER(); 874 ch_base[CH_MR] = 1; 875 ch_base[CH_MR] = 0; 876 ch_base[CH_CR] = CR_CMD_RTS_OFF; 877 RECOVER(); 878 if (ch_base[CH_MR] == 1) { 879 duart_type = "scn2681"; 880 scntype = SCN2681; 881 } else { 882 duart_type = "scn2692"; 883 scntype = SCN2692; 884 } 885 } 886 } 887 888 /* If a 2681, the CR_CMD_MR0 is interpreted as a TX_RESET */ 889 if (console) { 890 ch_base[CH_CR] = CR_ENA_TX; 891 RECOVER(); 892 } 893 ch_base[CH_CR] = CR_CMD_MR1; 894 RECOVER(); 895 ch_base[CH_MR] = mr1; 896 ch_base[CH_MR] = mr2; 897 splx(s); 898 899 intrname = malloc(sizeof("scnXX"), M_DEVBUF, M_NOWAIT); 900 snprintf(intrname, sizeof("scnXX"), "scn%d", unit); 901 902 /* 903 * On IP6 the console chip is duart1. The keyboard/mouse 904 * is duart0. Each chip has two channels and the channels 905 * share an interrupt. Duart0 is interrupt 0, duart1 is 906 * interrupt 1. 907 */ 908 if (duartno != 0 && duartno != 1) 909 panic("scn_attach: bad duartno: %d", duartno); 910 cpu_intr_establish(duartno, IPL_TTY, scnintr, duart); 911 912 printf("%c %s", delim, duart_type); 913 delim = ','; 914 915 duart->base = duart_base; 916 duart->type = scntype; 917 } 918 /* Record channel, uart */ 919 sc->sc_channel = channel; 920 sc->sc_chbase = ch_base; 921 922 /* Initialize modem/interrupt bit masks */ 923 if (channel == 0) { 924 sc->sc_op_rts = OP_RTSA; 925 sc->sc_op_dtr = OP_DTRA; 926 sc->sc_ip_cts = IP_CTSA; 927 sc->sc_ip_dcd = IP_DCDA; 928 929 sc->sc_tx_int = INT_TXA; 930 sc->sc_rx_int = INT_RXA; 931 } else { 932 sc->sc_op_rts = OP_RTSB; 933 sc->sc_op_dtr = OP_DTRB; 934 sc->sc_ip_cts = IP_CTSB; 935 sc->sc_ip_dcd = IP_DCDB; 936 937 sc->sc_tx_int = INT_TXB; 938 sc->sc_rx_int = INT_RXB; 939 } 940 941 /* Initialize counters */ 942 sc->sc_framing_errors = 0; 943 sc->sc_fifo_overruns = 0; 944 sc->sc_parity_errors = 0; 945 sc->sc_breaks = 0; 946 947 if (console) { 948 DELAY(5 * 10000); /* Let the output go out.... */ 949 } 950 951 /* 952 * Set up the hardware to a base state, in particular: 953 * o reset transmitter and receiver 954 * o set speeds and configurations 955 * o receiver interrupts only (RxRDY and BREAK) 956 */ 957 958 s = spltty(); 959 /* RTS off... */ 960 SCN_OP_BIC(sc, sc->sc_op_rts); /* "istop" */ 961 962 ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX; 963 RECOVER(); 964 ch_base[CH_CR] = CR_CMD_RESET_RX; 965 RECOVER(); 966 ch_base[CH_CR] = CR_CMD_RESET_TX; 967 RECOVER(); 968 ch_base[CH_CR] = CR_CMD_RESET_ERR; 969 RECOVER(); 970 ch_base[CH_CR] = CR_CMD_RESET_BRK; 971 RECOVER(); 972 ch_base[CH_CR] = CR_CMD_MR1; 973 RECOVER(); 974 975 /* No receiver control of RTS. */ 976 ch_base[CH_MR] = 0; 977 ch_base[CH_MR] = 0; 978 979 /* Initialize the uart structure if this is channel A. */ 980 if (first) { 981 /* Disable all interrupts. */ 982 duart_base[DU_IMR] = duart->imr = 0; 983 984 /* Output port config */ 985 duart_base[DU_OPCR] = duart->opcr = 0; 986 987 /* Speeds... */ 988 duart->mode = 0; 989 990 /* 991 * Set initial speed to an illegal code that can be changed to 992 * any other baud. 993 */ 994 duart->chan[0].icode = duart->chan[0].ocode = 0x2f; 995 duart->chan[1].icode = duart->chan[1].ocode = 0x2f; 996 duart->chan[0].ispeed = duart->chan[0].ospeed = 0; 997 duart->chan[1].ispeed = duart->chan[1].ospeed = 0; 998 999 duart->acr = 0; 1000 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */ 1001 } 1002 1003 if (channel == 0) { 1004 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */ 1005 } else { 1006 duart->acr |= ACR_DELTA_DCDB; /* Set CD int */ 1007 } 1008 1009 if (scnsir == NULL) { 1010 /* software intr: calls tty code, hence IPL_TTY */ 1011 scnsir = softint_establish(SOFTINT_SERIAL, scnsoft, NULL); 1012 } 1013 1014 duart_base[DU_ACR] = (duart->mode & ACR_BRG) | duart->acr; 1015 1016 if (console) 1017 speed = scnconsrate; 1018 else 1019 speed = scndefaultrate; 1020 1021 scn_config(unit, channel, speed, speed, MR1_PNONE | MR1_CS8, MR2_STOP1); 1022 if (console) { 1023 maj = cdevsw_lookup_major(&scn_cdevsw); 1024 KASSERT(maj != NODEVMAJOR); 1025 shutdownhook_establish(scncnreinit, NULL); 1026 /* Make sure console can do scncngetc */ 1027 duart_base[DU_OPSET] = channel ? (OP_RTSB | OP_DTRB) : 1028 (OP_RTSA | OP_DTRA); 1029 } 1030 1031 /* Turn on the receiver and transmitters */ 1032 ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX; 1033 1034 /* Set up the interrupts. */ 1035 duart->imr |= INT_IP; 1036 scn_rxdisable(sc); 1037 splx(s); 1038 1039 if (sc->sc_swflags) { 1040 printf("%c flags %d", delim, sc->sc_swflags); 1041 delim = ','; 1042 } 1043 1044 #ifdef KGDB 1045 major = cdevsw_lookup_major(&scn_cdevsw); 1046 KASSERT(major != NODEVMAJOR); 1047 if (kgdb_dev == makedev(major, unit)) { 1048 if (console) 1049 kgdb_dev = NODEV; /* can't debug over console port */ 1050 else { 1051 scninit(kgdb_dev, kgdb_rate); 1052 scn_rxenable(sc); 1053 scn->sc_iskgdb = 1; 1054 kgdb_attach(scncngetc, scncnputc, kgdb_dev); 1055 if (kgdb_debug_init) { 1056 printf("%c ", delim); 1057 kgdb_connect(1); 1058 } else 1059 printf("%c kgdb enabled", delim); 1060 delim = ','; 1061 } 1062 } 1063 #endif 1064 printf("\n"); 1065 } 1066 1067 /* ARGSUSED */ 1068 int 1069 scnopen(dev_t dev, int flags, int mode, struct lwp *l) 1070 { 1071 struct tty *tp; 1072 int unit = DEV_UNIT(dev); 1073 struct scn_softc *sc; 1074 int error = 0; 1075 int hwset = 0; 1076 1077 if (unit >= scn_cd.cd_ndevs) 1078 return ENXIO; 1079 sc = SOFTC(unit); 1080 if (!sc) 1081 return ENXIO; 1082 1083 tp = sc->sc_tty; 1084 if (!tp) { 1085 tp = ttymalloc(); 1086 sc->sc_tty = sc->sc_duart->chan[sc->sc_channel].tty = tp; 1087 tty_attach(tp); 1088 } 1089 1090 tp->t_oproc = scnstart; 1091 tp->t_param = scnparam; 1092 tp->t_hwiflow = scnhwiflow; 1093 tp->t_dev = dev; 1094 1095 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1096 return (EBUSY); 1097 1098 mutex_spin_enter(&tty_lock); 1099 1100 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1101 ttychars(tp); 1102 tp->t_iflag = TTYDEF_IFLAG; 1103 tp->t_oflag = TTYDEF_OFLAG; 1104 tp->t_cflag = SCNDEF_CFLAG; 1105 1106 sc->sc_rx_blocked = 0; 1107 1108 if (sc->sc_swflags & SCN_SW_CLOCAL) 1109 tp->t_cflag |= CLOCAL; 1110 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1111 tp->t_cflag |= CCTS_OFLOW | CRTS_IFLOW; 1112 tp->t_lflag = TTYDEF_LFLAG; 1113 if (sc->sc_isconsole) 1114 tp->t_ispeed = tp->t_ospeed = scnconsrate; 1115 else 1116 tp->t_ispeed = tp->t_ospeed = scndefaultrate; 1117 scnparam(tp, &tp->t_termios); 1118 ttsetwater(tp); 1119 1120 /* Turn on DTR and RTS. */ 1121 SCN_OP_BIS(sc, sc->sc_op_rts | sc->sc_op_dtr); 1122 1123 /* enable receiver interrupts */ 1124 scn_rxenable(sc); 1125 hwset = 1; 1126 1127 /* set carrier state; */ 1128 if ((sc->sc_swflags & SCN_SW_SOFTCAR) || /* check ttyflags */ 1129 SCN_DCD(sc) || /* check h/w */ 1130 DEV_DIALOUT(dev)) 1131 tp->t_state |= TS_CARR_ON; 1132 else 1133 tp->t_state &= ~TS_CARR_ON; 1134 } 1135 1136 mutex_spin_exit(&tty_lock); 1137 1138 error = ttyopen(tp, SCN_DIALOUT(sc), flags & O_NONBLOCK); 1139 if (error) printf("ttyopen failed line %d, error %d\n", __LINE__, error); 1140 if (error) 1141 goto bad; 1142 1143 error = (*tp->t_linesw->l_open) (dev, tp); 1144 if (error) printf("l_open failed line %d, error %d\n", __LINE__, error); 1145 if (error) 1146 goto bad; 1147 1148 return (0); 1149 1150 bad: 1151 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1152 scn_rxdisable(sc); 1153 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1154 } 1155 1156 return (error); 1157 } 1158 1159 1160 /*ARGSUSED*/ 1161 int 1162 scnclose(dev_t dev, int flags, int mode, struct lwp *l) 1163 { 1164 int unit = DEV_UNIT(dev); 1165 struct scn_softc *sc = SOFTC(unit); 1166 struct tty *tp = sc->sc_tty; 1167 devmajor_t major; 1168 1169 (void)major; 1170 1171 if ((tp->t_state & TS_ISOPEN) == 0) 1172 return 0; 1173 1174 (*tp->t_linesw->l_close) (tp, flags); 1175 1176 #ifdef KGDB 1177 /* do not disable interrupts if debugging */ 1178 major = cdevsw_lookup_major(&scn_devsw); 1179 KASSERT(major != cdevsw_lookup_major); 1180 if (kgdb_dev != makedev(major, unit)) 1181 #endif 1182 if ((tp->t_state & TS_ISOPEN) == 0) { 1183 scn_rxdisable(sc); 1184 } 1185 if ((tp->t_cflag & HUPCL) && (sc->sc_swflags & SCN_SW_SOFTCAR) == 0) { 1186 SCN_OP_BIC(sc, sc->sc_op_dtr); 1187 /* hold low for 1 second */ 1188 tsleep(sc, TTIPRI, ttclos, hz); 1189 } 1190 SCN_CLRDIALOUT(sc); 1191 ttyclose(tp); 1192 1193 #if 0 1194 if ((tp->t_state & TS_ISOPEN) == 0) { 1195 ttyfree(tp); 1196 sc->sc_tty = (struct tty *) NULL; 1197 } 1198 #endif 1199 1200 return (0); 1201 } 1202 1203 int 1204 scnread(dev_t dev, struct uio *uio, int flags) 1205 { 1206 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1207 struct tty *tp = sc->sc_tty; 1208 1209 return ((*tp->t_linesw->l_read) (tp, uio, flags)); 1210 } 1211 1212 int 1213 scnwrite(dev_t dev, struct uio *uio, int flags) 1214 { 1215 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1216 struct tty *tp = sc->sc_tty; 1217 1218 return ((*tp->t_linesw->l_write) (tp, uio, flags)); 1219 } 1220 1221 int 1222 scnpoll(dev_t dev, int events, struct lwp *l) 1223 { 1224 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1225 struct tty *tp = sc->sc_tty; 1226 1227 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1228 } 1229 1230 struct tty * 1231 scntty(dev_t dev) 1232 { 1233 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1234 1235 return sc->sc_tty; 1236 } 1237 1238 /* Worker routines for interrupt processing */ 1239 static inline void 1240 dcd_int(struct scn_softc *sc, struct tty *tp, u_char new) 1241 { 1242 1243 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1244 return; 1245 1246 #if 0 1247 printf("scn%d: dcd_int ip %x SCN_DCD %x new %x ipcr %x\n", 1248 sc->unit, 1249 sc->sc_duart->base[DU_IP], 1250 SCN_DCD(sc), 1251 new, 1252 sc->sc_duart->base[DU_IPCR] 1253 ); 1254 #endif 1255 1256 /* XXX set some flag to have some lower (soft) int call line discipline? */ 1257 if (!(*tp->t_linesw->l_modem) (tp, new == 0? 1: 0)) { 1258 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1259 } 1260 } 1261 1262 /* 1263 * Print out a ring or fifo overrun error message. 1264 */ 1265 static void 1266 scnoverrun(int unit, long *ptime, const char *what) 1267 { 1268 1269 if (*ptime != time_second) { 1270 *ptime = time_second; 1271 log(LOG_WARNING, "scn%d: %s overrun\n", unit, what); 1272 } 1273 } 1274 1275 /* 1276 * Try to block or unblock input using hardware flow-control. 1277 * This is called by kern/tty.c if MDMBUF|CRTSCTS is set, and 1278 * if this function returns non-zero, the TS_TBLOCK flag will 1279 * be set or cleared according to the "stop" arg passed. 1280 */ 1281 int 1282 scnhwiflow(struct tty *tp, int stop) 1283 { 1284 int unit = DEV_UNIT(tp->t_dev); 1285 struct scn_softc *sc = SOFTC(unit); 1286 int s; 1287 1288 s = splrtty(); 1289 if (!stop) { 1290 if (sc->sc_rbput - sc->sc_rbget - 1) { 1291 setsoftscn(); 1292 } 1293 } 1294 splx(s); 1295 return 1; 1296 } 1297 1298 static int 1299 scnintr(void *arg) 1300 { 1301 struct duart *duart = arg; 1302 struct scn_softc *sc0 = duart->chan[0].sc; 1303 struct scn_softc *sc1 = duart->chan[1].sc; 1304 1305 struct tty *tp0 = (sc0 != NULL) ? sc0->sc_tty : NULL; 1306 struct tty *tp1 = (sc1 != NULL) ? sc1->sc_tty : NULL; 1307 1308 char rs_work; 1309 u_char rs_stat; 1310 u_char rs_ipcr; 1311 1312 /* Check for RX interrupts first, since we cannot distinguish by irq. */ 1313 scnrxintr(duart); 1314 1315 do { 1316 /* Loop to pick up ALL pending interrupts for device. */ 1317 rs_work = false; 1318 rs_stat = duart->base[DU_ISR]; 1319 1320 /* channel a */ 1321 if (tp0 != NULL) { 1322 if ((rs_stat & INT_TXA) && (tp0->t_state & TS_BUSY)) { 1323 /* output char done. */ 1324 tp0->t_state &= ~(TS_BUSY | TS_FLUSH); 1325 1326 /* disable tx ints */ 1327 duart->imr &= ~sc0->sc_tx_int; 1328 duart->base[DU_IMR] = duart->imr; 1329 1330 if (sc0->sc_heldchanges) { 1331 scn_setchip(sc0); 1332 } 1333 1334 (*tp0->t_linesw->l_start) (tp0); 1335 rs_work = true; 1336 } 1337 } 1338 /* channel b */ 1339 if (tp1 != NULL) { 1340 if ((rs_stat & INT_TXB) && (tp1->t_state & TS_BUSY)) { 1341 /* output char done. */ 1342 tp1->t_state &= ~(TS_BUSY | TS_FLUSH); 1343 1344 /* disable tx ints */ 1345 duart->imr &= ~sc1->sc_tx_int; 1346 duart->base[DU_IMR] = duart->imr; 1347 1348 if (sc1->sc_heldchanges) { 1349 scn_setchip(sc1); 1350 } 1351 1352 (*tp1->t_linesw->l_start) (tp1); 1353 rs_work = true; 1354 } 1355 } 1356 if (rs_stat & INT_IP) { 1357 rs_work = true; 1358 rs_ipcr = duart->base[DU_IPCR]; 1359 1360 if (rs_ipcr & IPCR_DELTA_DCDA && tp0 != NULL) { 1361 dcd_int(sc0, tp0, rs_ipcr & IPCR_DCDA); 1362 } 1363 if (rs_ipcr & IPCR_DELTA_DCDB && tp1 != NULL) { 1364 dcd_int(sc1, tp1, rs_ipcr & IPCR_DCDB); 1365 } 1366 } 1367 } while (rs_work); 1368 1369 return (1); /* ? */ 1370 } 1371 1372 /* 1373 * Handle rxrdy/ffull interrupt: QUICKLY poll both channels (checking 1374 * status first) and stash data in a ring buffer. Ring buffer scheme 1375 * borowed from sparc/zs.c requires NO interlock on data! 1376 * 1377 * This interrupt should NOT be included in spltty() mask since it 1378 * invokes NO tty code! The whole point is to allow tty input as much 1379 * of the time as possible, while deferring "heavy" character 1380 * processing until later. 1381 * 1382 * see scn.hw.README and scnsoft() for more info. 1383 * 1384 * THIS ROUTINE SHOULD BE KEPT AS CLEAN AS POSSIBLE!! 1385 * IT'S A CANDIDATE FOR RECODING IN ASSEMBLER!! 1386 */ 1387 static inline int 1388 scn_rxintr(struct scn_softc *sc) 1389 { 1390 char sr; 1391 int i, n; 1392 int work; 1393 1394 work = 0; 1395 i = sc->sc_rbput; 1396 while (work <= 10) { 1397 #define SCN_GETCH(SC) \ 1398 sr = (SC)->sc_chbase[CH_SR]; \ 1399 if ((sr & SR_RX_RDY) == 0) \ 1400 break; \ 1401 if (sr & (SR_PARITY | SR_FRAME | SR_BREAK | SR_OVERRUN)) \ 1402 goto exception; \ 1403 work++; \ 1404 (SC)->sc_rbuf[i++ & SCN_RING_MASK] = (SC)->sc_chbase[CH_DAT] 1405 1406 SCN_GETCH(sc); SCN_GETCH(sc); SCN_GETCH(sc); 1407 /* XXX more here if 26C92? -plb */ 1408 continue; 1409 exception: 1410 #if defined(DDB) 1411 if (sc->sc_isconsole && (sr & SR_BREAK)) { 1412 Debugger(); 1413 sr = sc->sc_chbase[CH_SR]; 1414 } 1415 #endif 1416 #if defined(KGDB) 1417 if (sc->sc_iskgdb && (sr & SR_RX_RDY)) { 1418 kgdb_connect(1); 1419 sr = sc->sc_chbase[CH_SR]; 1420 } 1421 #endif 1422 work++; 1423 sc->sc_rbuf[i++ & SCN_RING_MASK] = (sr << 8) | sc->sc_chbase[CH_DAT]; 1424 sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */ 1425 RECOVER(); 1426 } 1427 /* 1428 * If ring is getting too full, try to block input. 1429 */ 1430 n = i - sc->sc_rbget; 1431 if (sc->sc_rbhiwat && (n > sc->sc_rbhiwat)) { 1432 /* If not CRTSCTS sc_rbhiwat is such that this 1433 * never happens. 1434 * Clear RTS 1435 */ 1436 SCN_OP_BIC(sc, sc->sc_op_rts); 1437 sc->sc_rx_blocked = 1; 1438 } 1439 sc->sc_rbput = i; 1440 1441 return work; 1442 } 1443 1444 static void 1445 scnrxintr(void *arg) 1446 { 1447 struct duart *duart = arg; 1448 int work = 0; 1449 1450 if (duart->chan[0].sc != NULL) 1451 work += scn_rxintr(duart->chan[0].sc); 1452 if (duart->chan[1].sc != NULL) 1453 work += scn_rxintr(duart->chan[1].sc); 1454 if (work > 0) { 1455 setsoftscn(); /* trigger s/w intr */ 1456 #ifdef SCN_TIMING 1457 microtime(&tstart); 1458 #endif 1459 } 1460 } 1461 1462 /* 1463 * Here on soft interrupt (at spltty) to empty ring buffers. 1464 * 1465 * Dave's original scheme was to use the DUART receiver timeout 1466 * interrupt. This requires 2692's (which my board doesn't have), and 1467 * I also liked the idea of using the C/T to generate alternate and/or 1468 * arbitrary bauds. -plb 1469 * 1470 * The ringbuffer code comes from Chris Torek's SPARC 44bsd zs driver 1471 * (hence the LBL notice on top of this file), DOES NOT require 1472 * interlocking with interrupt levels! 1473 * 1474 * The 44bsd sparc/zs driver reads the ring buffer from a separate 1475 * zssoftint, while the SunOS 4.x zs driver appears to use 1476 * timeout()'s. timeouts seem to be too slow to deal with high data 1477 * rates. I know, I tried them. 1478 * -plb. 1479 */ 1480 static void 1481 scnsoft(void *arg) 1482 { 1483 int s, unit; 1484 #ifdef SCN_TIMING 1485 struct timeval tend; 1486 u_long t; 1487 1488 microtime(&tend); 1489 t = (tend.tv_sec - tstart.tv_sec) * 1000000 + (tend.tv_usec - tstart.tv_usec); 1490 t = (t + tick / 20) / (tick / 10); 1491 if (t >= NJITTER - 1) { 1492 t = NJITTER - 1; 1493 } 1494 scn_jitter[t]++; 1495 #endif 1496 1497 for (unit = 0; unit < scn_cd.cd_ndevs; unit++) { 1498 struct scn_softc *sc; 1499 struct tty *tp; 1500 int n, get; 1501 1502 sc = SOFTC(unit); 1503 if (sc == NULL) { 1504 continue; 1505 } 1506 tp = sc->sc_tty; 1507 #ifdef KGDB 1508 if (tp == NULL) { 1509 sc->sc_rbget = sc->sc_rbput; 1510 continue; 1511 } 1512 #endif 1513 if (tp == NULL || tp->t_state & TS_TBLOCK) { 1514 continue; 1515 } 1516 1517 1518 get = sc->sc_rbget; 1519 1520 /* NOTE: fetch from rbput is atomic */ 1521 while (get != (n = sc->sc_rbput)) { 1522 /* 1523 * Compute the number of interrupts in the receive ring. 1524 * If the count is overlarge, we lost some events, and 1525 * must advance to the first valid one. It may get 1526 * overwritten if more data are arriving, but this is 1527 * too expensive to check and gains nothing (we already 1528 * lost out; all we can do at this point is trade one 1529 * kind of loss for another). 1530 */ 1531 n -= get; 1532 if (n > SCN_RING_SIZE) { 1533 scnoverrun(unit, &sc->sc_rotime, "ring"); 1534 get += n - SCN_RING_SIZE; 1535 n = SCN_RING_SIZE; 1536 sc->sc_ring_overruns++; 1537 } 1538 while (--n >= 0) { 1539 int c, sr; 1540 1541 if (tp->t_state & TS_TBLOCK) { 1542 sc->sc_rbget = get; 1543 goto done; 1544 } 1545 /* Race to keep ahead of incoming interrupts. */ 1546 c = sc->sc_rbuf[get++ & SCN_RING_MASK]; 1547 1548 sr = c >> 8; /* extract status */ 1549 c &= 0xff; /* leave just character */ 1550 1551 if (sr & SR_OVERRUN) { 1552 scnoverrun(unit, &sc->sc_fotime, "fifo"); 1553 sc->sc_fifo_overruns++; 1554 } 1555 if (sr & SR_PARITY) { 1556 c |= TTY_PE; 1557 sc->sc_parity_errors++; 1558 } 1559 if (sr & SR_FRAME) { 1560 c |= TTY_FE; 1561 sc->sc_framing_errors++; 1562 } 1563 if (sr & SR_BREAK) { 1564 #if 0 1565 /* 1566 * See DDB_CHECK() comments in 1567 * scnrxintr() 1568 */ 1569 if (sc->sc_isconsole) 1570 Debugger(); 1571 #endif 1572 c = TTY_FE | 0; 1573 sc->sc_breaks++; 1574 } 1575 1576 (*tp->t_linesw->l_rint) (c, tp); 1577 1578 if (sc->sc_rx_blocked && n < SCN_RING_THRESH) { 1579 s = splrtty(); 1580 sc->sc_rx_blocked = 0; 1581 SCN_OP_BIS(sc, sc->sc_op_rts); 1582 splx(s); 1583 } 1584 1585 } 1586 sc->sc_rbget = get; 1587 } 1588 done: ; 1589 } 1590 } 1591 1592 /* Convert TIOCM_xxx bits to output port bits. */ 1593 static unsigned char 1594 opbits(struct scn_softc *sc, int tioc_bits) 1595 { 1596 1597 return ((((tioc_bits) & TIOCM_DTR) ? sc->sc_op_dtr : 0) | 1598 (((tioc_bits) & TIOCM_RTS) ? sc->sc_op_rts : 0)); 1599 } 1600 1601 int 1602 scnioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1603 { 1604 int unit = DEV_UNIT(dev); 1605 struct scn_softc *sc = SOFTC(unit); 1606 struct tty *tp = sc->sc_tty; 1607 int error; 1608 1609 error = (*tp->t_linesw->l_ioctl) (tp, cmd, data, flags, l); 1610 if (error != EPASSTHROUGH) 1611 return (error); 1612 1613 error = ttioctl(tp, cmd, data, flags, l); 1614 if (error != EPASSTHROUGH) 1615 return (error); 1616 1617 switch (cmd) { 1618 case TIOCSBRK: 1619 sc->sc_chbase[CH_CR] = CR_CMD_START_BRK; 1620 break; 1621 1622 case TIOCCBRK: 1623 sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK; 1624 break; 1625 1626 case TIOCSDTR: 1627 SCN_OP_BIS(sc, sc->sc_op_dtr | sc->sc_op_rts); 1628 break; 1629 1630 case TIOCCDTR: 1631 SCN_OP_BIC(sc, sc->sc_op_dtr | sc->sc_op_rts); 1632 break; 1633 1634 case TIOCMSET: { 1635 int s; 1636 unsigned char sbits, cbits; 1637 1638 /* set bits */ 1639 sbits = opbits(sc, *(int *) data); 1640 1641 /* get bits to clear */ 1642 cbits = ~sbits & (sc->sc_op_dtr | sc->sc_op_rts); 1643 1644 s = spltty(); 1645 if (sbits) { 1646 SCN_OP_BIS(sc, sbits); 1647 } 1648 if (cbits) { 1649 SCN_OP_BIC(sc, cbits); 1650 } 1651 splx(s); 1652 break; 1653 } 1654 1655 case TIOCMBIS: 1656 SCN_OP_BIS(sc, opbits(sc, *(int *) data)); 1657 break; 1658 1659 case TIOCMBIC: 1660 SCN_OP_BIC(sc, opbits(sc, *(int *) data)); 1661 break; 1662 1663 case TIOCMGET: { 1664 int bits; 1665 unsigned char ip, op; 1666 1667 /* s = spltty(); */ 1668 ip = sc->sc_duart->base[DU_IP]; 1669 /* 1670 * XXX sigh; cannot get op current state!! even if 1671 * maintained in private, RTS is done in h/w!! 1672 */ 1673 op = 0; 1674 /* splx(s); */ 1675 1676 bits = 0; 1677 if (ip & sc->sc_ip_dcd) 1678 bits |= TIOCM_CD; 1679 if (ip & sc->sc_ip_cts) 1680 bits |= TIOCM_CTS; 1681 1682 #if 0 1683 if (op & sc->sc_op_dtr) 1684 bits |= TIOCM_DTR; 1685 if (op & sc->sc_op_rts) 1686 bits |= TIOCM_RTS; 1687 #endif 1688 1689 *(int *) data = bits; 1690 break; 1691 } 1692 1693 case TIOCGFLAGS:{ 1694 int bits = 0; 1695 1696 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1697 bits |= TIOCFLAG_SOFTCAR; 1698 if (sc->sc_swflags & SCN_SW_CLOCAL) 1699 bits |= TIOCFLAG_CLOCAL; 1700 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1701 bits |= TIOCFLAG_CRTSCTS; 1702 if (sc->sc_swflags & SCN_SW_MDMBUF) 1703 bits |= TIOCFLAG_MDMBUF; 1704 1705 *(int *) data = bits; 1706 break; 1707 } 1708 case TIOCSFLAGS:{ 1709 int userbits, driverbits = 0; 1710 1711 error = kauth_authorize_device_tty(l->l_cred, 1712 KAUTH_DEVICE_TTY_PRIVSET, tp); 1713 if (error != 0) 1714 return (EPERM); 1715 1716 userbits = *(int *) data; 1717 if (userbits & TIOCFLAG_SOFTCAR) 1718 driverbits |= SCN_SW_SOFTCAR; 1719 if (userbits & TIOCFLAG_CLOCAL) 1720 driverbits |= SCN_SW_CLOCAL; 1721 if (userbits & TIOCFLAG_CRTSCTS) 1722 driverbits |= SCN_SW_CRTSCTS; 1723 if (userbits & TIOCFLAG_MDMBUF) 1724 driverbits |= SCN_SW_MDMBUF; 1725 1726 sc->sc_swflags = driverbits; 1727 1728 break; 1729 } 1730 1731 default: 1732 return (EPASSTHROUGH); 1733 } 1734 return (0); 1735 } 1736 1737 int 1738 scnparam(struct tty *tp, struct termios *t) 1739 { 1740 int cflag = t->c_cflag; 1741 int unit = DEV_UNIT(tp->t_dev); 1742 char mr1, mr2; 1743 int error; 1744 struct scn_softc *sc = SOFTC(unit); 1745 1746 /* Is this a hang up? */ 1747 if (t->c_ospeed == B0) { 1748 SCN_OP_BIC(sc, sc->sc_op_dtr); 1749 /* leave DTR down. see comment in scnclose() -plb */ 1750 return (0); 1751 } 1752 mr1 = mr2 = 0; 1753 1754 /* Parity? */ 1755 if (cflag & PARENB) { 1756 if ((cflag & PARODD) == 0) 1757 mr1 |= MR1_PEVEN; 1758 else 1759 mr1 |= MR1_PODD; 1760 } else 1761 mr1 |= MR1_PNONE; 1762 1763 /* Stop bits. */ 1764 if (cflag & CSTOPB) 1765 mr2 |= MR2_STOP2; 1766 else 1767 mr2 |= MR2_STOP1; 1768 1769 /* Data bits. */ 1770 switch (cflag & CSIZE) { 1771 case CS5: 1772 mr1 |= MR1_CS5; 1773 break; 1774 case CS6: 1775 mr1 |= MR1_CS6; 1776 break; 1777 case CS7: 1778 mr1 |= MR1_CS7; 1779 break; 1780 case CS8: 1781 default: 1782 mr1 |= MR1_CS8; 1783 break; 1784 } 1785 1786 if (cflag & CCTS_OFLOW) 1787 mr2 |= MR2_TXCTS; 1788 1789 if (cflag & CRTS_IFLOW) { 1790 mr1 |= MR1_RXRTS; 1791 sc->sc_rbhiwat = SCN_RING_HIWAT; 1792 } else { 1793 sc->sc_rbhiwat = 0; 1794 } 1795 1796 error = scn_config(unit, sc->sc_channel, t->c_ispeed, 1797 t->c_ospeed, mr1, mr2); 1798 1799 /* If successful, copy to tty */ 1800 if (!error) { 1801 tp->t_ispeed = t->c_ispeed; 1802 tp->t_ospeed = t->c_ospeed; 1803 tp->t_cflag = cflag; 1804 } 1805 return (error); 1806 } 1807 1808 /* 1809 * Start or restart a transmission. 1810 */ 1811 void 1812 scnstart(struct tty *tp) 1813 { 1814 int s, c; 1815 int unit = DEV_UNIT(tp->t_dev); 1816 struct scn_softc *sc = SOFTC(unit); 1817 1818 s = spltty(); 1819 if (tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1820 goto out; 1821 if (!ttypull(tp)) 1822 goto out; 1823 1824 tp->t_state |= TS_BUSY; 1825 1826 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) { 1827 if ((c = getc(&tp->t_outq)) == -1) 1828 break; 1829 sc->sc_chbase[CH_DAT] = c; 1830 } 1831 sc->sc_duart->imr |= (sc->sc_tx_int | sc->sc_rx_int); 1832 sc->sc_duart->base[DU_IMR] = sc->sc_duart->imr; 1833 1834 out: 1835 splx(s); 1836 } 1837 1838 /* 1839 * Stop output on a line. 1840 */ 1841 /*ARGSUSED*/ 1842 void 1843 scnstop(struct tty *tp, int flags) 1844 { 1845 int s; 1846 1847 s = spltty(); 1848 if (tp->t_state & TS_BUSY) { 1849 if ((tp->t_state & TS_TTSTOP) == 0) 1850 tp->t_state |= TS_FLUSH; 1851 } 1852 splx(s); 1853 } 1854 1855 /* 1856 * Following are all routines needed for SCN to act as console. 1857 */ 1858 1859 void 1860 scncnprobe(struct consdev *cn) 1861 { 1862 } 1863 1864 void 1865 scncnreinit(void *v) 1866 { 1867 volatile u_char *du_base = 1868 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1869 1870 du_base[DU_OPSET] = 1871 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1872 } 1873 1874 void 1875 scncninit(struct consdev *cn) 1876 { 1877 devmajor_t major; 1878 1879 /* initialize required fields */ 1880 major = cdevsw_lookup_major(&scn_cdevsw); 1881 KASSERT(major != NODEV); 1882 cn->cn_dev = makedev(major, SCN_CONSOLE); 1883 cn->cn_pri = CN_REMOTE; 1884 1885 scninit(cn->cn_dev, scnconsrate); 1886 } 1887 1888 /* Used by scncninit and kgdb startup. */ 1889 int 1890 scninit(dev_t dev, int rate) 1891 { 1892 /* XXX - maintain PROM's settings */ 1893 #if 0 1894 volatile u_char *du_base = 1895 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1896 int unit = DEV_UNIT(dev); 1897 1898 du_base[DU_OPSET] = 1899 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1900 scn_config(unit, SCN_CONSCHAN, rate, rate, 1901 MR1_PNONE | MR1_CS8, MR2_STOP1); 1902 #endif 1903 return (0); 1904 } 1905 1906 /* 1907 * Console kernel input character routine. 1908 */ 1909 int 1910 scncngetc(dev_t dev) 1911 { 1912 volatile u_char *ch_base = 1913 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1914 char c; 1915 int s; 1916 1917 s = spltty(); 1918 1919 while ((ch_base[CH_SR] & SR_RX_RDY) == 0) 1920 ; 1921 c = ch_base[CH_DAT]; 1922 1923 splx(s); 1924 return c; 1925 } 1926 1927 void 1928 scncnpollc(dev_t dev, int on) 1929 { 1930 } 1931 1932 /* 1933 * Console kernel output character routine. 1934 */ 1935 void 1936 scncnputc(dev_t dev, int c) 1937 { 1938 volatile u_char *ch_base = 1939 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1940 volatile u_char *du_base = 1941 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1942 int s; 1943 1944 s = spltty(); 1945 1946 if (c == '\n') 1947 scncnputc(dev, '\r'); 1948 1949 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1950 ; 1951 ch_base[CH_DAT] = c; 1952 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1953 ; 1954 du_base[DU_ISR]; 1955 1956 splx(s); 1957 } 1958