1 /* $NetBSD: scn.c,v 1.2 2009/11/21 17:40:28 rmind Exp $ */ 2 3 /* 4 * Resurrected from the old pc532 port 1/18/2009. 5 * 6 * XXX- The locking in this is probably totally broken. I haven't attempted 7 * to get it right, but it seems to work okay anyhow. 8 */ 9 10 /* 11 * Copyright (c) 1991, 1992, 1993 12 * The Regents of the University of California. All rights reserved. 13 * 14 * Portions of this software were developed by the Computer Systems 15 * Engineering group at Lawrence Berkeley Laboratory under DARPA 16 * contract BG 91-66 and contributed to Berkeley. 17 * 18 * All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Lawrence Berkeley Laboratory. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 48 */ 49 50 /* 51 * Copyright (c) 1996, 1997 Philip L. Budne. 52 * Copyright (c) 1993 Philip A. Nelson. 53 * 54 * Portions of this software were developed by the Computer Systems 55 * Engineering group at Lawrence Berkeley Laboratory under DARPA 56 * contract BG 91-66 and contributed to Berkeley. 57 * 58 * All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Lawrence Berkeley Laboratory. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 3. All advertising materials mentioning features or use of this software 72 * must display the following acknowledgement: 73 * This product includes software developed by the University of 74 * California, Berkeley and its contributors. 75 * 4. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 #include <sys/cdefs.h> 95 __KERNEL_RCSID(0, "$NetBSD: scn.c,v 1.2 2009/11/21 17:40:28 rmind Exp $"); 96 97 #include "opt_ddb.h" 98 #include "opt_kgdb.h" 99 #include "scn.h" 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/file.h> 108 #include <sys/uio.h> 109 #include <sys/kernel.h> 110 #include <sys/syslog.h> 111 #include <sys/types.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/conf.h> 115 #include <sys/intr.h> 116 #ifdef KGDB 117 #include <sys/kgdb.h> 118 #endif 119 #include <sys/kauth.h> 120 121 #include <dev/cons.h> 122 123 #include <machine/autoconf.h> 124 #include <machine/machtype.h> 125 126 #include <sgimips/dev/scnreg.h> 127 #include <sgimips/dev/scnvar.h> 128 129 int scn_match(device_t, struct cfdata *, void *); 130 void scn_attach(device_t, device_t, void *); 131 int scnparam(struct tty *, struct termios *); 132 void scnstart(struct tty *); 133 int scnhwiflow(struct tty *, int); 134 135 void scncnprobe(struct consdev *); 136 void scncninit(struct consdev *); 137 int scncngetc(dev_t); 138 void scncnputc(dev_t, int); 139 void scncnpollc(dev_t, int); 140 int scninit(dev_t, int); 141 void scncnreinit(void *); 142 143 CFATTACH_DECL(scn, sizeof(struct scn_softc), 144 scn_match, scn_attach, NULL, NULL); 145 146 extern struct cfdriver scn_cd; 147 148 dev_type_open(scnopen); 149 dev_type_close(scnclose); 150 dev_type_read(scnread); 151 dev_type_write(scnwrite); 152 dev_type_ioctl(scnioctl); 153 dev_type_stop(scnstop); 154 dev_type_tty(scntty); 155 dev_type_poll(scnpoll); 156 157 const struct cdevsw scn_cdevsw = { 158 scnopen, scnclose, scnread, scnwrite, scnioctl, 159 scnstop, scntty, scnpoll, nommap, ttykqfilter, D_TTY 160 }; 161 162 struct consdev scn_cn = { 163 scncnprobe, 164 scncninit, 165 scncngetc, 166 scncnputc, 167 scncnpollc, 168 NULL, 169 NULL, 170 NULL, 171 NODEV, 172 CN_NORMAL 173 }; 174 175 #ifndef CONSOLE_SPEED 176 #define CONSOLE_SPEED TTYDEF_SPEED 177 #endif 178 179 #ifndef SCNDEF_CFLAG 180 #define SCNDEF_CFLAG TTYDEF_CFLAG 181 #endif 182 183 #ifdef CPU30MHZ 184 #define RECOVER() __asm volatile("bispsrw 0x800" : : : "cc") 185 #else 186 #define RECOVER() 187 #endif 188 189 int scndefaultrate = TTYDEF_SPEED; 190 int scnconsrate = CONSOLE_SPEED; 191 192 static inline struct scn_softc * 193 SOFTC(int unit) 194 { 195 if (unit < 0 || unit >= scn_cd.cd_ndevs) 196 return (NULL); 197 return ((struct scn_softc *)scn_cd.cd_devs[unit]); 198 } 199 200 static int scnintr(void *); 201 static void scnrxintr(void *); 202 static int scn_rxintr(struct scn_softc *); 203 static void scnsoft(void *); 204 static void scn_setchip(struct scn_softc *sc); 205 static int scniter(int *, int, int*, int*, struct chan *, int); 206 static int scn_config(int, int, int, int, u_char, u_char); 207 static void scn_rxenable(struct scn_softc *); 208 static void scn_rxdisable(struct scn_softc *); 209 static void dcd_int(struct scn_softc *, struct tty *, u_char); 210 static void scnoverrun(int, long *, const char *); 211 static u_char opbits(struct scn_softc *, int); 212 213 static void *scnsir = NULL; /* s/w intr cookie */ 214 #define setsoftscn() softint_schedule(scnsir) 215 216 #ifdef SCN_TIMING 217 /* 218 * Keep timing info on latency of software interrupt used by 219 * the ringbuf code to empty ring buffer. 220 * "getinfo" program reads data from /dev/kmem. 221 */ 222 static struct timeval tstart; 223 #define NJITTER 100 224 int scn_njitter = NJITTER; 225 int scn_jitter[NJITTER]; 226 #endif 227 228 #define SCN_CLOCK 3686400 /* input clock */ 229 230 /* speed table groups ACR[7] */ 231 #define GRP_A 0 232 #define GRP_B ACR_BRG 233 234 /* combo of MR0[2:0] and ACR[7] */ 235 #define MODE0A MR0_MODE_0 236 #define MODE0B (MR0_MODE_0|ACR_BRG) 237 #define MODE1A MR0_MODE_1 238 #define MODE1B (MR0_MODE_1|ACR_BRG) 239 #define MODE2A MR0_MODE_2 240 #define MODE2B (MR0_MODE_2|ACR_BRG) 241 242 #define ANYMODE -1 243 #define DEFMODE(C92) MODE0A /* use MODE4A if 26c92? */ 244 245 /* speed code for Counter/Timer (all modes, groups) */ 246 #define USE_CT 0xd 247 248 /* 249 * Rate table, ordered by speed, then mode. 250 * NOTE: ordering of modes must be done carefully! 251 */ 252 struct tabent { 253 int32_t speed; 254 int16_t code; 255 int16_t mode; 256 } table[] = { 257 { 50, 0x0, MODE0A }, 258 { 75, 0x0, MODE0B }, 259 { 110, 0x1, MODE0A }, 260 { 110, 0x1, MODE0B }, 261 { 110, 0x1, MODE1A }, 262 { 110, 0x1, MODE1B }, 263 { 134, 0x2, MODE0A }, /* 134.5 */ 264 { 134, 0x2, MODE0B }, /* 134.5 */ 265 { 134, 0x2, MODE1A }, /* 134.5 */ 266 { 134, 0x2, MODE1B }, /* 134.5 */ 267 { 150, 0x3, MODE0A }, 268 { 150, 0x3, MODE0A }, 269 { 200, 0x3, MODE0A }, 270 { 300, 0x4, MODE0A }, 271 { 300, 0x4, MODE0B }, 272 { 300, 0x0, MODE1A }, 273 { 450, 0x0, MODE1B }, 274 { 600, 0x5, MODE0A }, 275 { 600, 0x5, MODE0B }, 276 { 880, 0x1, MODE2A }, 277 { 880, 0x1, MODE2B }, 278 { 900, 0x3, MODE1B }, 279 { 1050, 0x7, MODE0A }, 280 { 1050, 0x7, MODE1A }, 281 { 1076, 0x2, MODE2A }, 282 { 1076, 0x2, MODE2B }, 283 { 1200, 0x6, MODE0A }, 284 { 1200, 0x6, MODE0B }, 285 { 1200, 0x3, MODE1A }, 286 { 1800, 0xa, MODE0B }, 287 { 1800, 0x4, MODE1A }, 288 { 1800, 0x4, MODE1B }, 289 { 2000, 0x7, MODE0B }, 290 { 2000, 0x7, MODE1B }, 291 { 2400, 0x8, MODE0A }, 292 { 2400, 0x8, MODE0B }, 293 { 3600, 0x5, MODE1A }, 294 { 3600, 0x5, MODE1B }, 295 { 4800, 0x9, MODE2A }, 296 { 4800, 0x9, MODE2B }, 297 { 4800, 0x9, MODE0A }, 298 { 4800, 0x9, MODE0B }, 299 { 7200, 0xa, MODE0A }, 300 { 7200, 0x0, MODE2B }, 301 { 7200, 0x6, MODE1A }, 302 { 7200, 0x6, MODE1B }, 303 { 9600, 0xb, MODE2A }, 304 { 9600, 0xb, MODE2B }, 305 { 9600, 0xb, MODE0A }, 306 { 9600, 0xb, MODE0B }, 307 { 9600, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 308 { 9600, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 309 { 14400, 0x3, MODE2B }, 310 { 14400, 0x8, MODE1A }, 311 { 14400, 0x8, MODE1B }, 312 { 19200, 0x3, MODE2A }, 313 { 19200, 0xc, MODE2B }, 314 { 19200, 0xc, MODE0B }, 315 { 19200, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 316 { 19200, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 317 { 28800, 0x4, MODE2A }, 318 { 28800, 0x4, MODE2B }, 319 { 28800, 0x9, MODE1A }, 320 { 28800, 0x9, MODE1B }, 321 { 38400, 0xc, MODE2A }, 322 { 38400, 0xc, MODE0A }, 323 { 57600, 0x5, MODE2A }, 324 { 57600, 0x5, MODE2B }, 325 { 57600, 0xb, MODE1A }, 326 { 57600, 0xb, MODE1B }, 327 { 115200, 0x6, MODE2A }, 328 { 115200, 0x6, MODE2B }, 329 { 115200, 0xc, MODE1B }, 330 { 230400, 0xc, MODE1A } 331 }; 332 #define TABENTRIES (sizeof(table)/sizeof(table[0])) 333 334 /* 335 * boolean for speed codes which are identical in both A/B BRG groups 336 * in all modes 337 */ 338 static u_char bothgroups[16] = { 339 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1 340 }; 341 342 /* 343 * Manually constructed divisors table 344 * for minimum error (from some of Dave Rand's code) 345 */ 346 const struct { 347 uint16_t speed; 348 uint16_t div; 349 } divs[] = { 350 { 50, 2303 }, /* 2304 is exact?? */ 351 { 110, 1047 }, /* Should be 1047.27 */ 352 { 134, 857 }, /* Should be 856.505576 */ 353 { 1050, 110 }, /* Should be 109.7142857 */ 354 { 2000, 57 } /* Should be 57.6 */ 355 }; 356 #define DIVS (sizeof(divs)/sizeof(divs[0])) 357 358 /* 359 * minor unit bit decode: 360 * CxxxUUU 361 * 362 * C - carrier 363 * 0 - delay open until carrier high 364 * 1 - allow open with carrier low 365 * UUU - unit 0-7 366 */ 367 368 #define DEV_UNIT(x) (minor(x) & 0x7) 369 #define DEV_DIALOUT(x) (minor(x) & 0x80) 370 371 extern struct tty *constty; 372 373 #define SCN_MAXDUART 4 374 static struct duart scn_duart[SCN_MAXDUART]; 375 376 #ifdef KGDB 377 extern int kgdb_dev; 378 extern int kgdb_rate; 379 extern int kgdb_debug_init; 380 #endif 381 382 /* XXXXX - fix this */ 383 #define splrtty() spltty() 384 385 /* RS-232 configuration routines */ 386 387 /* 388 * set chip parameters, or mark for delayed change. 389 * called at spltty() or on TxEMPTY interrupt. 390 * 391 * Reads current values to avoid glitches from redundant sets. 392 * Perhaps should save last value set to avoid read/write? NOTE: 393 * Would still need to do read if write not needed to advance MR 394 * pointer. 395 * 396 * new 2/97 -plb 397 */ 398 399 static void 400 scn_setchip(struct scn_softc *sc) 401 { 402 struct duart *dp; 403 u_char acr, csr, mr1, mr2; 404 int chan; 405 406 if (sc->sc_tty && (sc->sc_tty->t_state & TS_BUSY)) { 407 sc->sc_heldchanges = 1; 408 return; 409 } 410 411 chan = sc->sc_channel; 412 dp = sc->sc_duart; 413 if (dp->type == SC26C92) { 414 u_char nmr0a, mr0a; 415 416 /* input rate high enough so 64 bit time watchdog not 417 * onerous? */ 418 if (dp->chan[chan].ispeed >= 1200) { 419 /* set FIFO threshold at 6 for other 420 * thresholds we could have to set MR1_FFULL 421 */ 422 dp->chan[chan].mr0 |= MR0_RXWD | MR0_RXINT; 423 } else { 424 dp->chan[chan].mr0 &= ~(MR0_RXWD | MR0_RXINT); 425 } 426 427 /* select BRG mode (MR0A only) */ 428 nmr0a = dp->chan[0].mr0 | (dp->mode & MR0_MODE); 429 430 dp->base[CH_CR] = CR_CMD_MR0; 431 RECOVER(); 432 433 mr0a = dp->base[CH_MR]; 434 if (mr0a != nmr0a) { 435 dp->base[CH_CR] = CR_CMD_MR0; 436 RECOVER(); 437 dp->base[CH_MR] = nmr0a; 438 } 439 440 if (chan) { /* channel B? */ 441 u_char mr0b; 442 443 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 444 RECOVER(); 445 mr0b = dp->base[CH_MR]; 446 447 if (dp->chan[chan].mr0 != mr0b) { 448 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 449 RECOVER(); 450 sc->sc_chbase[CH_MR] = dp->chan[chan].mr0; 451 } 452 } 453 } else { 454 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 455 RECOVER(); 456 } 457 458 mr1 = sc->sc_chbase[CH_MR]; 459 mr2 = sc->sc_chbase[CH_MR]; 460 if (mr1 != dp->chan[chan].new_mr1 || 461 mr2 != dp->chan[chan].new_mr2) { 462 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 463 RECOVER(); 464 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr1; 465 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr2; 466 } 467 468 acr = dp->acr | (dp->mode & ACR_BRG); 469 dp->base[DU_ACR] = acr; /* write-only reg! */ 470 471 /* set speed codes */ 472 csr = (dp->chan[chan].icode<<4) | dp->chan[chan].ocode; 473 if (sc->sc_chbase[CH_CSR] != csr) { 474 sc->sc_chbase[CH_CSR] = csr; 475 } 476 477 /* see if counter/timer in use */ 478 if (dp->counter && 479 (dp->chan[0].icode == USE_CT || dp->chan[0].ocode == USE_CT || 480 dp->chan[1].icode == USE_CT || dp->chan[1].ocode == USE_CT)) { 481 482 /* program counter/timer only if necessary */ 483 if (dp->counter != dp->ocounter) { 484 uint16_t div; 485 #ifdef DIVS 486 int i; 487 488 /* look for precalculated rate, for minimum error */ 489 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { 490 if (divs[i].speed == dp->counter) { 491 div = divs[i].div; 492 goto found; 493 } 494 } 495 #endif 496 497 /* not found in table; calculate a value (rounding up) */ 498 div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter; 499 500 found: 501 /* halt before loading? may ALWAYS glitch? 502 * reload race may only sometimes glitch?? 503 */ 504 dp->base[DU_CTUR] = div >> 8; 505 dp->base[DU_CTLR] = div & 255; 506 if (dp->ocounter == 0) { 507 /* not previously used? */ 508 u_char temp; 509 /* start C/T running */ 510 temp = dp->base[DU_CSTRT]; 511 } 512 dp->ocounter = dp->counter; 513 } 514 } else { 515 /* counter not in use; mark as free */ 516 dp->counter = 0; 517 } 518 sc->sc_heldchanges = 0; 519 520 /* 521 * delay a tiny bit to try and avoid tx glitching. 522 * I know we're at spltty(), but this is much better than the 523 * old version used DELAY((96000 / out_speed) * 10000) 524 * -plb 525 */ 526 DELAY(10); 527 } 528 529 /* 530 * iterator function for speeds. 531 * (could be called "findnextcode") 532 * Returns sequence of possible speed codes for a given rate. 533 * should set index to zero before first call. 534 * 535 * Could be implemented as a "checkspeed()" function called 536 * to evaluate table entries, BUT this allows more variety in 537 * use of C/T with fewer table entries. 538 */ 539 540 static int 541 scniter(int *index, int wanted, int *counter, int *mode, struct chan *other, 542 int c92) 543 { 544 545 while (*index < TABENTRIES) { 546 struct tabent *tp; 547 548 tp = table + (*index)++; 549 if (tp->speed != wanted) 550 continue; 551 552 /* if not a 26C92 only look at MODE0 entries */ 553 if (!c92 && (tp->mode & MR0_MODE) != MR0_MODE_0) 554 continue; 555 556 /* 557 * check mode; 558 * OK if this table entry for current mode, or mode not 559 * yet set, or other channel's rates are available in both 560 * A and B groups. 561 */ 562 563 if (tp->mode == *mode || *mode == ANYMODE || 564 (other != NULL && (tp->mode & MR0_MODE) == (*mode & MR0_MODE) && 565 bothgroups[other->icode] && bothgroups[other->ocode])) { 566 /* 567 * for future table entries specifying 568 * use of counter/timer 569 */ 570 if (tp->code == USE_CT) { 571 if (*counter != wanted && *counter != 0) 572 continue; /* counter busy */ 573 *counter = wanted; 574 } 575 *mode = tp->mode; 576 return tp->code; 577 } 578 } 579 580 /* here after returning all applicable table entries */ 581 /* XXX return sequence of USE_CT with all possible modes?? */ 582 if ((*index)++ == TABENTRIES) { 583 /* Max C/T rate (even on 26C92?) is 57600 */ 584 if (wanted <= 57600 && (*counter == wanted || *counter == 0)) { 585 *counter = wanted; 586 return USE_CT; 587 } 588 } 589 590 return -1; /* FAIL */ 591 } 592 593 /* 594 * calculate configuration 595 * rewritten 2/97 -plb 596 */ 597 static int 598 scn_config(int unit, int chan, int ispeed, int ospeed, u_char mr1, u_char mr2) 599 { 600 struct scn_softc *sc; 601 struct duart *dp; 602 int other; /* opposite of chan */ 603 int mode; 604 int counter; 605 int i, o; /* input, output iterator indexes */ 606 int ic, oc; /* input, output codes */ 607 struct chan *ocp; /* other duart channel */ 608 struct tty *otp; /* other channel tty struct */ 609 int c92; /* true if duart is sc26c92 */ 610 int s; 611 612 /* Set up softc pointer. */ 613 if (unit >= scn_cd.cd_ndevs) 614 return ENXIO; 615 sc = SOFTC(unit); 616 chan = sc->sc_channel; 617 other = chan ^ 1; 618 dp = sc->sc_duart; 619 ocp = &dp->chan[other]; 620 otp = ocp->tty; 621 c92 = (dp->type == SC26C92); 622 623 /* 624 * Right now the first combination that works is used. 625 * Perhaps it should search entire solution space for "best" 626 * combination. For example, use heuristic weighting of mode 627 * preferences, and use of counter timer? 628 * 629 * For example right now with 2681/2692 when default rate is 630 * 9600 and other channel is closed setting 19200 will pick 631 * mode 0a and use counter/timer. Better solution might be 632 * mode 0b, leaving counter/timer free! 633 * 634 * When other channel is open might want to prefer 635 * leaving counter timer free, or not flipping A/B group? 636 */ 637 if (otp && (otp->t_state & TS_ISOPEN)) { 638 639 /* 640 * Other channel open; 641 * Find speed codes compatible with current mode/counter. 642 */ 643 644 i = 0; 645 for (;;) { 646 mode = dp->mode; 647 counter = dp->counter; 648 649 /* NOTE: pass other chan pointer to allow group flipping */ 650 ic = scniter(&i, ispeed, &counter, &mode, ocp, c92); 651 if (ic == -1) 652 break; 653 654 o = 0; 655 if ((oc = scniter(&o, ospeed, &counter, 656 &mode, NULL, c92)) != -1) { 657 /* 658 * take first match 659 * 660 * Perhaps calculate heuristic "score", 661 * save score,codes,mode,counter if score 662 * better than previous best? 663 */ 664 goto gotit; 665 } 666 } 667 /* XXX try looping for ospeed? */ 668 } else { 669 /* other channel closed */ 670 int oo, oi; /* other input, output iterators */ 671 int oic, ooc; /* other input, output codes */ 672 673 /* 674 * Here when other channel closed. Finds first 675 * combination that will allow other channel to be opened 676 * (with defaults) and fits our needs. 677 */ 678 oi = 0; 679 for (;;) { 680 mode = ANYMODE; 681 counter = 0; 682 683 oic = scniter(&oi, ocp->ispeed, &counter, &mode, NULL, c92); 684 if (oic == -1) 685 break; 686 687 oo = 0; 688 while ((ooc = scniter(&oo, ocp->ospeed, &counter, 689 &mode, NULL, c92)) != -1) { 690 i = 0; 691 while ((ic = scniter(&i, ispeed, &counter, 692 &mode, NULL, c92)) != -1) { 693 o = 0; 694 if ((oc = scniter(&o, ospeed, &counter, 695 &mode, NULL, c92)) != -1) { 696 /* 697 * take first match 698 * 699 * Perhaps calculate heuristic 700 * "score", save 701 * score,codes,mode,counter 702 * if score better than 703 * previous best? 704 */ 705 s = spltty(); 706 dp->chan[other].icode = oic; 707 dp->chan[other].ocode = ooc; 708 goto gotit2; 709 } 710 } 711 } 712 } 713 } 714 return EINVAL; 715 716 gotit: 717 s = spltty(); 718 gotit2: 719 dp->chan[chan].new_mr1 = mr1; 720 dp->chan[chan].new_mr2 = mr2; 721 dp->chan[chan].ispeed = ispeed; 722 dp->chan[chan].ospeed = ospeed; 723 dp->chan[chan].icode = ic; 724 dp->chan[chan].ocode = oc; 725 if (mode == ANYMODE) /* no mode selected?? */ 726 mode = DEFMODE(c92); 727 dp->mode = mode; 728 dp->counter = counter; 729 730 scn_setchip(sc); /* set chip now, if possible */ 731 splx(s); 732 return (0); 733 } 734 735 int 736 scn_match(device_t parent, struct cfdata *cf, void *aux) 737 { 738 struct mainbus_attach_args *ma = aux; 739 740 if ((mach_type == MACH_SGI_IP6 || mach_type == MACH_SGI_IP10) && 741 ma->ma_addr == 0x1fb80004) 742 return (1); 743 744 return (0); 745 } 746 747 /* 748 * No need to make scn_rx{en,dis}able too efficient, 749 * they're only called on setup, open & close! 750 */ 751 static inline void 752 scn_rxenable(struct scn_softc *sc) 753 { 754 struct duart *dp; 755 int channel; 756 757 dp = sc->sc_duart; 758 channel = sc->sc_channel; 759 760 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 761 if (channel == 0) 762 dp->opcr |= OPCR_OP4_RXRDYA; 763 else 764 dp->opcr |= OPCR_OP5_RXRDYB; 765 dp->base[DU_OPCR] = dp->opcr; 766 dp->imr |= sc->sc_rx_int; 767 dp->base[DU_IMR] = dp->imr; 768 } 769 770 static inline void 771 scn_rxdisable(struct scn_softc *sc) 772 { 773 struct duart *dp; 774 int channel; 775 776 dp = sc->sc_duart; 777 channel = sc->sc_channel; 778 779 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 780 if (channel == 0) 781 dp->opcr &= ~OPCR_OP4_RXRDYA; 782 else 783 dp->opcr &= ~OPCR_OP5_RXRDYB; 784 dp->base[DU_OPCR] = dp->opcr; 785 dp->imr &= ~sc->sc_rx_int; 786 dp->base[DU_IMR] = dp->imr; 787 } 788 789 void 790 scn_attach(device_t parent, device_t self, void *aux) 791 { 792 struct mainbus_attach_args *ma = aux; 793 struct scn_softc *sc; 794 struct duart *duart; 795 volatile u_char *ch_base; 796 volatile u_char *duart_base; 797 int channel; 798 int speed; 799 int s; 800 int maj; 801 u_char unit; 802 u_char duartno; 803 u_char delim = ':'; 804 u_char mr1, mr2; 805 enum scntype scntype = SCNUNK; 806 const char *duart_type = "Unknown"; 807 char *intrname; 808 bool console, first; 809 devmajor_t major; 810 811 (void)major; 812 813 sc = device_private(self); 814 unit = device_unit(self); 815 816 /* XXX - hard-coded */ 817 if (ma->ma_addr == 0x1fb80004) 818 duartno = 1; 819 else 820 duartno = 0; 821 channel = 0; 822 console = 1; 823 824 duart = sc->sc_duart = &scn_duart[duartno]; 825 duart->chan[channel].sc = sc; 826 first = (duart->base == NULL); 827 828 if (console) { 829 sc->sc_isconsole = 1; 830 sc->sc_swflags |= SCN_SW_SOFTCAR; /* ignore carrier */ 831 } 832 833 duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr); 834 ch_base = duart_base; /* XXX */ 835 836 if (first) { 837 /* Probe DUART type */ 838 s = spltty(); 839 if (console) { 840 ch_base[CH_CR] = CR_DIS_TX; 841 delay(5 * 10000); 842 } 843 ch_base[CH_CR] = CR_CMD_MR1; 844 RECOVER(); 845 mr1 = ch_base[CH_MR]; 846 mr2 = ch_base[CH_MR]; 847 ch_base[CH_CR] = CR_CMD_MR1; 848 RECOVER(); 849 ch_base[CH_MR] = 1; 850 ch_base[CH_MR] = 0; 851 ch_base[CH_CR] = CR_CMD_MR1; 852 RECOVER(); 853 if (ch_base[CH_MR] == 1) { 854 /* MR 2 selected */ 855 ch_base[CH_CR] = CR_CMD_MR0; 856 RECOVER(); 857 /* if 2681, MR2 still selected */ 858 ch_base[CH_MR] = 1; 859 ch_base[CH_CR] = CR_CMD_MR1; 860 RECOVER(); 861 ch_base[CH_MR] = 0; /* MR1 */ 862 ch_base[CH_MR] = 0; /* MR2 */ 863 ch_base[CH_CR] = CR_CMD_MR0; 864 RECOVER(); 865 /* if 2681, MR2 still selected */ 866 if((ch_base[CH_MR] & 1) == 1) { 867 duart_type = "sc26c92"; 868 scntype = SC26C92; 869 } else { 870 /* 2681 treats as MR1 Select */ 871 ch_base[CH_CR] = CR_CMD_RTS_OFF; 872 RECOVER(); 873 ch_base[CH_MR] = 1; 874 ch_base[CH_MR] = 0; 875 ch_base[CH_CR] = CR_CMD_RTS_OFF; 876 RECOVER(); 877 if (ch_base[CH_MR] == 1) { 878 duart_type = "scn2681"; 879 scntype = SCN2681; 880 } else { 881 duart_type = "scn2692"; 882 scntype = SCN2692; 883 } 884 } 885 } 886 887 /* If a 2681, the CR_CMD_MR0 is interpreted as a TX_RESET */ 888 if (console) { 889 ch_base[CH_CR] = CR_ENA_TX; 890 RECOVER(); 891 } 892 ch_base[CH_CR] = CR_CMD_MR1; 893 RECOVER(); 894 ch_base[CH_MR] = mr1; 895 ch_base[CH_MR] = mr2; 896 splx(s); 897 898 intrname = malloc(sizeof("scnXX"), M_DEVBUF, M_NOWAIT); 899 snprintf(intrname, sizeof("scnXX"), "scn%d", unit); 900 901 /* 902 * On IP6 the console chip is duart1. The keyboard/mouse 903 * is duart0. Each chip has two channels and the channels 904 * share an interrupt. Duart0 is interrupt 0, duart1 is 905 * interrupt 1. 906 */ 907 if (duartno != 0 && duartno != 1) 908 panic("scn_attach: bad duartno: %d", duartno); 909 cpu_intr_establish(duartno, IPL_TTY, scnintr, duart); 910 911 printf("%c %s", delim, duart_type); 912 delim = ','; 913 914 duart->base = duart_base; 915 duart->type = scntype; 916 } 917 /* Record channel, uart */ 918 sc->sc_channel = channel; 919 sc->sc_chbase = ch_base; 920 921 /* Initialize modem/interrupt bit masks */ 922 if (channel == 0) { 923 sc->sc_op_rts = OP_RTSA; 924 sc->sc_op_dtr = OP_DTRA; 925 sc->sc_ip_cts = IP_CTSA; 926 sc->sc_ip_dcd = IP_DCDA; 927 928 sc->sc_tx_int = INT_TXA; 929 sc->sc_rx_int = INT_RXA; 930 } else { 931 sc->sc_op_rts = OP_RTSB; 932 sc->sc_op_dtr = OP_DTRB; 933 sc->sc_ip_cts = IP_CTSB; 934 sc->sc_ip_dcd = IP_DCDB; 935 936 sc->sc_tx_int = INT_TXB; 937 sc->sc_rx_int = INT_RXB; 938 } 939 940 /* Initialize counters */ 941 sc->sc_framing_errors = 0; 942 sc->sc_fifo_overruns = 0; 943 sc->sc_parity_errors = 0; 944 sc->sc_breaks = 0; 945 946 if (console) { 947 DELAY(5 * 10000); /* Let the output go out.... */ 948 } 949 950 /* 951 * Set up the hardware to a base state, in particular: 952 * o reset transmitter and receiver 953 * o set speeds and configurations 954 * o receiver interrupts only (RxRDY and BREAK) 955 */ 956 957 s = spltty(); 958 /* RTS off... */ 959 SCN_OP_BIC(sc, sc->sc_op_rts); /* "istop" */ 960 961 ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX; 962 RECOVER(); 963 ch_base[CH_CR] = CR_CMD_RESET_RX; 964 RECOVER(); 965 ch_base[CH_CR] = CR_CMD_RESET_TX; 966 RECOVER(); 967 ch_base[CH_CR] = CR_CMD_RESET_ERR; 968 RECOVER(); 969 ch_base[CH_CR] = CR_CMD_RESET_BRK; 970 RECOVER(); 971 ch_base[CH_CR] = CR_CMD_MR1; 972 RECOVER(); 973 974 /* No receiver control of RTS. */ 975 ch_base[CH_MR] = 0; 976 ch_base[CH_MR] = 0; 977 978 /* Initialize the uart structure if this is channel A. */ 979 if (first) { 980 /* Disable all interrupts. */ 981 duart_base[DU_IMR] = duart->imr = 0; 982 983 /* Output port config */ 984 duart_base[DU_OPCR] = duart->opcr = 0; 985 986 /* Speeds... */ 987 duart->mode = 0; 988 989 /* 990 * Set initial speed to an illegal code that can be changed to 991 * any other baud. 992 */ 993 duart->chan[0].icode = duart->chan[0].ocode = 0x2f; 994 duart->chan[1].icode = duart->chan[1].ocode = 0x2f; 995 duart->chan[0].ispeed = duart->chan[0].ospeed = 0; 996 duart->chan[1].ispeed = duart->chan[1].ospeed = 0; 997 998 duart->acr = 0; 999 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */ 1000 } 1001 1002 if (channel == 0) { 1003 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */ 1004 } else { 1005 duart->acr |= ACR_DELTA_DCDB; /* Set CD int */ 1006 } 1007 1008 if (scnsir == NULL) { 1009 /* software intr: calls tty code, hence IPL_TTY */ 1010 scnsir = softint_establish(SOFTINT_SERIAL, scnsoft, NULL); 1011 } 1012 1013 duart_base[DU_ACR] = (duart->mode & ACR_BRG) | duart->acr; 1014 1015 if (console) 1016 speed = scnconsrate; 1017 else 1018 speed = scndefaultrate; 1019 1020 scn_config(unit, channel, speed, speed, MR1_PNONE | MR1_CS8, MR2_STOP1); 1021 if (console) { 1022 maj = cdevsw_lookup_major(&scn_cdevsw); 1023 KASSERT(maj != NODEVMAJOR); 1024 shutdownhook_establish(scncnreinit, NULL); 1025 /* Make sure console can do scncngetc */ 1026 duart_base[DU_OPSET] = channel ? (OP_RTSB | OP_DTRB) : 1027 (OP_RTSA | OP_DTRA); 1028 } 1029 1030 /* Turn on the receiver and transmitters */ 1031 ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX; 1032 1033 /* Set up the interrupts. */ 1034 duart->imr |= INT_IP; 1035 scn_rxdisable(sc); 1036 splx(s); 1037 1038 if (sc->sc_swflags) { 1039 printf("%c flags %d", delim, sc->sc_swflags); 1040 delim = ','; 1041 } 1042 1043 #ifdef KGDB 1044 major = cdevsw_lookup_major(&scn_cdevsw); 1045 KASSERT(major != NODEVMAJOR); 1046 if (kgdb_dev == makedev(major, unit)) { 1047 if (console) 1048 kgdb_dev = NODEV; /* can't debug over console port */ 1049 else { 1050 scninit(kgdb_dev, kgdb_rate); 1051 scn_rxenable(sc); 1052 scn->sc_iskgdb = 1; 1053 kgdb_attach(scncngetc, scncnputc, kgdb_dev); 1054 if (kgdb_debug_init) { 1055 printf("%c ", delim); 1056 kgdb_connect(1); 1057 } else 1058 printf("%c kgdb enabled", delim); 1059 delim = ','; 1060 } 1061 } 1062 #endif 1063 printf("\n"); 1064 } 1065 1066 /* ARGSUSED */ 1067 int 1068 scnopen(dev_t dev, int flags, int mode, struct lwp *l) 1069 { 1070 struct tty *tp; 1071 int unit = DEV_UNIT(dev); 1072 struct scn_softc *sc; 1073 int error = 0; 1074 int hwset = 0; 1075 1076 if (unit >= scn_cd.cd_ndevs) 1077 return ENXIO; 1078 sc = SOFTC(unit); 1079 if (!sc) 1080 return ENXIO; 1081 1082 tp = sc->sc_tty; 1083 if (!tp) { 1084 tp = ttymalloc(); 1085 sc->sc_tty = sc->sc_duart->chan[sc->sc_channel].tty = tp; 1086 tty_attach(tp); 1087 } 1088 1089 tp->t_oproc = scnstart; 1090 tp->t_param = scnparam; 1091 tp->t_hwiflow = scnhwiflow; 1092 tp->t_dev = dev; 1093 1094 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1095 return (EBUSY); 1096 1097 mutex_spin_enter(&tty_lock); 1098 1099 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1100 ttychars(tp); 1101 tp->t_iflag = TTYDEF_IFLAG; 1102 tp->t_oflag = TTYDEF_OFLAG; 1103 tp->t_cflag = SCNDEF_CFLAG; 1104 1105 sc->sc_rx_blocked = 0; 1106 1107 if (sc->sc_swflags & SCN_SW_CLOCAL) 1108 tp->t_cflag |= CLOCAL; 1109 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1110 tp->t_cflag |= CCTS_OFLOW | CRTS_IFLOW; 1111 tp->t_lflag = TTYDEF_LFLAG; 1112 if (sc->sc_isconsole) 1113 tp->t_ispeed = tp->t_ospeed = scnconsrate; 1114 else 1115 tp->t_ispeed = tp->t_ospeed = scndefaultrate; 1116 scnparam(tp, &tp->t_termios); 1117 ttsetwater(tp); 1118 1119 /* Turn on DTR and RTS. */ 1120 SCN_OP_BIS(sc, sc->sc_op_rts | sc->sc_op_dtr); 1121 1122 /* enable receiver interrupts */ 1123 scn_rxenable(sc); 1124 hwset = 1; 1125 1126 /* set carrier state; */ 1127 if ((sc->sc_swflags & SCN_SW_SOFTCAR) || /* check ttyflags */ 1128 SCN_DCD(sc) || /* check h/w */ 1129 DEV_DIALOUT(dev)) 1130 tp->t_state |= TS_CARR_ON; 1131 else 1132 tp->t_state &= ~TS_CARR_ON; 1133 } 1134 1135 mutex_spin_exit(&tty_lock); 1136 1137 error = ttyopen(tp, SCN_DIALOUT(sc), flags & O_NONBLOCK); 1138 if (error) printf("ttyopen failed line %d, error %d\n", __LINE__, error); 1139 if (error) 1140 goto bad; 1141 1142 error = (*tp->t_linesw->l_open) (dev, tp); 1143 if (error) printf("l_open failed line %d, error %d\n", __LINE__, error); 1144 if (error) 1145 goto bad; 1146 1147 return (0); 1148 1149 bad: 1150 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1151 scn_rxdisable(sc); 1152 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1153 } 1154 1155 return (error); 1156 } 1157 1158 1159 /*ARGSUSED*/ 1160 int 1161 scnclose(dev_t dev, int flags, int mode, struct lwp *l) 1162 { 1163 int unit = DEV_UNIT(dev); 1164 struct scn_softc *sc = SOFTC(unit); 1165 struct tty *tp = sc->sc_tty; 1166 devmajor_t major; 1167 1168 (void)major; 1169 1170 if ((tp->t_state & TS_ISOPEN) == 0) 1171 return 0; 1172 1173 (*tp->t_linesw->l_close) (tp, flags); 1174 1175 #ifdef KGDB 1176 /* do not disable interrupts if debugging */ 1177 major = cdevsw_lookup_major(&scn_devsw); 1178 KASSERT(major != cdevsw_lookup_major); 1179 if (kgdb_dev != makedev(major, unit)) 1180 #endif 1181 if ((tp->t_state & TS_ISOPEN) == 0) { 1182 scn_rxdisable(sc); 1183 } 1184 if ((tp->t_cflag & HUPCL) && (sc->sc_swflags & SCN_SW_SOFTCAR) == 0) { 1185 SCN_OP_BIC(sc, sc->sc_op_dtr); 1186 /* hold low for 1 second */ 1187 tsleep(sc, TTIPRI, ttclos, hz); 1188 } 1189 SCN_CLRDIALOUT(sc); 1190 ttyclose(tp); 1191 1192 #if 0 1193 if ((tp->t_state & TS_ISOPEN) == 0) { 1194 ttyfree(tp); 1195 sc->sc_tty = (struct tty *) NULL; 1196 } 1197 #endif 1198 1199 return (0); 1200 } 1201 1202 int 1203 scnread(dev_t dev, struct uio *uio, int flags) 1204 { 1205 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1206 struct tty *tp = sc->sc_tty; 1207 1208 return ((*tp->t_linesw->l_read) (tp, uio, flags)); 1209 } 1210 1211 int 1212 scnwrite(dev_t dev, struct uio *uio, int flags) 1213 { 1214 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1215 struct tty *tp = sc->sc_tty; 1216 1217 return ((*tp->t_linesw->l_write) (tp, uio, flags)); 1218 } 1219 1220 int 1221 scnpoll(dev_t dev, int events, struct lwp *l) 1222 { 1223 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1224 struct tty *tp = sc->sc_tty; 1225 1226 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1227 } 1228 1229 struct tty * 1230 scntty(dev_t dev) 1231 { 1232 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1233 1234 return sc->sc_tty; 1235 } 1236 1237 /* Worker routines for interrupt processing */ 1238 static inline void 1239 dcd_int(struct scn_softc *sc, struct tty *tp, u_char new) 1240 { 1241 1242 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1243 return; 1244 1245 #if 0 1246 printf("scn%d: dcd_int ip %x SCN_DCD %x new %x ipcr %x\n", 1247 sc->unit, 1248 sc->sc_duart->base[DU_IP], 1249 SCN_DCD(sc), 1250 new, 1251 sc->sc_duart->base[DU_IPCR] 1252 ); 1253 #endif 1254 1255 /* XXX set some flag to have some lower (soft) int call line discipline? */ 1256 if (!(*tp->t_linesw->l_modem) (tp, new == 0? 1: 0)) { 1257 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1258 } 1259 } 1260 1261 /* 1262 * Print out a ring or fifo overrun error message. 1263 */ 1264 static void 1265 scnoverrun(int unit, long *ptime, const char *what) 1266 { 1267 1268 if (*ptime != time_second) { 1269 *ptime = time_second; 1270 log(LOG_WARNING, "scn%d: %s overrun\n", unit, what); 1271 } 1272 } 1273 1274 /* 1275 * Try to block or unblock input using hardware flow-control. 1276 * This is called by kern/tty.c if MDMBUF|CRTSCTS is set, and 1277 * if this function returns non-zero, the TS_TBLOCK flag will 1278 * be set or cleared according to the "stop" arg passed. 1279 */ 1280 int 1281 scnhwiflow(struct tty *tp, int stop) 1282 { 1283 int unit = DEV_UNIT(tp->t_dev); 1284 struct scn_softc *sc = SOFTC(unit); 1285 int s; 1286 1287 s = splrtty(); 1288 if (!stop) { 1289 if (sc->sc_rbput - sc->sc_rbget - 1) { 1290 setsoftscn(); 1291 } 1292 } 1293 splx(s); 1294 return 1; 1295 } 1296 1297 static int 1298 scnintr(void *arg) 1299 { 1300 struct duart *duart = arg; 1301 struct scn_softc *sc0 = duart->chan[0].sc; 1302 struct scn_softc *sc1 = duart->chan[1].sc; 1303 1304 struct tty *tp0 = (sc0 != NULL) ? sc0->sc_tty : NULL; 1305 struct tty *tp1 = (sc1 != NULL) ? sc1->sc_tty : NULL; 1306 1307 char rs_work; 1308 u_char rs_stat; 1309 u_char rs_ipcr; 1310 1311 /* Check for RX interrupts first, since we cannot distinguish by irq. */ 1312 scnrxintr(duart); 1313 1314 do { 1315 /* Loop to pick up ALL pending interrupts for device. */ 1316 rs_work = false; 1317 rs_stat = duart->base[DU_ISR]; 1318 1319 /* channel a */ 1320 if (tp0 != NULL) { 1321 if ((rs_stat & INT_TXA) && (tp0->t_state & TS_BUSY)) { 1322 /* output char done. */ 1323 tp0->t_state &= ~(TS_BUSY | TS_FLUSH); 1324 1325 /* disable tx ints */ 1326 duart->imr &= ~sc0->sc_tx_int; 1327 duart->base[DU_IMR] = duart->imr; 1328 1329 if (sc0->sc_heldchanges) { 1330 scn_setchip(sc0); 1331 } 1332 1333 (*tp0->t_linesw->l_start) (tp0); 1334 rs_work = true; 1335 } 1336 } 1337 /* channel b */ 1338 if (tp1 != NULL) { 1339 if ((rs_stat & INT_TXB) && (tp1->t_state & TS_BUSY)) { 1340 /* output char done. */ 1341 tp1->t_state &= ~(TS_BUSY | TS_FLUSH); 1342 1343 /* disable tx ints */ 1344 duart->imr &= ~sc1->sc_tx_int; 1345 duart->base[DU_IMR] = duart->imr; 1346 1347 if (sc1->sc_heldchanges) { 1348 scn_setchip(sc1); 1349 } 1350 1351 (*tp1->t_linesw->l_start) (tp1); 1352 rs_work = true; 1353 } 1354 } 1355 if (rs_stat & INT_IP) { 1356 rs_work = true; 1357 rs_ipcr = duart->base[DU_IPCR]; 1358 1359 if (rs_ipcr & IPCR_DELTA_DCDA && tp0 != NULL) { 1360 dcd_int(sc0, tp0, rs_ipcr & IPCR_DCDA); 1361 } 1362 if (rs_ipcr & IPCR_DELTA_DCDB && tp1 != NULL) { 1363 dcd_int(sc1, tp1, rs_ipcr & IPCR_DCDB); 1364 } 1365 } 1366 } while (rs_work); 1367 1368 return (1); /* ? */ 1369 } 1370 1371 /* 1372 * Handle rxrdy/ffull interrupt: QUICKLY poll both channels (checking 1373 * status first) and stash data in a ring buffer. Ring buffer scheme 1374 * borowed from sparc/zs.c requires NO interlock on data! 1375 * 1376 * This interrupt should NOT be included in spltty() mask since it 1377 * invokes NO tty code! The whole point is to allow tty input as much 1378 * of the time as possible, while deferring "heavy" character 1379 * processing until later. 1380 * 1381 * see scn.hw.README and scnsoft() for more info. 1382 * 1383 * THIS ROUTINE SHOULD BE KEPT AS CLEAN AS POSSIBLE!! 1384 * IT'S A CANDIDATE FOR RECODING IN ASSEMBLER!! 1385 */ 1386 static inline int 1387 scn_rxintr(struct scn_softc *sc) 1388 { 1389 char sr; 1390 int i, n; 1391 int work; 1392 1393 work = 0; 1394 i = sc->sc_rbput; 1395 while (work <= 10) { 1396 #define SCN_GETCH(SC) \ 1397 sr = (SC)->sc_chbase[CH_SR]; \ 1398 if ((sr & SR_RX_RDY) == 0) \ 1399 break; \ 1400 if (sr & (SR_PARITY | SR_FRAME | SR_BREAK | SR_OVERRUN)) \ 1401 goto exception; \ 1402 work++; \ 1403 (SC)->sc_rbuf[i++ & SCN_RING_MASK] = (SC)->sc_chbase[CH_DAT] 1404 1405 SCN_GETCH(sc); SCN_GETCH(sc); SCN_GETCH(sc); 1406 /* XXX more here if 26C92? -plb */ 1407 continue; 1408 exception: 1409 #if defined(DDB) 1410 if (sc->sc_isconsole && (sr & SR_BREAK)) { 1411 Debugger(); 1412 sr = sc->sc_chbase[CH_SR]; 1413 } 1414 #endif 1415 #if defined(KGDB) 1416 if (sc->sc_iskgdb && (sr & SR_RX_RDY)) { 1417 kgdb_connect(1); 1418 sr = sc->sc_chbase[CH_SR]; 1419 } 1420 #endif 1421 work++; 1422 sc->sc_rbuf[i++ & SCN_RING_MASK] = (sr << 8) | sc->sc_chbase[CH_DAT]; 1423 sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */ 1424 RECOVER(); 1425 } 1426 /* 1427 * If ring is getting too full, try to block input. 1428 */ 1429 n = i - sc->sc_rbget; 1430 if (sc->sc_rbhiwat && (n > sc->sc_rbhiwat)) { 1431 /* If not CRTSCTS sc_rbhiwat is such that this 1432 * never happens. 1433 * Clear RTS 1434 */ 1435 SCN_OP_BIC(sc, sc->sc_op_rts); 1436 sc->sc_rx_blocked = 1; 1437 } 1438 sc->sc_rbput = i; 1439 1440 return work; 1441 } 1442 1443 static void 1444 scnrxintr(void *arg) 1445 { 1446 struct duart *duart = arg; 1447 int work = 0; 1448 1449 if (duart->chan[0].sc != NULL) 1450 work += scn_rxintr(duart->chan[0].sc); 1451 if (duart->chan[1].sc != NULL) 1452 work += scn_rxintr(duart->chan[1].sc); 1453 if (work > 0) { 1454 setsoftscn(); /* trigger s/w intr */ 1455 #ifdef SCN_TIMING 1456 microtime(&tstart); 1457 #endif 1458 } 1459 } 1460 1461 /* 1462 * Here on soft interrupt (at spltty) to empty ring buffers. 1463 * 1464 * Dave's original scheme was to use the DUART receiver timeout 1465 * interrupt. This requires 2692's (which my board doesn't have), and 1466 * I also liked the idea of using the C/T to generate alternate and/or 1467 * arbitrary bauds. -plb 1468 * 1469 * The ringbuffer code comes from Chris Torek's SPARC 44bsd zs driver 1470 * (hence the LBL notice on top of this file), DOES NOT require 1471 * interlocking with interrupt levels! 1472 * 1473 * The 44bsd sparc/zs driver reads the ring buffer from a separate 1474 * zssoftint, while the SunOS 4.x zs driver appears to use 1475 * timeout()'s. timeouts seem to be too slow to deal with high data 1476 * rates. I know, I tried them. 1477 * -plb. 1478 */ 1479 static void 1480 scnsoft(void *arg) 1481 { 1482 int s, unit; 1483 #ifdef SCN_TIMING 1484 struct timeval tend; 1485 u_long t; 1486 1487 microtime(&tend); 1488 t = (tend.tv_sec - tstart.tv_sec) * 1000000 + (tend.tv_usec - tstart.tv_usec); 1489 t = (t + tick / 20) / (tick / 10); 1490 if (t >= NJITTER - 1) { 1491 t = NJITTER - 1; 1492 } 1493 scn_jitter[t]++; 1494 #endif 1495 1496 for (unit = 0; unit < scn_cd.cd_ndevs; unit++) { 1497 struct scn_softc *sc; 1498 struct tty *tp; 1499 int n, get; 1500 1501 sc = SOFTC(unit); 1502 if (sc == NULL) { 1503 continue; 1504 } 1505 tp = sc->sc_tty; 1506 #ifdef KGDB 1507 if (tp == NULL) { 1508 sc->sc_rbget = sc->sc_rbput; 1509 continue; 1510 } 1511 #endif 1512 if (tp == NULL || tp->t_state & TS_TBLOCK) { 1513 continue; 1514 } 1515 1516 1517 get = sc->sc_rbget; 1518 1519 /* NOTE: fetch from rbput is atomic */ 1520 while (get != (n = sc->sc_rbput)) { 1521 /* 1522 * Compute the number of interrupts in the receive ring. 1523 * If the count is overlarge, we lost some events, and 1524 * must advance to the first valid one. It may get 1525 * overwritten if more data are arriving, but this is 1526 * too expensive to check and gains nothing (we already 1527 * lost out; all we can do at this point is trade one 1528 * kind of loss for another). 1529 */ 1530 n -= get; 1531 if (n > SCN_RING_SIZE) { 1532 scnoverrun(unit, &sc->sc_rotime, "ring"); 1533 get += n - SCN_RING_SIZE; 1534 n = SCN_RING_SIZE; 1535 sc->sc_ring_overruns++; 1536 } 1537 while (--n >= 0) { 1538 int c, sr; 1539 1540 if (tp->t_state & TS_TBLOCK) { 1541 sc->sc_rbget = get; 1542 goto done; 1543 } 1544 /* Race to keep ahead of incoming interrupts. */ 1545 c = sc->sc_rbuf[get++ & SCN_RING_MASK]; 1546 1547 sr = c >> 8; /* extract status */ 1548 c &= 0xff; /* leave just character */ 1549 1550 if (sr & SR_OVERRUN) { 1551 scnoverrun(unit, &sc->sc_fotime, "fifo"); 1552 sc->sc_fifo_overruns++; 1553 } 1554 if (sr & SR_PARITY) { 1555 c |= TTY_PE; 1556 sc->sc_parity_errors++; 1557 } 1558 if (sr & SR_FRAME) { 1559 c |= TTY_FE; 1560 sc->sc_framing_errors++; 1561 } 1562 if (sr & SR_BREAK) { 1563 #if 0 1564 /* 1565 * See DDB_CHECK() comments in 1566 * scnrxintr() 1567 */ 1568 if (sc->sc_isconsole) 1569 Debugger(); 1570 #endif 1571 c = TTY_FE | 0; 1572 sc->sc_breaks++; 1573 } 1574 1575 (*tp->t_linesw->l_rint) (c, tp); 1576 1577 if (sc->sc_rx_blocked && n < SCN_RING_THRESH) { 1578 s = splrtty(); 1579 sc->sc_rx_blocked = 0; 1580 SCN_OP_BIS(sc, sc->sc_op_rts); 1581 splx(s); 1582 } 1583 1584 } 1585 sc->sc_rbget = get; 1586 } 1587 done: ; 1588 } 1589 } 1590 1591 /* Convert TIOCM_xxx bits to output port bits. */ 1592 static unsigned char 1593 opbits(struct scn_softc *sc, int tioc_bits) 1594 { 1595 1596 return ((((tioc_bits) & TIOCM_DTR) ? sc->sc_op_dtr : 0) | 1597 (((tioc_bits) & TIOCM_RTS) ? sc->sc_op_rts : 0)); 1598 } 1599 1600 int 1601 scnioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1602 { 1603 int unit = DEV_UNIT(dev); 1604 struct scn_softc *sc = SOFTC(unit); 1605 struct tty *tp = sc->sc_tty; 1606 int error; 1607 1608 error = (*tp->t_linesw->l_ioctl) (tp, cmd, data, flags, l); 1609 if (error != EPASSTHROUGH) 1610 return (error); 1611 1612 error = ttioctl(tp, cmd, data, flags, l); 1613 if (error != EPASSTHROUGH) 1614 return (error); 1615 1616 switch (cmd) { 1617 case TIOCSBRK: 1618 sc->sc_chbase[CH_CR] = CR_CMD_START_BRK; 1619 break; 1620 1621 case TIOCCBRK: 1622 sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK; 1623 break; 1624 1625 case TIOCSDTR: 1626 SCN_OP_BIS(sc, sc->sc_op_dtr | sc->sc_op_rts); 1627 break; 1628 1629 case TIOCCDTR: 1630 SCN_OP_BIC(sc, sc->sc_op_dtr | sc->sc_op_rts); 1631 break; 1632 1633 case TIOCMSET: { 1634 int s; 1635 unsigned char sbits, cbits; 1636 1637 /* set bits */ 1638 sbits = opbits(sc, *(int *) data); 1639 1640 /* get bits to clear */ 1641 cbits = ~sbits & (sc->sc_op_dtr | sc->sc_op_rts); 1642 1643 s = spltty(); 1644 if (sbits) { 1645 SCN_OP_BIS(sc, sbits); 1646 } 1647 if (cbits) { 1648 SCN_OP_BIC(sc, cbits); 1649 } 1650 splx(s); 1651 break; 1652 } 1653 1654 case TIOCMBIS: 1655 SCN_OP_BIS(sc, opbits(sc, *(int *) data)); 1656 break; 1657 1658 case TIOCMBIC: 1659 SCN_OP_BIC(sc, opbits(sc, *(int *) data)); 1660 break; 1661 1662 case TIOCMGET: { 1663 int bits; 1664 unsigned char ip, op; 1665 1666 /* s = spltty(); */ 1667 ip = sc->sc_duart->base[DU_IP]; 1668 /* 1669 * XXX sigh; cannot get op current state!! even if 1670 * maintained in private, RTS is done in h/w!! 1671 */ 1672 op = 0; 1673 /* splx(s); */ 1674 1675 bits = 0; 1676 if (ip & sc->sc_ip_dcd) 1677 bits |= TIOCM_CD; 1678 if (ip & sc->sc_ip_cts) 1679 bits |= TIOCM_CTS; 1680 1681 #if 0 1682 if (op & sc->sc_op_dtr) 1683 bits |= TIOCM_DTR; 1684 if (op & sc->sc_op_rts) 1685 bits |= TIOCM_RTS; 1686 #endif 1687 1688 *(int *) data = bits; 1689 break; 1690 } 1691 1692 case TIOCGFLAGS:{ 1693 int bits = 0; 1694 1695 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1696 bits |= TIOCFLAG_SOFTCAR; 1697 if (sc->sc_swflags & SCN_SW_CLOCAL) 1698 bits |= TIOCFLAG_CLOCAL; 1699 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1700 bits |= TIOCFLAG_CRTSCTS; 1701 if (sc->sc_swflags & SCN_SW_MDMBUF) 1702 bits |= TIOCFLAG_MDMBUF; 1703 1704 *(int *) data = bits; 1705 break; 1706 } 1707 case TIOCSFLAGS:{ 1708 int userbits, driverbits = 0; 1709 1710 error = kauth_authorize_device_tty(l->l_cred, 1711 KAUTH_DEVICE_TTY_PRIVSET, tp); 1712 if (error != 0) 1713 return (EPERM); 1714 1715 userbits = *(int *) data; 1716 if (userbits & TIOCFLAG_SOFTCAR) 1717 driverbits |= SCN_SW_SOFTCAR; 1718 if (userbits & TIOCFLAG_CLOCAL) 1719 driverbits |= SCN_SW_CLOCAL; 1720 if (userbits & TIOCFLAG_CRTSCTS) 1721 driverbits |= SCN_SW_CRTSCTS; 1722 if (userbits & TIOCFLAG_MDMBUF) 1723 driverbits |= SCN_SW_MDMBUF; 1724 1725 sc->sc_swflags = driverbits; 1726 1727 break; 1728 } 1729 1730 default: 1731 return (EPASSTHROUGH); 1732 } 1733 return (0); 1734 } 1735 1736 int 1737 scnparam(struct tty *tp, struct termios *t) 1738 { 1739 int cflag = t->c_cflag; 1740 int unit = DEV_UNIT(tp->t_dev); 1741 char mr1, mr2; 1742 int error; 1743 struct scn_softc *sc = SOFTC(unit); 1744 1745 /* Is this a hang up? */ 1746 if (t->c_ospeed == B0) { 1747 SCN_OP_BIC(sc, sc->sc_op_dtr); 1748 /* leave DTR down. see comment in scnclose() -plb */ 1749 return (0); 1750 } 1751 mr1 = mr2 = 0; 1752 1753 /* Parity? */ 1754 if (cflag & PARENB) { 1755 if ((cflag & PARODD) == 0) 1756 mr1 |= MR1_PEVEN; 1757 else 1758 mr1 |= MR1_PODD; 1759 } else 1760 mr1 |= MR1_PNONE; 1761 1762 /* Stop bits. */ 1763 if (cflag & CSTOPB) 1764 mr2 |= MR2_STOP2; 1765 else 1766 mr2 |= MR2_STOP1; 1767 1768 /* Data bits. */ 1769 switch (cflag & CSIZE) { 1770 case CS5: 1771 mr1 |= MR1_CS5; 1772 break; 1773 case CS6: 1774 mr1 |= MR1_CS6; 1775 break; 1776 case CS7: 1777 mr1 |= MR1_CS7; 1778 break; 1779 case CS8: 1780 default: 1781 mr1 |= MR1_CS8; 1782 break; 1783 } 1784 1785 if (cflag & CCTS_OFLOW) 1786 mr2 |= MR2_TXCTS; 1787 1788 if (cflag & CRTS_IFLOW) { 1789 mr1 |= MR1_RXRTS; 1790 sc->sc_rbhiwat = SCN_RING_HIWAT; 1791 } else { 1792 sc->sc_rbhiwat = 0; 1793 } 1794 1795 error = scn_config(unit, sc->sc_channel, t->c_ispeed, 1796 t->c_ospeed, mr1, mr2); 1797 1798 /* If successful, copy to tty */ 1799 if (!error) { 1800 tp->t_ispeed = t->c_ispeed; 1801 tp->t_ospeed = t->c_ospeed; 1802 tp->t_cflag = cflag; 1803 } 1804 return (error); 1805 } 1806 1807 /* 1808 * Start or restart a transmission. 1809 */ 1810 void 1811 scnstart(struct tty *tp) 1812 { 1813 int s, c; 1814 int unit = DEV_UNIT(tp->t_dev); 1815 struct scn_softc *sc = SOFTC(unit); 1816 1817 s = spltty(); 1818 if (tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1819 goto out; 1820 if (!ttypull(tp)) 1821 goto out; 1822 1823 tp->t_state |= TS_BUSY; 1824 1825 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) { 1826 if ((c = getc(&tp->t_outq)) == -1) 1827 break; 1828 sc->sc_chbase[CH_DAT] = c; 1829 } 1830 sc->sc_duart->imr |= (sc->sc_tx_int | sc->sc_rx_int); 1831 sc->sc_duart->base[DU_IMR] = sc->sc_duart->imr; 1832 1833 out: 1834 splx(s); 1835 } 1836 1837 /* 1838 * Stop output on a line. 1839 */ 1840 /*ARGSUSED*/ 1841 void 1842 scnstop(struct tty *tp, int flags) 1843 { 1844 int s; 1845 1846 s = spltty(); 1847 if (tp->t_state & TS_BUSY) { 1848 if ((tp->t_state & TS_TTSTOP) == 0) 1849 tp->t_state |= TS_FLUSH; 1850 } 1851 splx(s); 1852 } 1853 1854 /* 1855 * Following are all routines needed for SCN to act as console. 1856 */ 1857 1858 void 1859 scncnprobe(struct consdev *cn) 1860 { 1861 } 1862 1863 void 1864 scncnreinit(void *v) 1865 { 1866 volatile u_char *du_base = 1867 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1868 1869 du_base[DU_OPSET] = 1870 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1871 } 1872 1873 void 1874 scncninit(struct consdev *cn) 1875 { 1876 devmajor_t major; 1877 1878 /* initialize required fields */ 1879 major = cdevsw_lookup_major(&scn_cdevsw); 1880 KASSERT(major != NODEV); 1881 cn->cn_dev = makedev(major, SCN_CONSOLE); 1882 cn->cn_pri = CN_REMOTE; 1883 1884 scninit(cn->cn_dev, scnconsrate); 1885 } 1886 1887 /* Used by scncninit and kgdb startup. */ 1888 int 1889 scninit(dev_t dev, int rate) 1890 { 1891 /* XXX - maintain PROM's settings */ 1892 #if 0 1893 volatile u_char *du_base = 1894 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1895 int unit = DEV_UNIT(dev); 1896 1897 du_base[DU_OPSET] = 1898 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1899 scn_config(unit, SCN_CONSCHAN, rate, rate, 1900 MR1_PNONE | MR1_CS8, MR2_STOP1); 1901 #endif 1902 return (0); 1903 } 1904 1905 /* 1906 * Console kernel input character routine. 1907 */ 1908 int 1909 scncngetc(dev_t dev) 1910 { 1911 volatile u_char *ch_base = 1912 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1913 char c; 1914 int s; 1915 1916 s = spltty(); 1917 1918 while ((ch_base[CH_SR] & SR_RX_RDY) == 0) 1919 ; 1920 c = ch_base[CH_DAT]; 1921 1922 splx(s); 1923 return c; 1924 } 1925 1926 void 1927 scncnpollc(dev_t dev, int on) 1928 { 1929 } 1930 1931 /* 1932 * Console kernel output character routine. 1933 */ 1934 void 1935 scncnputc(dev_t dev, int c) 1936 { 1937 volatile u_char *ch_base = 1938 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1939 volatile u_char *du_base = 1940 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1941 int s; 1942 1943 s = spltty(); 1944 1945 if (c == '\n') 1946 scncnputc(dev, '\r'); 1947 1948 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1949 ; 1950 ch_base[CH_DAT] = c; 1951 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1952 ; 1953 du_base[DU_ISR]; 1954 1955 splx(s); 1956 } 1957