1 /* $NetBSD: scn.c,v 1.10 2022/10/26 23:59:14 riastradh Exp $ */ 2 3 /* 4 * Resurrected from the old pc532 port 1/18/2009. 5 * 6 * XXX- The locking in this is probably totally broken. I haven't attempted 7 * to get it right, but it seems to work okay anyhow. 8 */ 9 10 /* 11 * Copyright (c) 1991, 1992, 1993 12 * The Regents of the University of California. All rights reserved. 13 * 14 * Portions of this software were developed by the Computer Systems 15 * Engineering group at Lawrence Berkeley Laboratory under DARPA 16 * contract BG 91-66 and contributed to Berkeley. 17 * 18 * All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Lawrence Berkeley Laboratory. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 48 */ 49 50 /* 51 * Copyright (c) 1996, 1997 Philip L. Budne. 52 * Copyright (c) 1993 Philip A. Nelson. 53 * 54 * Portions of this software were developed by the Computer Systems 55 * Engineering group at Lawrence Berkeley Laboratory under DARPA 56 * contract BG 91-66 and contributed to Berkeley. 57 * 58 * All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Lawrence Berkeley Laboratory. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 3. All advertising materials mentioning features or use of this software 72 * must display the following acknowledgement: 73 * This product includes software developed by the University of 74 * California, Berkeley and its contributors. 75 * 4. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 #include <sys/cdefs.h> 95 __KERNEL_RCSID(0, "$NetBSD: scn.c,v 1.10 2022/10/26 23:59:14 riastradh Exp $"); 96 97 #include "opt_ddb.h" 98 #include "opt_kgdb.h" 99 #include "scn.h" 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/file.h> 108 #include <sys/uio.h> 109 #include <sys/kernel.h> 110 #include <sys/syslog.h> 111 #include <sys/types.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/conf.h> 115 #include <sys/intr.h> 116 #ifdef KGDB 117 #include <sys/kgdb.h> 118 #endif 119 #include <sys/kauth.h> 120 121 #include <dev/cons.h> 122 123 #include <machine/autoconf.h> 124 #include <machine/machtype.h> 125 126 #include <sgimips/dev/scnreg.h> 127 #include <sgimips/dev/scnvar.h> 128 129 int scn_match(device_t, struct cfdata *, void *); 130 void scn_attach(device_t, device_t, void *); 131 int scnparam(struct tty *, struct termios *); 132 void scnstart(struct tty *); 133 int scnhwiflow(struct tty *, int); 134 135 void scncnprobe(struct consdev *); 136 void scncninit(struct consdev *); 137 int scncngetc(dev_t); 138 void scncnputc(dev_t, int); 139 void scncnpollc(dev_t, int); 140 int scninit(dev_t, int); 141 void scncnreinit(void *); 142 143 CFATTACH_DECL_NEW(scn, sizeof(struct scn_softc), 144 scn_match, scn_attach, NULL, NULL); 145 146 extern struct cfdriver scn_cd; 147 148 dev_type_open(scnopen); 149 dev_type_close(scnclose); 150 dev_type_read(scnread); 151 dev_type_write(scnwrite); 152 dev_type_ioctl(scnioctl); 153 dev_type_stop(scnstop); 154 dev_type_tty(scntty); 155 dev_type_poll(scnpoll); 156 157 const struct cdevsw scn_cdevsw = { 158 .d_open = scnopen, 159 .d_close = scnclose, 160 .d_read = scnread, 161 .d_write = scnwrite, 162 .d_ioctl = scnioctl, 163 .d_stop = scnstop, 164 .d_tty = scntty, 165 .d_poll = scnpoll, 166 .d_mmap = nommap, 167 .d_kqfilter = ttykqfilter, 168 .d_discard = nodiscard, 169 .d_flag = D_TTY 170 }; 171 172 struct consdev scn_cn = { 173 scncnprobe, 174 scncninit, 175 scncngetc, 176 scncnputc, 177 scncnpollc, 178 NULL, 179 NULL, 180 NULL, 181 NODEV, 182 CN_NORMAL 183 }; 184 185 #ifndef CONSOLE_SPEED 186 #define CONSOLE_SPEED TTYDEF_SPEED 187 #endif 188 189 #ifndef SCNDEF_CFLAG 190 #define SCNDEF_CFLAG TTYDEF_CFLAG 191 #endif 192 193 #ifdef CPU30MHZ 194 #define RECOVER() __asm volatile("bispsrw 0x800" : : : "cc") 195 #else 196 #define RECOVER() 197 #endif 198 199 int scndefaultrate = TTYDEF_SPEED; 200 int scnconsrate = CONSOLE_SPEED; 201 202 static inline struct scn_softc * 203 SOFTC(int unit) 204 { 205 if (unit < 0 || unit >= scn_cd.cd_ndevs) 206 return (NULL); 207 return device_private(scn_cd.cd_devs[unit]); 208 } 209 210 static int scnintr(void *); 211 static void scnrxintr(void *); 212 static int scn_rxintr(struct scn_softc *); 213 static void scnsoft(void *); 214 static void scn_setchip(struct scn_softc *sc); 215 static int scniter(int *, int, int*, int*, struct chan *, int); 216 static int scn_config(int, int, int, int, u_char, u_char); 217 static void scn_rxenable(struct scn_softc *); 218 static void scn_rxdisable(struct scn_softc *); 219 static void dcd_int(struct scn_softc *, struct tty *, u_char); 220 static void scnoverrun(int, long *, const char *); 221 static u_char opbits(struct scn_softc *, int); 222 223 static void *scnsir = NULL; /* s/w intr cookie */ 224 #define setsoftscn() softint_schedule(scnsir) 225 226 #ifdef SCN_TIMING 227 /* 228 * Keep timing info on latency of software interrupt used by 229 * the ringbuf code to empty ring buffer. 230 * "getinfo" program reads data from /dev/kmem. 231 */ 232 static struct timeval tstart; 233 #define NJITTER 100 234 int scn_njitter = NJITTER; 235 int scn_jitter[NJITTER]; 236 #endif 237 238 #define SCN_CLOCK 3686400 /* input clock */ 239 240 /* speed table groups ACR[7] */ 241 #define GRP_A 0 242 #define GRP_B ACR_BRG 243 244 /* combo of MR0[2:0] and ACR[7] */ 245 #define MODE0A MR0_MODE_0 246 #define MODE0B (MR0_MODE_0|ACR_BRG) 247 #define MODE1A MR0_MODE_1 248 #define MODE1B (MR0_MODE_1|ACR_BRG) 249 #define MODE2A MR0_MODE_2 250 #define MODE2B (MR0_MODE_2|ACR_BRG) 251 252 #define ANYMODE -1 253 #define DEFMODE(C92) MODE0A /* use MODE4A if 26c92? */ 254 255 /* speed code for Counter/Timer (all modes, groups) */ 256 #define USE_CT 0xd 257 258 /* 259 * Rate table, ordered by speed, then mode. 260 * NOTE: ordering of modes must be done carefully! 261 */ 262 struct tabent { 263 int32_t speed; 264 int16_t code; 265 int16_t mode; 266 } table[] = { 267 { 50, 0x0, MODE0A }, 268 { 75, 0x0, MODE0B }, 269 { 110, 0x1, MODE0A }, 270 { 110, 0x1, MODE0B }, 271 { 110, 0x1, MODE1A }, 272 { 110, 0x1, MODE1B }, 273 { 134, 0x2, MODE0A }, /* 134.5 */ 274 { 134, 0x2, MODE0B }, /* 134.5 */ 275 { 134, 0x2, MODE1A }, /* 134.5 */ 276 { 134, 0x2, MODE1B }, /* 134.5 */ 277 { 150, 0x3, MODE0A }, 278 { 150, 0x3, MODE0A }, 279 { 200, 0x3, MODE0A }, 280 { 300, 0x4, MODE0A }, 281 { 300, 0x4, MODE0B }, 282 { 300, 0x0, MODE1A }, 283 { 450, 0x0, MODE1B }, 284 { 600, 0x5, MODE0A }, 285 { 600, 0x5, MODE0B }, 286 { 880, 0x1, MODE2A }, 287 { 880, 0x1, MODE2B }, 288 { 900, 0x3, MODE1B }, 289 { 1050, 0x7, MODE0A }, 290 { 1050, 0x7, MODE1A }, 291 { 1076, 0x2, MODE2A }, 292 { 1076, 0x2, MODE2B }, 293 { 1200, 0x6, MODE0A }, 294 { 1200, 0x6, MODE0B }, 295 { 1200, 0x3, MODE1A }, 296 { 1800, 0xa, MODE0B }, 297 { 1800, 0x4, MODE1A }, 298 { 1800, 0x4, MODE1B }, 299 { 2000, 0x7, MODE0B }, 300 { 2000, 0x7, MODE1B }, 301 { 2400, 0x8, MODE0A }, 302 { 2400, 0x8, MODE0B }, 303 { 3600, 0x5, MODE1A }, 304 { 3600, 0x5, MODE1B }, 305 { 4800, 0x9, MODE2A }, 306 { 4800, 0x9, MODE2B }, 307 { 4800, 0x9, MODE0A }, 308 { 4800, 0x9, MODE0B }, 309 { 7200, 0xa, MODE0A }, 310 { 7200, 0x0, MODE2B }, 311 { 7200, 0x6, MODE1A }, 312 { 7200, 0x6, MODE1B }, 313 { 9600, 0xb, MODE2A }, 314 { 9600, 0xb, MODE2B }, 315 { 9600, 0xb, MODE0A }, 316 { 9600, 0xb, MODE0B }, 317 { 9600, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 318 { 9600, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 319 { 14400, 0x3, MODE2B }, 320 { 14400, 0x8, MODE1A }, 321 { 14400, 0x8, MODE1B }, 322 { 19200, 0x3, MODE2A }, 323 { 19200, 0xc, MODE2B }, 324 { 19200, 0xc, MODE0B }, 325 { 19200, 0xd, MODE1A }, /* use C/T as entre' to mode1 */ 326 { 19200, 0xd, MODE1B }, /* use C/T as entre' to mode1 */ 327 { 28800, 0x4, MODE2A }, 328 { 28800, 0x4, MODE2B }, 329 { 28800, 0x9, MODE1A }, 330 { 28800, 0x9, MODE1B }, 331 { 38400, 0xc, MODE2A }, 332 { 38400, 0xc, MODE0A }, 333 { 57600, 0x5, MODE2A }, 334 { 57600, 0x5, MODE2B }, 335 { 57600, 0xb, MODE1A }, 336 { 57600, 0xb, MODE1B }, 337 { 115200, 0x6, MODE2A }, 338 { 115200, 0x6, MODE2B }, 339 { 115200, 0xc, MODE1B }, 340 { 230400, 0xc, MODE1A } 341 }; 342 #define TABENTRIES (sizeof(table)/sizeof(table[0])) 343 344 /* 345 * boolean for speed codes which are identical in both A/B BRG groups 346 * in all modes 347 */ 348 static u_char bothgroups[16] = { 349 0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1 350 }; 351 352 /* 353 * Manually constructed divisors table 354 * for minimum error (from some of Dave Rand's code) 355 */ 356 const struct { 357 uint16_t speed; 358 uint16_t div; 359 } divs[] = { 360 { 50, 2303 }, /* 2304 is exact?? */ 361 { 110, 1047 }, /* Should be 1047.27 */ 362 { 134, 857 }, /* Should be 856.505576 */ 363 { 1050, 110 }, /* Should be 109.7142857 */ 364 { 2000, 57 } /* Should be 57.6 */ 365 }; 366 #define DIVS (sizeof(divs)/sizeof(divs[0])) 367 368 /* 369 * minor unit bit decode: 370 * CxxxUUU 371 * 372 * C - carrier 373 * 0 - delay open until carrier high 374 * 1 - allow open with carrier low 375 * UUU - unit 0-7 376 */ 377 378 #define DEV_UNIT(x) (minor(x) & 0x7) 379 #define DEV_DIALOUT(x) (minor(x) & 0x80) 380 381 #define SCN_MAXDUART 4 382 static struct duart scn_duart[SCN_MAXDUART]; 383 384 #ifdef KGDB 385 extern int kgdb_dev; 386 extern int kgdb_rate; 387 extern int kgdb_debug_init; 388 #endif 389 390 /* XXXXX - fix this */ 391 #define splrtty() spltty() 392 393 /* RS-232 configuration routines */ 394 395 /* 396 * set chip parameters, or mark for delayed change. 397 * called at spltty() or on TxEMPTY interrupt. 398 * 399 * Reads current values to avoid glitches from redundant sets. 400 * Perhaps should save last value set to avoid read/write? NOTE: 401 * Would still need to do read if write not needed to advance MR 402 * pointer. 403 * 404 * new 2/97 -plb 405 */ 406 407 static void 408 scn_setchip(struct scn_softc *sc) 409 { 410 struct duart *dp; 411 u_char acr, csr, mr1, mr2; 412 int chan; 413 414 if (sc->sc_tty && (sc->sc_tty->t_state & TS_BUSY)) { 415 sc->sc_heldchanges = 1; 416 return; 417 } 418 419 chan = sc->sc_channel; 420 dp = sc->sc_duart; 421 if (dp->type == SC26C92) { 422 u_char nmr0a, mr0a; 423 424 /* input rate high enough so 64 bit time watchdog not 425 * onerous? */ 426 if (dp->chan[chan].ispeed >= 1200) { 427 /* set FIFO threshold at 6 for other 428 * thresholds we could have to set MR1_FFULL 429 */ 430 dp->chan[chan].mr0 |= MR0_RXWD | MR0_RXINT; 431 } else { 432 dp->chan[chan].mr0 &= ~(MR0_RXWD | MR0_RXINT); 433 } 434 435 /* select BRG mode (MR0A only) */ 436 nmr0a = dp->chan[0].mr0 | (dp->mode & MR0_MODE); 437 438 dp->base[CH_CR] = CR_CMD_MR0; 439 RECOVER(); 440 441 mr0a = dp->base[CH_MR]; 442 if (mr0a != nmr0a) { 443 dp->base[CH_CR] = CR_CMD_MR0; 444 RECOVER(); 445 dp->base[CH_MR] = nmr0a; 446 } 447 448 if (chan) { /* channel B? */ 449 u_char mr0b; 450 451 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 452 RECOVER(); 453 mr0b = dp->base[CH_MR]; 454 455 if (dp->chan[chan].mr0 != mr0b) { 456 sc->sc_chbase[CH_CR] = CR_CMD_MR0; 457 RECOVER(); 458 sc->sc_chbase[CH_MR] = dp->chan[chan].mr0; 459 } 460 } 461 } else { 462 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 463 RECOVER(); 464 } 465 466 mr1 = sc->sc_chbase[CH_MR]; 467 mr2 = sc->sc_chbase[CH_MR]; 468 if (mr1 != dp->chan[chan].new_mr1 || 469 mr2 != dp->chan[chan].new_mr2) { 470 sc->sc_chbase[CH_CR] = CR_CMD_MR1; 471 RECOVER(); 472 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr1; 473 sc->sc_chbase[CH_MR] = dp->chan[chan].new_mr2; 474 } 475 476 acr = dp->acr | (dp->mode & ACR_BRG); 477 dp->base[DU_ACR] = acr; /* write-only reg! */ 478 479 /* set speed codes */ 480 csr = (dp->chan[chan].icode<<4) | dp->chan[chan].ocode; 481 if (sc->sc_chbase[CH_CSR] != csr) { 482 sc->sc_chbase[CH_CSR] = csr; 483 } 484 485 /* see if counter/timer in use */ 486 if (dp->counter && 487 (dp->chan[0].icode == USE_CT || dp->chan[0].ocode == USE_CT || 488 dp->chan[1].icode == USE_CT || dp->chan[1].ocode == USE_CT)) { 489 490 /* program counter/timer only if necessary */ 491 if (dp->counter != dp->ocounter) { 492 uint16_t div; 493 #ifdef DIVS 494 int i; 495 496 /* look for precalculated rate, for minimum error */ 497 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { 498 if (divs[i].speed == dp->counter) { 499 div = divs[i].div; 500 goto found; 501 } 502 } 503 #endif 504 505 /* not found in table; calculate a value (rounding up) */ 506 div = ((long)SCN_CLOCK/16/2 + dp->counter/2) / dp->counter; 507 508 found: 509 /* halt before loading? may ALWAYS glitch? 510 * reload race may only sometimes glitch?? 511 */ 512 dp->base[DU_CTUR] = div >> 8; 513 dp->base[DU_CTLR] = div & 255; 514 if (dp->ocounter == 0) { 515 /* not previously used? */ 516 u_char temp; 517 /* start C/T running */ 518 temp = dp->base[DU_CSTRT]; 519 __USE(temp); 520 } 521 dp->ocounter = dp->counter; 522 } 523 } else { 524 /* counter not in use; mark as free */ 525 dp->counter = 0; 526 } 527 sc->sc_heldchanges = 0; 528 529 /* 530 * delay a tiny bit to try and avoid tx glitching. 531 * I know we're at spltty(), but this is much better than the 532 * old version used DELAY((96000 / out_speed) * 10000) 533 * -plb 534 */ 535 DELAY(10); 536 } 537 538 /* 539 * iterator function for speeds. 540 * (could be called "findnextcode") 541 * Returns sequence of possible speed codes for a given rate. 542 * should set index to zero before first call. 543 * 544 * Could be implemented as a "checkspeed()" function called 545 * to evaluate table entries, BUT this allows more variety in 546 * use of C/T with fewer table entries. 547 */ 548 549 static int 550 scniter(int *index, int wanted, int *counter, int *mode, struct chan *other, 551 int c92) 552 { 553 554 while (*index < TABENTRIES) { 555 struct tabent *tp; 556 557 tp = table + (*index)++; 558 if (tp->speed != wanted) 559 continue; 560 561 /* if not a 26C92 only look at MODE0 entries */ 562 if (!c92 && (tp->mode & MR0_MODE) != MR0_MODE_0) 563 continue; 564 565 /* 566 * check mode; 567 * OK if this table entry for current mode, or mode not 568 * yet set, or other channel's rates are available in both 569 * A and B groups. 570 */ 571 572 if (tp->mode == *mode || *mode == ANYMODE || 573 (other != NULL && (tp->mode & MR0_MODE) == (*mode & MR0_MODE) && 574 bothgroups[other->icode] && bothgroups[other->ocode])) { 575 /* 576 * for future table entries specifying 577 * use of counter/timer 578 */ 579 if (tp->code == USE_CT) { 580 if (*counter != wanted && *counter != 0) 581 continue; /* counter busy */ 582 *counter = wanted; 583 } 584 *mode = tp->mode; 585 return tp->code; 586 } 587 } 588 589 /* here after returning all applicable table entries */ 590 /* XXX return sequence of USE_CT with all possible modes?? */ 591 if ((*index)++ == TABENTRIES) { 592 /* Max C/T rate (even on 26C92?) is 57600 */ 593 if (wanted <= 57600 && (*counter == wanted || *counter == 0)) { 594 *counter = wanted; 595 return USE_CT; 596 } 597 } 598 599 return -1; /* FAIL */ 600 } 601 602 /* 603 * calculate configuration 604 * rewritten 2/97 -plb 605 */ 606 static int 607 scn_config(int unit, int chan, int ispeed, int ospeed, u_char mr1, u_char mr2) 608 { 609 struct scn_softc *sc; 610 struct duart *dp; 611 int other; /* opposite of chan */ 612 int mode; 613 int counter; 614 int i, o; /* input, output iterator indexes */ 615 int ic, oc; /* input, output codes */ 616 struct chan *ocp; /* other duart channel */ 617 struct tty *otp; /* other channel tty struct */ 618 int c92; /* true if duart is sc26c92 */ 619 int s; 620 621 /* Set up softc pointer. */ 622 if (unit >= scn_cd.cd_ndevs) 623 return ENXIO; 624 sc = SOFTC(unit); 625 chan = sc->sc_channel; 626 other = chan ^ 1; 627 dp = sc->sc_duart; 628 ocp = &dp->chan[other]; 629 otp = ocp->tty; 630 c92 = (dp->type == SC26C92); 631 632 /* 633 * Right now the first combination that works is used. 634 * Perhaps it should search entire solution space for "best" 635 * combination. For example, use heuristic weighting of mode 636 * preferences, and use of counter timer? 637 * 638 * For example right now with 2681/2692 when default rate is 639 * 9600 and other channel is closed setting 19200 will pick 640 * mode 0a and use counter/timer. Better solution might be 641 * mode 0b, leaving counter/timer free! 642 * 643 * When other channel is open might want to prefer 644 * leaving counter timer free, or not flipping A/B group? 645 */ 646 if (otp && (otp->t_state & TS_ISOPEN)) { 647 648 /* 649 * Other channel open; 650 * Find speed codes compatible with current mode/counter. 651 */ 652 653 i = 0; 654 for (;;) { 655 mode = dp->mode; 656 counter = dp->counter; 657 658 /* NOTE: pass other chan pointer to allow group flipping */ 659 ic = scniter(&i, ispeed, &counter, &mode, ocp, c92); 660 if (ic == -1) 661 break; 662 663 o = 0; 664 if ((oc = scniter(&o, ospeed, &counter, 665 &mode, NULL, c92)) != -1) { 666 /* 667 * take first match 668 * 669 * Perhaps calculate heuristic "score", 670 * save score,codes,mode,counter if score 671 * better than previous best? 672 */ 673 goto gotit; 674 } 675 } 676 /* XXX try looping for ospeed? */ 677 } else { 678 /* other channel closed */ 679 int oo, oi; /* other input, output iterators */ 680 int oic, ooc; /* other input, output codes */ 681 682 /* 683 * Here when other channel closed. Finds first 684 * combination that will allow other channel to be opened 685 * (with defaults) and fits our needs. 686 */ 687 oi = 0; 688 for (;;) { 689 mode = ANYMODE; 690 counter = 0; 691 692 oic = scniter(&oi, ocp->ispeed, &counter, &mode, NULL, c92); 693 if (oic == -1) 694 break; 695 696 oo = 0; 697 while ((ooc = scniter(&oo, ocp->ospeed, &counter, 698 &mode, NULL, c92)) != -1) { 699 i = 0; 700 while ((ic = scniter(&i, ispeed, &counter, 701 &mode, NULL, c92)) != -1) { 702 o = 0; 703 if ((oc = scniter(&o, ospeed, &counter, 704 &mode, NULL, c92)) != -1) { 705 /* 706 * take first match 707 * 708 * Perhaps calculate heuristic 709 * "score", save 710 * score,codes,mode,counter 711 * if score better than 712 * previous best? 713 */ 714 s = spltty(); 715 dp->chan[other].icode = oic; 716 dp->chan[other].ocode = ooc; 717 goto gotit2; 718 } 719 } 720 } 721 } 722 } 723 return EINVAL; 724 725 gotit: 726 s = spltty(); 727 gotit2: 728 dp->chan[chan].new_mr1 = mr1; 729 dp->chan[chan].new_mr2 = mr2; 730 dp->chan[chan].ispeed = ispeed; 731 dp->chan[chan].ospeed = ospeed; 732 dp->chan[chan].icode = ic; 733 dp->chan[chan].ocode = oc; 734 if (mode == ANYMODE) /* no mode selected?? */ 735 mode = DEFMODE(c92); 736 dp->mode = mode; 737 dp->counter = counter; 738 739 scn_setchip(sc); /* set chip now, if possible */ 740 splx(s); 741 return (0); 742 } 743 744 int 745 scn_match(device_t parent, struct cfdata *cf, void *aux) 746 { 747 struct mainbus_attach_args *ma = aux; 748 749 if ((mach_type == MACH_SGI_IP6 || mach_type == MACH_SGI_IP10) && 750 ma->ma_addr == 0x1fb80004) 751 return (1); 752 753 return (0); 754 } 755 756 /* 757 * No need to make scn_rx{en,dis}able too efficient, 758 * they're only called on setup, open & close! 759 */ 760 static inline void 761 scn_rxenable(struct scn_softc *sc) 762 { 763 struct duart *dp; 764 int channel; 765 766 dp = sc->sc_duart; 767 channel = sc->sc_channel; 768 769 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 770 if (channel == 0) 771 dp->opcr |= OPCR_OP4_RXRDYA; 772 else 773 dp->opcr |= OPCR_OP5_RXRDYB; 774 dp->base[DU_OPCR] = dp->opcr; 775 dp->imr |= sc->sc_rx_int; 776 dp->base[DU_IMR] = dp->imr; 777 } 778 779 static inline void 780 scn_rxdisable(struct scn_softc *sc) 781 { 782 struct duart *dp; 783 int channel; 784 785 dp = sc->sc_duart; 786 channel = sc->sc_channel; 787 788 /* Outputs wire-ored and connected to ICU input for fast rx interrupt. */ 789 if (channel == 0) 790 dp->opcr &= ~OPCR_OP4_RXRDYA; 791 else 792 dp->opcr &= ~OPCR_OP5_RXRDYB; 793 dp->base[DU_OPCR] = dp->opcr; 794 dp->imr &= ~sc->sc_rx_int; 795 dp->base[DU_IMR] = dp->imr; 796 } 797 798 void 799 scn_attach(device_t parent, device_t self, void *aux) 800 { 801 struct mainbus_attach_args *ma = aux; 802 struct scn_softc *sc; 803 struct duart *duart; 804 volatile u_char *ch_base; 805 volatile u_char *duart_base; 806 int channel; 807 int speed; 808 int s; 809 int maj __diagused; 810 u_char unit; 811 u_char duartno; 812 u_char delim = ':'; 813 u_char mr1, mr2; 814 enum scntype scntype = SCNUNK; 815 const char *duart_type = "Unknown"; 816 bool console, first; 817 devmajor_t major; 818 819 (void)major; 820 821 sc = device_private(self); 822 unit = device_unit(self); 823 824 /* XXX - hard-coded */ 825 if (ma->ma_addr == 0x1fb80004) 826 duartno = 1; 827 else 828 duartno = 0; 829 channel = 0; 830 console = 1; 831 832 duart = sc->sc_duart = &scn_duart[duartno]; 833 duart->chan[channel].sc = sc; 834 first = (duart->base == NULL); 835 836 if (console) { 837 sc->sc_isconsole = 1; 838 sc->sc_swflags |= SCN_SW_SOFTCAR; /* ignore carrier */ 839 } 840 841 duart_base = (volatile u_char *)MIPS_PHYS_TO_KSEG1(ma->ma_addr); 842 ch_base = duart_base; /* XXX */ 843 844 if (first) { 845 /* Probe DUART type */ 846 s = spltty(); 847 if (console) { 848 ch_base[CH_CR] = CR_DIS_TX; 849 delay(5 * 10000); 850 } 851 ch_base[CH_CR] = CR_CMD_MR1; 852 RECOVER(); 853 mr1 = ch_base[CH_MR]; 854 mr2 = ch_base[CH_MR]; 855 ch_base[CH_CR] = CR_CMD_MR1; 856 RECOVER(); 857 ch_base[CH_MR] = 1; 858 ch_base[CH_MR] = 0; 859 ch_base[CH_CR] = CR_CMD_MR1; 860 RECOVER(); 861 if (ch_base[CH_MR] == 1) { 862 /* MR 2 selected */ 863 ch_base[CH_CR] = CR_CMD_MR0; 864 RECOVER(); 865 /* if 2681, MR2 still selected */ 866 ch_base[CH_MR] = 1; 867 ch_base[CH_CR] = CR_CMD_MR1; 868 RECOVER(); 869 ch_base[CH_MR] = 0; /* MR1 */ 870 ch_base[CH_MR] = 0; /* MR2 */ 871 ch_base[CH_CR] = CR_CMD_MR0; 872 RECOVER(); 873 /* if 2681, MR2 still selected */ 874 if((ch_base[CH_MR] & 1) == 1) { 875 duart_type = "sc26c92"; 876 scntype = SC26C92; 877 } else { 878 /* 2681 treats as MR1 Select */ 879 ch_base[CH_CR] = CR_CMD_RTS_OFF; 880 RECOVER(); 881 ch_base[CH_MR] = 1; 882 ch_base[CH_MR] = 0; 883 ch_base[CH_CR] = CR_CMD_RTS_OFF; 884 RECOVER(); 885 if (ch_base[CH_MR] == 1) { 886 duart_type = "scn2681"; 887 scntype = SCN2681; 888 } else { 889 duart_type = "scn2692"; 890 scntype = SCN2692; 891 } 892 } 893 } 894 895 /* If a 2681, the CR_CMD_MR0 is interpreted as a TX_RESET */ 896 if (console) { 897 ch_base[CH_CR] = CR_ENA_TX; 898 RECOVER(); 899 } 900 ch_base[CH_CR] = CR_CMD_MR1; 901 RECOVER(); 902 ch_base[CH_MR] = mr1; 903 ch_base[CH_MR] = mr2; 904 splx(s); 905 906 /* 907 * On IP6 the console chip is duart1. The keyboard/mouse 908 * is duart0. Each chip has two channels and the channels 909 * share an interrupt. Duart0 is interrupt 0, duart1 is 910 * interrupt 1. 911 */ 912 if (duartno != 0 && duartno != 1) 913 panic("scn_attach: bad duartno: %d", duartno); 914 cpu_intr_establish(duartno, IPL_TTY, scnintr, duart); 915 916 printf("%c %s", delim, duart_type); 917 delim = ','; 918 919 duart->base = duart_base; 920 duart->type = scntype; 921 } 922 /* Record channel, uart */ 923 sc->sc_channel = channel; 924 sc->sc_chbase = ch_base; 925 926 /* Initialize modem/interrupt bit masks */ 927 if (channel == 0) { 928 sc->sc_op_rts = OP_RTSA; 929 sc->sc_op_dtr = OP_DTRA; 930 sc->sc_ip_cts = IP_CTSA; 931 sc->sc_ip_dcd = IP_DCDA; 932 933 sc->sc_tx_int = INT_TXA; 934 sc->sc_rx_int = INT_RXA; 935 } else { 936 sc->sc_op_rts = OP_RTSB; 937 sc->sc_op_dtr = OP_DTRB; 938 sc->sc_ip_cts = IP_CTSB; 939 sc->sc_ip_dcd = IP_DCDB; 940 941 sc->sc_tx_int = INT_TXB; 942 sc->sc_rx_int = INT_RXB; 943 } 944 945 /* Initialize counters */ 946 sc->sc_framing_errors = 0; 947 sc->sc_fifo_overruns = 0; 948 sc->sc_parity_errors = 0; 949 sc->sc_breaks = 0; 950 951 if (console) { 952 DELAY(5 * 10000); /* Let the output go out.... */ 953 } 954 955 /* 956 * Set up the hardware to a base state, in particular: 957 * o reset transmitter and receiver 958 * o set speeds and configurations 959 * o receiver interrupts only (RxRDY and BREAK) 960 */ 961 962 s = spltty(); 963 /* RTS off... */ 964 SCN_OP_BIC(sc, sc->sc_op_rts); /* "istop" */ 965 966 ch_base[CH_CR] = CR_DIS_RX | CR_DIS_TX; 967 RECOVER(); 968 ch_base[CH_CR] = CR_CMD_RESET_RX; 969 RECOVER(); 970 ch_base[CH_CR] = CR_CMD_RESET_TX; 971 RECOVER(); 972 ch_base[CH_CR] = CR_CMD_RESET_ERR; 973 RECOVER(); 974 ch_base[CH_CR] = CR_CMD_RESET_BRK; 975 RECOVER(); 976 ch_base[CH_CR] = CR_CMD_MR1; 977 RECOVER(); 978 979 /* No receiver control of RTS. */ 980 ch_base[CH_MR] = 0; 981 ch_base[CH_MR] = 0; 982 983 /* Initialize the uart structure if this is channel A. */ 984 if (first) { 985 /* Disable all interrupts. */ 986 duart_base[DU_IMR] = duart->imr = 0; 987 988 /* Output port config */ 989 duart_base[DU_OPCR] = duart->opcr = 0; 990 991 /* Speeds... */ 992 duart->mode = 0; 993 994 /* 995 * Set initial speed to an illegal code that can be changed to 996 * any other baud. 997 */ 998 duart->chan[0].icode = duart->chan[0].ocode = 0x2f; 999 duart->chan[1].icode = duart->chan[1].ocode = 0x2f; 1000 duart->chan[0].ispeed = duart->chan[0].ospeed = 0; 1001 duart->chan[1].ispeed = duart->chan[1].ospeed = 0; 1002 1003 duart->acr = 0; 1004 duart->acr |= ACR_CT_TCLK1; /* timer mode 1x clk */ 1005 } 1006 1007 if (channel == 0) { 1008 duart->acr |= ACR_DELTA_DCDA; /* Set CD int */ 1009 } else { 1010 duart->acr |= ACR_DELTA_DCDB; /* Set CD int */ 1011 } 1012 1013 if (scnsir == NULL) { 1014 /* software intr: calls tty code, hence IPL_TTY */ 1015 scnsir = softint_establish(SOFTINT_SERIAL, scnsoft, NULL); 1016 } 1017 1018 duart_base[DU_ACR] = (duart->mode & ACR_BRG) | duart->acr; 1019 1020 if (console) 1021 speed = scnconsrate; 1022 else 1023 speed = scndefaultrate; 1024 1025 scn_config(unit, channel, speed, speed, MR1_PNONE | MR1_CS8, MR2_STOP1); 1026 if (console) { 1027 maj = cdevsw_lookup_major(&scn_cdevsw); 1028 KASSERT(maj != NODEVMAJOR); 1029 shutdownhook_establish(scncnreinit, NULL); 1030 /* Make sure console can do scncngetc */ 1031 duart_base[DU_OPSET] = channel ? (OP_RTSB | OP_DTRB) : 1032 (OP_RTSA | OP_DTRA); 1033 } 1034 1035 /* Turn on the receiver and transmitters */ 1036 ch_base[CH_CR] = CR_ENA_RX | CR_ENA_TX; 1037 1038 /* Set up the interrupts. */ 1039 duart->imr |= INT_IP; 1040 scn_rxdisable(sc); 1041 splx(s); 1042 1043 if (sc->sc_swflags) { 1044 printf("%c flags %d", delim, sc->sc_swflags); 1045 delim = ','; 1046 } 1047 1048 #ifdef KGDB 1049 major = cdevsw_lookup_major(&scn_cdevsw); 1050 KASSERT(major != NODEVMAJOR); 1051 if (kgdb_dev == makedev(major, unit)) { 1052 if (console) 1053 kgdb_dev = NODEV; /* can't debug over console port */ 1054 else { 1055 scninit(kgdb_dev, kgdb_rate); 1056 scn_rxenable(sc); 1057 scn->sc_iskgdb = 1; 1058 kgdb_attach(scncngetc, scncnputc, kgdb_dev); 1059 if (kgdb_debug_init) { 1060 printf("%c ", delim); 1061 kgdb_connect(1); 1062 } else 1063 printf("%c kgdb enabled", delim); 1064 delim = ','; 1065 } 1066 } 1067 #endif 1068 printf("\n"); 1069 } 1070 1071 /* ARGSUSED */ 1072 int 1073 scnopen(dev_t dev, int flags, int mode, struct lwp *l) 1074 { 1075 struct tty *tp; 1076 int unit = DEV_UNIT(dev); 1077 struct scn_softc *sc; 1078 int error = 0; 1079 1080 if (unit >= scn_cd.cd_ndevs) 1081 return ENXIO; 1082 sc = SOFTC(unit); 1083 if (!sc) 1084 return ENXIO; 1085 1086 tp = sc->sc_tty; 1087 if (!tp) { 1088 tp = tty_alloc(); 1089 sc->sc_tty = sc->sc_duart->chan[sc->sc_channel].tty = tp; 1090 tty_attach(tp); 1091 } 1092 1093 tp->t_oproc = scnstart; 1094 tp->t_param = scnparam; 1095 tp->t_hwiflow = scnhwiflow; 1096 tp->t_dev = dev; 1097 1098 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1099 return (EBUSY); 1100 1101 ttylock(tp); 1102 1103 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1104 ttychars(tp); 1105 tp->t_iflag = TTYDEF_IFLAG; 1106 tp->t_oflag = TTYDEF_OFLAG; 1107 tp->t_cflag = SCNDEF_CFLAG; 1108 1109 sc->sc_rx_blocked = 0; 1110 1111 if (sc->sc_swflags & SCN_SW_CLOCAL) 1112 tp->t_cflag |= CLOCAL; 1113 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1114 tp->t_cflag |= CCTS_OFLOW | CRTS_IFLOW; 1115 tp->t_lflag = TTYDEF_LFLAG; 1116 if (sc->sc_isconsole) 1117 tp->t_ispeed = tp->t_ospeed = scnconsrate; 1118 else 1119 tp->t_ispeed = tp->t_ospeed = scndefaultrate; 1120 scnparam(tp, &tp->t_termios); 1121 ttsetwater(tp); 1122 1123 /* Turn on DTR and RTS. */ 1124 SCN_OP_BIS(sc, sc->sc_op_rts | sc->sc_op_dtr); 1125 1126 /* enable receiver interrupts */ 1127 scn_rxenable(sc); 1128 1129 /* set carrier state; */ 1130 if ((sc->sc_swflags & SCN_SW_SOFTCAR) || /* check ttyflags */ 1131 SCN_DCD(sc) || /* check h/w */ 1132 DEV_DIALOUT(dev)) 1133 tp->t_state |= TS_CARR_ON; 1134 else 1135 tp->t_state &= ~TS_CARR_ON; 1136 } 1137 1138 ttyunlock(tp); 1139 1140 error = ttyopen(tp, SCN_DIALOUT(sc), flags & O_NONBLOCK); 1141 if (error) printf("ttyopen failed line %d, error %d\n", __LINE__, error); 1142 if (error) 1143 goto bad; 1144 1145 error = (*tp->t_linesw->l_open) (dev, tp); 1146 if (error) printf("l_open failed line %d, error %d\n", __LINE__, error); 1147 if (error) 1148 goto bad; 1149 1150 return (0); 1151 1152 bad: 1153 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) { 1154 scn_rxdisable(sc); 1155 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1156 } 1157 1158 return (error); 1159 } 1160 1161 1162 /*ARGSUSED*/ 1163 int 1164 scnclose(dev_t dev, int flags, int mode, struct lwp *l) 1165 { 1166 int unit = DEV_UNIT(dev); 1167 struct scn_softc *sc = SOFTC(unit); 1168 struct tty *tp = sc->sc_tty; 1169 devmajor_t major; 1170 1171 (void)major; 1172 1173 if ((tp->t_state & TS_ISOPEN) == 0) 1174 return 0; 1175 1176 (*tp->t_linesw->l_close) (tp, flags); 1177 1178 #ifdef KGDB 1179 /* do not disable interrupts if debugging */ 1180 major = cdevsw_lookup_major(&scn_devsw); 1181 KASSERT(major != cdevsw_lookup_major); 1182 if (kgdb_dev != makedev(major, unit)) 1183 #endif 1184 if ((tp->t_state & TS_ISOPEN) == 0) { 1185 scn_rxdisable(sc); 1186 } 1187 if ((tp->t_cflag & HUPCL) && (sc->sc_swflags & SCN_SW_SOFTCAR) == 0) { 1188 SCN_OP_BIC(sc, sc->sc_op_dtr); 1189 /* hold low for 1 second */ 1190 tsleep(sc, TTIPRI, ttclos, hz); 1191 } 1192 SCN_CLRDIALOUT(sc); 1193 ttyclose(tp); 1194 1195 #if 0 1196 if ((tp->t_state & TS_ISOPEN) == 0) { 1197 tty_free(tp); 1198 sc->sc_tty = (struct tty *) NULL; 1199 } 1200 #endif 1201 1202 return (0); 1203 } 1204 1205 int 1206 scnread(dev_t dev, struct uio *uio, int flags) 1207 { 1208 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1209 struct tty *tp = sc->sc_tty; 1210 1211 return ((*tp->t_linesw->l_read) (tp, uio, flags)); 1212 } 1213 1214 int 1215 scnwrite(dev_t dev, struct uio *uio, int flags) 1216 { 1217 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1218 struct tty *tp = sc->sc_tty; 1219 1220 return ((*tp->t_linesw->l_write) (tp, uio, flags)); 1221 } 1222 1223 int 1224 scnpoll(dev_t dev, int events, struct lwp *l) 1225 { 1226 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1227 struct tty *tp = sc->sc_tty; 1228 1229 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1230 } 1231 1232 struct tty * 1233 scntty(dev_t dev) 1234 { 1235 struct scn_softc *sc = SOFTC(DEV_UNIT(dev)); 1236 1237 return sc->sc_tty; 1238 } 1239 1240 /* Worker routines for interrupt processing */ 1241 static inline void 1242 dcd_int(struct scn_softc *sc, struct tty *tp, u_char new) 1243 { 1244 1245 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1246 return; 1247 1248 #if 0 1249 printf("scn%d: dcd_int ip %x SCN_DCD %x new %x ipcr %x\n", 1250 sc->unit, 1251 sc->sc_duart->base[DU_IP], 1252 SCN_DCD(sc), 1253 new, 1254 sc->sc_duart->base[DU_IPCR] 1255 ); 1256 #endif 1257 1258 /* XXX set some flag to have some lower (soft) int call line discipline? */ 1259 if (!(*tp->t_linesw->l_modem) (tp, new == 0? 1: 0)) { 1260 SCN_OP_BIC(sc, sc->sc_op_rts | sc->sc_op_dtr); 1261 } 1262 } 1263 1264 /* 1265 * Print out a ring or fifo overrun error message. 1266 */ 1267 static void 1268 scnoverrun(int unit, long *ptime, const char *what) 1269 { 1270 1271 if (*ptime != time_second) { 1272 *ptime = time_second; 1273 log(LOG_WARNING, "scn%d: %s overrun\n", unit, what); 1274 } 1275 } 1276 1277 /* 1278 * Try to block or unblock input using hardware flow-control. 1279 * This is called by kern/tty.c if MDMBUF|CRTSCTS is set, and 1280 * if this function returns non-zero, the TS_TBLOCK flag will 1281 * be set or cleared according to the "stop" arg passed. 1282 */ 1283 int 1284 scnhwiflow(struct tty *tp, int stop) 1285 { 1286 int unit = DEV_UNIT(tp->t_dev); 1287 struct scn_softc *sc = SOFTC(unit); 1288 int s; 1289 1290 s = splrtty(); 1291 if (!stop) { 1292 if (sc->sc_rbput - sc->sc_rbget - 1) { 1293 setsoftscn(); 1294 } 1295 } 1296 splx(s); 1297 return 1; 1298 } 1299 1300 static int 1301 scnintr(void *arg) 1302 { 1303 struct duart *duart = arg; 1304 struct scn_softc *sc0 = duart->chan[0].sc; 1305 struct scn_softc *sc1 = duart->chan[1].sc; 1306 1307 struct tty *tp0 = (sc0 != NULL) ? sc0->sc_tty : NULL; 1308 struct tty *tp1 = (sc1 != NULL) ? sc1->sc_tty : NULL; 1309 1310 char rs_work; 1311 u_char rs_stat; 1312 u_char rs_ipcr; 1313 1314 /* Check for RX interrupts first, since we cannot distinguish by irq. */ 1315 scnrxintr(duart); 1316 1317 do { 1318 /* Loop to pick up ALL pending interrupts for device. */ 1319 rs_work = false; 1320 rs_stat = duart->base[DU_ISR]; 1321 1322 /* channel a */ 1323 if (tp0 != NULL) { 1324 if ((rs_stat & INT_TXA) && (tp0->t_state & TS_BUSY)) { 1325 /* output char done. */ 1326 tp0->t_state &= ~(TS_BUSY | TS_FLUSH); 1327 1328 /* disable tx ints */ 1329 duart->imr &= ~sc0->sc_tx_int; 1330 duart->base[DU_IMR] = duart->imr; 1331 1332 if (sc0->sc_heldchanges) { 1333 scn_setchip(sc0); 1334 } 1335 1336 (*tp0->t_linesw->l_start) (tp0); 1337 rs_work = true; 1338 } 1339 } 1340 /* channel b */ 1341 if (tp1 != NULL) { 1342 if ((rs_stat & INT_TXB) && (tp1->t_state & TS_BUSY)) { 1343 /* output char done. */ 1344 tp1->t_state &= ~(TS_BUSY | TS_FLUSH); 1345 1346 /* disable tx ints */ 1347 duart->imr &= ~sc1->sc_tx_int; 1348 duart->base[DU_IMR] = duart->imr; 1349 1350 if (sc1->sc_heldchanges) { 1351 scn_setchip(sc1); 1352 } 1353 1354 (*tp1->t_linesw->l_start) (tp1); 1355 rs_work = true; 1356 } 1357 } 1358 if (rs_stat & INT_IP) { 1359 rs_work = true; 1360 rs_ipcr = duart->base[DU_IPCR]; 1361 1362 if (rs_ipcr & IPCR_DELTA_DCDA && tp0 != NULL) { 1363 dcd_int(sc0, tp0, rs_ipcr & IPCR_DCDA); 1364 } 1365 if (rs_ipcr & IPCR_DELTA_DCDB && tp1 != NULL) { 1366 dcd_int(sc1, tp1, rs_ipcr & IPCR_DCDB); 1367 } 1368 } 1369 } while (rs_work); 1370 1371 return (1); /* ? */ 1372 } 1373 1374 /* 1375 * Handle rxrdy/ffull interrupt: QUICKLY poll both channels (checking 1376 * status first) and stash data in a ring buffer. Ring buffer scheme 1377 * borowed from sparc/zs.c requires NO interlock on data! 1378 * 1379 * This interrupt should NOT be included in spltty() mask since it 1380 * invokes NO tty code! The whole point is to allow tty input as much 1381 * of the time as possible, while deferring "heavy" character 1382 * processing until later. 1383 * 1384 * see scn.hw.README and scnsoft() for more info. 1385 * 1386 * THIS ROUTINE SHOULD BE KEPT AS CLEAN AS POSSIBLE!! 1387 * IT'S A CANDIDATE FOR RECODING IN ASSEMBLER!! 1388 */ 1389 static inline int 1390 scn_rxintr(struct scn_softc *sc) 1391 { 1392 char sr; 1393 int i, n; 1394 int work; 1395 1396 work = 0; 1397 i = sc->sc_rbput; 1398 while (work <= 10) { 1399 #define SCN_GETCH(SC) \ 1400 sr = (SC)->sc_chbase[CH_SR]; \ 1401 if ((sr & SR_RX_RDY) == 0) \ 1402 break; \ 1403 if (sr & (SR_PARITY | SR_FRAME | SR_BREAK | SR_OVERRUN)) \ 1404 goto exception; \ 1405 work++; \ 1406 (SC)->sc_rbuf[i++ & SCN_RING_MASK] = (SC)->sc_chbase[CH_DAT] 1407 1408 SCN_GETCH(sc); SCN_GETCH(sc); SCN_GETCH(sc); 1409 /* XXX more here if 26C92? -plb */ 1410 continue; 1411 exception: 1412 #if defined(DDB) 1413 if (sc->sc_isconsole && (sr & SR_BREAK)) { 1414 Debugger(); 1415 sr = sc->sc_chbase[CH_SR]; 1416 } 1417 #endif 1418 #if defined(KGDB) 1419 if (sc->sc_iskgdb && (sr & SR_RX_RDY)) { 1420 kgdb_connect(1); 1421 sr = sc->sc_chbase[CH_SR]; 1422 } 1423 #endif 1424 work++; 1425 sc->sc_rbuf[i++ & SCN_RING_MASK] = (sr << 8) | sc->sc_chbase[CH_DAT]; 1426 sc->sc_chbase[CH_CR] = CR_CMD_RESET_ERR; /* resets break? */ 1427 RECOVER(); 1428 } 1429 /* 1430 * If ring is getting too full, try to block input. 1431 */ 1432 n = i - sc->sc_rbget; 1433 if (sc->sc_rbhiwat && (n > sc->sc_rbhiwat)) { 1434 /* If not CRTSCTS sc_rbhiwat is such that this 1435 * never happens. 1436 * Clear RTS 1437 */ 1438 SCN_OP_BIC(sc, sc->sc_op_rts); 1439 sc->sc_rx_blocked = 1; 1440 } 1441 sc->sc_rbput = i; 1442 1443 return work; 1444 } 1445 1446 static void 1447 scnrxintr(void *arg) 1448 { 1449 struct duart *duart = arg; 1450 int work = 0; 1451 1452 if (duart->chan[0].sc != NULL) 1453 work += scn_rxintr(duart->chan[0].sc); 1454 if (duart->chan[1].sc != NULL) 1455 work += scn_rxintr(duart->chan[1].sc); 1456 if (work > 0) { 1457 setsoftscn(); /* trigger s/w intr */ 1458 #ifdef SCN_TIMING 1459 microtime(&tstart); 1460 #endif 1461 } 1462 } 1463 1464 /* 1465 * Here on soft interrupt (at spltty) to empty ring buffers. 1466 * 1467 * Dave's original scheme was to use the DUART receiver timeout 1468 * interrupt. This requires 2692's (which my board doesn't have), and 1469 * I also liked the idea of using the C/T to generate alternate and/or 1470 * arbitrary bauds. -plb 1471 * 1472 * The ringbuffer code comes from Chris Torek's SPARC 44bsd zs driver 1473 * (hence the LBL notice on top of this file), DOES NOT require 1474 * interlocking with interrupt levels! 1475 * 1476 * The 44bsd sparc/zs driver reads the ring buffer from a separate 1477 * zssoftint, while the SunOS 4.x zs driver appears to use 1478 * timeout()'s. timeouts seem to be too slow to deal with high data 1479 * rates. I know, I tried them. 1480 * -plb. 1481 */ 1482 static void 1483 scnsoft(void *arg) 1484 { 1485 int s, unit; 1486 #ifdef SCN_TIMING 1487 struct timeval tend; 1488 u_long t; 1489 1490 microtime(&tend); 1491 t = (tend.tv_sec - tstart.tv_sec) * 1000000 + (tend.tv_usec - tstart.tv_usec); 1492 t = (t + tick / 20) / (tick / 10); 1493 if (t >= NJITTER - 1) { 1494 t = NJITTER - 1; 1495 } 1496 scn_jitter[t]++; 1497 #endif 1498 1499 for (unit = 0; unit < scn_cd.cd_ndevs; unit++) { 1500 struct scn_softc *sc; 1501 struct tty *tp; 1502 int n, get; 1503 1504 sc = SOFTC(unit); 1505 if (sc == NULL) { 1506 continue; 1507 } 1508 tp = sc->sc_tty; 1509 #ifdef KGDB 1510 if (tp == NULL) { 1511 sc->sc_rbget = sc->sc_rbput; 1512 continue; 1513 } 1514 #endif 1515 if (tp == NULL || tp->t_state & TS_TBLOCK) { 1516 continue; 1517 } 1518 1519 1520 get = sc->sc_rbget; 1521 1522 /* NOTE: fetch from rbput is atomic */ 1523 while (get != (n = sc->sc_rbput)) { 1524 /* 1525 * Compute the number of interrupts in the receive ring. 1526 * If the count is overlarge, we lost some events, and 1527 * must advance to the first valid one. It may get 1528 * overwritten if more data are arriving, but this is 1529 * too expensive to check and gains nothing (we already 1530 * lost out; all we can do at this point is trade one 1531 * kind of loss for another). 1532 */ 1533 n -= get; 1534 if (n > SCN_RING_SIZE) { 1535 scnoverrun(unit, &sc->sc_rotime, "ring"); 1536 get += n - SCN_RING_SIZE; 1537 n = SCN_RING_SIZE; 1538 sc->sc_ring_overruns++; 1539 } 1540 while (--n >= 0) { 1541 int c, sr; 1542 1543 if (tp->t_state & TS_TBLOCK) { 1544 sc->sc_rbget = get; 1545 goto done; 1546 } 1547 /* Race to keep ahead of incoming interrupts. */ 1548 c = sc->sc_rbuf[get++ & SCN_RING_MASK]; 1549 1550 sr = c >> 8; /* extract status */ 1551 c &= 0xff; /* leave just character */ 1552 1553 if (sr & SR_OVERRUN) { 1554 scnoverrun(unit, &sc->sc_fotime, "fifo"); 1555 sc->sc_fifo_overruns++; 1556 } 1557 if (sr & SR_PARITY) { 1558 c |= TTY_PE; 1559 sc->sc_parity_errors++; 1560 } 1561 if (sr & SR_FRAME) { 1562 c |= TTY_FE; 1563 sc->sc_framing_errors++; 1564 } 1565 if (sr & SR_BREAK) { 1566 #if 0 1567 /* 1568 * See DDB_CHECK() comments in 1569 * scnrxintr() 1570 */ 1571 if (sc->sc_isconsole) 1572 Debugger(); 1573 #endif 1574 c = TTY_FE | 0; 1575 sc->sc_breaks++; 1576 } 1577 1578 (*tp->t_linesw->l_rint) (c, tp); 1579 1580 if (sc->sc_rx_blocked && n < SCN_RING_THRESH) { 1581 s = splrtty(); 1582 sc->sc_rx_blocked = 0; 1583 SCN_OP_BIS(sc, sc->sc_op_rts); 1584 splx(s); 1585 } 1586 1587 } 1588 sc->sc_rbget = get; 1589 } 1590 done: ; 1591 } 1592 } 1593 1594 /* Convert TIOCM_xxx bits to output port bits. */ 1595 static unsigned char 1596 opbits(struct scn_softc *sc, int tioc_bits) 1597 { 1598 1599 return ((((tioc_bits) & TIOCM_DTR) ? sc->sc_op_dtr : 0) | 1600 (((tioc_bits) & TIOCM_RTS) ? sc->sc_op_rts : 0)); 1601 } 1602 1603 int 1604 scnioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1605 { 1606 int unit = DEV_UNIT(dev); 1607 struct scn_softc *sc = SOFTC(unit); 1608 struct tty *tp = sc->sc_tty; 1609 int error; 1610 1611 error = (*tp->t_linesw->l_ioctl) (tp, cmd, data, flags, l); 1612 if (error != EPASSTHROUGH) 1613 return (error); 1614 1615 error = ttioctl(tp, cmd, data, flags, l); 1616 if (error != EPASSTHROUGH) 1617 return (error); 1618 1619 switch (cmd) { 1620 case TIOCSBRK: 1621 sc->sc_chbase[CH_CR] = CR_CMD_START_BRK; 1622 break; 1623 1624 case TIOCCBRK: 1625 sc->sc_chbase[CH_CR] = CR_CMD_STOP_BRK; 1626 break; 1627 1628 case TIOCSDTR: 1629 SCN_OP_BIS(sc, sc->sc_op_dtr | sc->sc_op_rts); 1630 break; 1631 1632 case TIOCCDTR: 1633 SCN_OP_BIC(sc, sc->sc_op_dtr | sc->sc_op_rts); 1634 break; 1635 1636 case TIOCMSET: { 1637 int s; 1638 unsigned char sbits, cbits; 1639 1640 /* set bits */ 1641 sbits = opbits(sc, *(int *) data); 1642 1643 /* get bits to clear */ 1644 cbits = ~sbits & (sc->sc_op_dtr | sc->sc_op_rts); 1645 1646 s = spltty(); 1647 if (sbits) { 1648 SCN_OP_BIS(sc, sbits); 1649 } 1650 if (cbits) { 1651 SCN_OP_BIC(sc, cbits); 1652 } 1653 splx(s); 1654 break; 1655 } 1656 1657 case TIOCMBIS: 1658 SCN_OP_BIS(sc, opbits(sc, *(int *) data)); 1659 break; 1660 1661 case TIOCMBIC: 1662 SCN_OP_BIC(sc, opbits(sc, *(int *) data)); 1663 break; 1664 1665 case TIOCMGET: { 1666 int bits; 1667 unsigned char ip; 1668 1669 /* s = spltty(); */ 1670 ip = sc->sc_duart->base[DU_IP]; 1671 /* splx(s); */ 1672 1673 bits = 0; 1674 if (ip & sc->sc_ip_dcd) 1675 bits |= TIOCM_CD; 1676 if (ip & sc->sc_ip_cts) 1677 bits |= TIOCM_CTS; 1678 1679 #if 0 1680 /* 1681 * XXX sigh; cannot get op current state!! even if 1682 * maintained in private, RTS is done in h/w!! 1683 */ 1684 unsigned char op = 0; 1685 if (op & sc->sc_op_dtr) 1686 bits |= TIOCM_DTR; 1687 if (op & sc->sc_op_rts) 1688 bits |= TIOCM_RTS; 1689 #endif 1690 1691 *(int *) data = bits; 1692 break; 1693 } 1694 1695 case TIOCGFLAGS:{ 1696 int bits = 0; 1697 1698 if (sc->sc_swflags & SCN_SW_SOFTCAR) 1699 bits |= TIOCFLAG_SOFTCAR; 1700 if (sc->sc_swflags & SCN_SW_CLOCAL) 1701 bits |= TIOCFLAG_CLOCAL; 1702 if (sc->sc_swflags & SCN_SW_CRTSCTS) 1703 bits |= TIOCFLAG_CRTSCTS; 1704 if (sc->sc_swflags & SCN_SW_MDMBUF) 1705 bits |= TIOCFLAG_MDMBUF; 1706 1707 *(int *) data = bits; 1708 break; 1709 } 1710 case TIOCSFLAGS:{ 1711 int userbits, driverbits = 0; 1712 1713 error = kauth_authorize_device_tty(l->l_cred, 1714 KAUTH_DEVICE_TTY_PRIVSET, tp); 1715 if (error != 0) 1716 return (EPERM); 1717 1718 userbits = *(int *) data; 1719 if (userbits & TIOCFLAG_SOFTCAR) 1720 driverbits |= SCN_SW_SOFTCAR; 1721 if (userbits & TIOCFLAG_CLOCAL) 1722 driverbits |= SCN_SW_CLOCAL; 1723 if (userbits & TIOCFLAG_CRTSCTS) 1724 driverbits |= SCN_SW_CRTSCTS; 1725 if (userbits & TIOCFLAG_MDMBUF) 1726 driverbits |= SCN_SW_MDMBUF; 1727 1728 sc->sc_swflags = driverbits; 1729 1730 break; 1731 } 1732 1733 default: 1734 return (EPASSTHROUGH); 1735 } 1736 return (0); 1737 } 1738 1739 int 1740 scnparam(struct tty *tp, struct termios *t) 1741 { 1742 int cflag = t->c_cflag; 1743 int unit = DEV_UNIT(tp->t_dev); 1744 char mr1, mr2; 1745 int error; 1746 struct scn_softc *sc = SOFTC(unit); 1747 1748 /* Is this a hang up? */ 1749 if (t->c_ospeed == B0) { 1750 SCN_OP_BIC(sc, sc->sc_op_dtr); 1751 /* leave DTR down. see comment in scnclose() -plb */ 1752 return (0); 1753 } 1754 mr1 = mr2 = 0; 1755 1756 /* Parity? */ 1757 if (cflag & PARENB) { 1758 if ((cflag & PARODD) == 0) 1759 mr1 |= MR1_PEVEN; 1760 else 1761 mr1 |= MR1_PODD; 1762 } else 1763 mr1 |= MR1_PNONE; 1764 1765 /* Stop bits. */ 1766 if (cflag & CSTOPB) 1767 mr2 |= MR2_STOP2; 1768 else 1769 mr2 |= MR2_STOP1; 1770 1771 /* Data bits. */ 1772 switch (cflag & CSIZE) { 1773 case CS5: 1774 mr1 |= MR1_CS5; 1775 break; 1776 case CS6: 1777 mr1 |= MR1_CS6; 1778 break; 1779 case CS7: 1780 mr1 |= MR1_CS7; 1781 break; 1782 case CS8: 1783 default: 1784 mr1 |= MR1_CS8; 1785 break; 1786 } 1787 1788 if (cflag & CCTS_OFLOW) 1789 mr2 |= MR2_TXCTS; 1790 1791 if (cflag & CRTS_IFLOW) { 1792 mr1 |= MR1_RXRTS; 1793 sc->sc_rbhiwat = SCN_RING_HIWAT; 1794 } else { 1795 sc->sc_rbhiwat = 0; 1796 } 1797 1798 error = scn_config(unit, sc->sc_channel, t->c_ispeed, 1799 t->c_ospeed, mr1, mr2); 1800 1801 /* If successful, copy to tty */ 1802 if (!error) { 1803 tp->t_ispeed = t->c_ispeed; 1804 tp->t_ospeed = t->c_ospeed; 1805 tp->t_cflag = cflag; 1806 } 1807 return (error); 1808 } 1809 1810 /* 1811 * Start or restart a transmission. 1812 */ 1813 void 1814 scnstart(struct tty *tp) 1815 { 1816 int s, c; 1817 int unit = DEV_UNIT(tp->t_dev); 1818 struct scn_softc *sc = SOFTC(unit); 1819 1820 s = spltty(); 1821 if (tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1822 goto out; 1823 if (!ttypull(tp)) 1824 goto out; 1825 1826 tp->t_state |= TS_BUSY; 1827 1828 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) { 1829 if ((c = getc(&tp->t_outq)) == -1) 1830 break; 1831 sc->sc_chbase[CH_DAT] = c; 1832 } 1833 sc->sc_duart->imr |= (sc->sc_tx_int | sc->sc_rx_int); 1834 sc->sc_duart->base[DU_IMR] = sc->sc_duart->imr; 1835 1836 out: 1837 splx(s); 1838 } 1839 1840 /* 1841 * Stop output on a line. 1842 */ 1843 /*ARGSUSED*/ 1844 void 1845 scnstop(struct tty *tp, int flags) 1846 { 1847 int s; 1848 1849 s = spltty(); 1850 if (tp->t_state & TS_BUSY) { 1851 if ((tp->t_state & TS_TTSTOP) == 0) 1852 tp->t_state |= TS_FLUSH; 1853 } 1854 splx(s); 1855 } 1856 1857 /* 1858 * Following are all routines needed for SCN to act as console. 1859 */ 1860 1861 void 1862 scncnprobe(struct consdev *cn) 1863 { 1864 } 1865 1866 void 1867 scncnreinit(void *v) 1868 { 1869 volatile u_char *du_base = 1870 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1871 1872 du_base[DU_OPSET] = 1873 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1874 } 1875 1876 void 1877 scncninit(struct consdev *cn) 1878 { 1879 devmajor_t major; 1880 1881 /* initialize required fields */ 1882 major = cdevsw_lookup_major(&scn_cdevsw); 1883 KASSERT(major != NODEV); 1884 cn->cn_dev = makedev(major, SCN_CONSOLE); 1885 cn->cn_pri = CN_REMOTE; 1886 1887 scninit(cn->cn_dev, scnconsrate); 1888 } 1889 1890 /* Used by scncninit and kgdb startup. */ 1891 int 1892 scninit(dev_t dev, int rate) 1893 { 1894 /* XXX - maintain PROM's settings */ 1895 #if 0 1896 volatile u_char *du_base = 1897 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1898 int unit = DEV_UNIT(dev); 1899 1900 du_base[DU_OPSET] = 1901 SCN_CONSCHAN ? (OP_RTSB | OP_DTRB) : (OP_RTSA | OP_DTRA); 1902 scn_config(unit, SCN_CONSCHAN, rate, rate, 1903 MR1_PNONE | MR1_CS8, MR2_STOP1); 1904 #endif 1905 return (0); 1906 } 1907 1908 /* 1909 * Console kernel input character routine. 1910 */ 1911 int 1912 scncngetc(dev_t dev) 1913 { 1914 volatile u_char *ch_base = 1915 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1916 char c; 1917 int s; 1918 1919 s = spltty(); 1920 1921 while ((ch_base[CH_SR] & SR_RX_RDY) == 0) 1922 ; 1923 c = ch_base[CH_DAT]; 1924 1925 splx(s); 1926 return c; 1927 } 1928 1929 void 1930 scncnpollc(dev_t dev, int on) 1931 { 1932 } 1933 1934 /* 1935 * Console kernel output character routine. 1936 */ 1937 void 1938 scncnputc(dev_t dev, int c) 1939 { 1940 volatile u_char *ch_base = 1941 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1942 volatile u_char *du_base = 1943 (volatile u_char *)MIPS_PHYS_TO_KSEG1(0x1fb80004); 1944 int s; 1945 1946 s = spltty(); 1947 1948 if (c == '\n') 1949 scncnputc(dev, '\r'); 1950 1951 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1952 ; 1953 ch_base[CH_DAT] = c; 1954 while ((ch_base[CH_SR] & SR_TX_RDY) == 0) 1955 ; 1956 du_base[DU_ISR]; 1957 1958 splx(s); 1959 } 1960