xref: /netbsd-src/sys/arch/sgimips/dev/dpclock.c (revision 7330f729ccf0bd976a06f95fad452fe774fc7fd1)
1 /*	$NetBSD: dpclock.c,v 1.6 2015/02/18 16:47:58 macallan Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Erik Reid
5  * Copyright (c) 2001 Rafal K. Boni
6  * Copyright (c) 2001 Christopher Sekiya
7  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
8  * All rights reserved.
9  *
10  * Portions of this code are derived from software contributed to The
11  * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace
12  * Simulation Facility, NASA Ames Research Center.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in the
21  *    documentation and/or other materials provided with the distribution.
22  * 3. The name of the author may not be used to endorse or promote products
23  *    derived from this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41 
42 #include <sys/bus.h>
43 #include <machine/autoconf.h>
44 #include <machine/sysconf.h>
45 #include <machine/machtype.h>
46 
47 #include <dev/clock_subr.h>
48 #include <sgimips/dev/dp8573areg.h>
49 
50 #include <sgimips/sgimips/clockvar.h>
51 
52 struct dpclock_softc {
53 	struct todr_chip_handle sc_todrch;
54 
55 	/* RTC registers */
56 	bus_space_tag_t		sc_rtct;
57 	bus_space_handle_t	sc_rtch;
58 	int			sc_offset;
59 };
60 
61 static int	dpclock_match(device_t, cfdata_t, void *);
62 static void	dpclock_attach(device_t, device_t, void *);
63 static int	dpclock_gettime(struct todr_chip_handle *, struct timeval *);
64 static int	dpclock_settime(struct todr_chip_handle *, struct timeval *);
65 
66 CFATTACH_DECL_NEW(dpclock, sizeof(struct dpclock_softc),
67     dpclock_match, dpclock_attach, NULL, NULL);
68 
69 static int
70 dpclock_match(device_t parent, cfdata_t cf, void *aux)
71 {
72 	struct mainbus_attach_args *ma = aux;
73 
74 	switch (mach_type) {
75 	case MACH_SGI_IP6 | MACH_SGI_IP10:
76 		if (ma->ma_addr == 0x1fbc0000)
77 			return (1);
78 		break;
79 
80 	case MACH_SGI_IP12:
81 	case MACH_SGI_IP20:
82 		if (ma->ma_addr == 0x1fb80e00)
83 			return (1);
84 		break;
85 	}
86 
87 	return (0);
88 }
89 
90 static void
91 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val)
92 {
93 	bus_space_write_1(sc->sc_rtct, sc->sc_rtch,
94 	    (reg << 2) + sc->sc_offset, val);
95 }
96 
97 static uint8_t
98 readreg(struct dpclock_softc *sc, uint32_t reg)
99 {
100 	return bus_space_read_1(sc->sc_rtct, sc->sc_rtch,
101 	    (reg << 2) + sc->sc_offset);
102 }
103 
104 static void
105 dpclock_attach(device_t parent, device_t self, void *aux)
106 {
107 	struct dpclock_softc *sc = device_private(self);
108 	struct mainbus_attach_args *ma = aux;
109 	int err;
110 
111 	printf("\n");
112 
113 	sc->sc_rtct = normal_memt;
114 	/*
115 	 * All machines have one byte register per word. IP6/IP10 use
116 	 * the MSB, others the LSB.
117 	 */
118 	if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20)
119 		sc->sc_offset = 3;
120 	else
121 		sc->sc_offset = 0;
122 
123 	if ((err = bus_space_map(sc->sc_rtct, ma->ma_addr, 0x1ffff,
124 	    BUS_SPACE_MAP_LINEAR, &sc->sc_rtch)) != 0) {
125 		printf(": unable to map RTC registers, error = %d\n", err);
126 		return;
127 	}
128 
129 	sc->sc_todrch.cookie = sc;
130 	sc->sc_todrch.todr_gettime = dpclock_gettime;
131 	sc->sc_todrch.todr_settime = dpclock_settime;
132 	sc->sc_todrch.todr_setwen = NULL;
133 
134 	todr_attach(&sc->sc_todrch);
135 }
136 
137 /*
138  * Get the time of day, based on the clock's value and/or the base value.
139  */
140 static int
141 dpclock_gettime(struct todr_chip_handle *todrch, struct timeval *tv)
142 {
143 	struct dpclock_softc *sc = (struct dpclock_softc *)todrch->cookie;
144 	struct clock_ymdhms dt;
145 	int s;
146 	u_int8_t i, j;
147 	u_int8_t regs[32];
148 
149 	s = splhigh();
150 	i = readreg(sc, DP8573A_TIMESAVE_CTL);
151 	j = i | DP8573A_TIMESAVE_CTL_EN;
152 	writereg(sc, DP8573A_TIMESAVE_CTL, j);
153 	writereg(sc, DP8573A_TIMESAVE_CTL, i);
154 	splx(s);
155 
156 	for (i = 0; i < 32; i++)
157 		regs[i] = readreg(sc, i);
158 
159 	dt.dt_sec = bcdtobin(regs[DP8573A_SAVE_SEC]);
160 	dt.dt_min = bcdtobin(regs[DP8573A_SAVE_MIN]);
161 
162 	if (regs[DP8573A_RT_MODE] & DP8573A_RT_MODE_1224) {
163 		dt.dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] &
164 						DP8573A_HOUR_12HR_MASK) +
165 		    ((regs[DP8573A_SAVE_HOUR] & DP8573A_RT_MODE_1224) ? 0 : 12);
166 
167 		/*
168 		 * In AM/PM mode, hour range is 01-12, so adding in 12 hours
169 		 * for PM gives us 01-24, whereas we want 00-23, so map hour
170 		 * 24 to hour 0.
171 		 */
172 
173 		if (dt.dt_hour == 24)
174 			dt.dt_hour = 0;
175 	} else {
176 		dt.dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] &
177 							DP8573A_HOUR_24HR_MASK);
178 	}
179 
180 	dt.dt_wday = bcdtobin(regs[DP8573A_DOW]);    /* Not from time saved */
181 	dt.dt_day = bcdtobin(regs[DP8573A_SAVE_DOM]);
182 	dt.dt_mon = bcdtobin(regs[DP8573A_SAVE_MONTH]);
183 	dt.dt_year = FROM_IRIX_YEAR(bcdtobin(regs[DP8573A_YEAR]));
184 
185 	/* simple sanity checks */
186 	if (dt.dt_mon > 12 || dt.dt_day > 31 ||
187 	    dt.dt_hour >= 24 || dt.dt_min >= 60 || dt.dt_sec >= 60)
188 		return (EIO);
189 
190 	tv->tv_sec = (long)clock_ymdhms_to_secs(&dt);
191 	if (tv->tv_sec == -1)
192 		return (ERANGE);
193 	tv->tv_usec = 0;
194 
195 	return (0);
196 }
197 
198 /*
199  * Reset the TODR based on the time value.
200  */
201 static int
202 dpclock_settime(struct todr_chip_handle *todrch, struct timeval *tv)
203 {
204 	struct dpclock_softc *sc = (struct dpclock_softc *)todrch->cookie;
205 	struct clock_ymdhms dt;
206 	int s;
207 	u_int8_t i, j;
208 	u_int8_t regs[32];
209 
210 	clock_secs_to_ymdhms((time_t)(tv->tv_sec + (tv->tv_usec > 500000)),&dt);
211 
212 	s = splhigh();
213 	i = readreg(sc, DP8573A_TIMESAVE_CTL);
214 	j = i | DP8573A_TIMESAVE_CTL_EN;
215 	writereg(sc, DP8573A_TIMESAVE_CTL, j);
216 	writereg(sc, DP8573A_TIMESAVE_CTL, i);
217 	splx(s);
218 
219 	for (i = 0; i < 32; i++)
220 		regs[i] = readreg(sc, i);
221 
222 	regs[DP8573A_SUBSECOND] = 0;
223 	regs[DP8573A_SECOND] = bintobcd(dt.dt_sec);
224 	regs[DP8573A_MINUTE] = bintobcd(dt.dt_min);
225 	regs[DP8573A_HOUR] = bintobcd(dt.dt_hour) & DP8573A_HOUR_24HR_MASK;
226 	regs[DP8573A_DOW] = bintobcd(dt.dt_wday);
227 	regs[DP8573A_DOM] = bintobcd(dt.dt_day);
228 	regs[DP8573A_MONTH] = bintobcd(dt.dt_mon);
229 	regs[DP8573A_YEAR] = bintobcd(TO_IRIX_YEAR(dt.dt_year));
230 
231 	s = splhigh();
232 	i = readreg(sc, DP8573A_RT_MODE);
233 	j = i & ~DP8573A_RT_MODE_CLKSS;
234 	writereg(sc, DP8573A_RT_MODE, j);
235 
236 	for (i = 0; i < 10; i++)
237 		writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
238 
239 	writereg(sc, DP8573A_RT_MODE, i);
240 	splx(s);
241 
242 	return (0);
243 }
244