xref: /netbsd-src/sys/arch/sbmips/include/intr.h (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /* $NetBSD: intr.h,v 1.3 2003/10/25 15:52:38 simonb Exp $ */
2 
3 /*
4  * Copyright 2000, 2001
5  * Broadcom Corporation. All rights reserved.
6  *
7  * This software is furnished under license and may be used and copied only
8  * in accordance with the following terms and conditions.  Subject to these
9  * conditions, you may download, copy, install, use, modify and distribute
10  * modified or unmodified copies of this software in source and/or binary
11  * form. No title or ownership is transferred hereby.
12  *
13  * 1) Any source code used, modified or distributed must reproduce and
14  *    retain this copyright notice and list of conditions as they appear in
15  *    the source file.
16  *
17  * 2) No right is granted to use any trade name, trademark, or logo of
18  *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
19  *    used to endorse or promote products derived from this software
20  *    without the prior written permission of Broadcom Corporation.
21  *
22  * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
23  *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
24  *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
25  *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
26  *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
27  *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30  *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31  *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32  *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef _SBMIPS_INTR_H_
36 #define	_SBMIPS_INTR_H_
37 
38 #include <machine/systemsw.h>
39 
40 /* Interrupt levels */
41 #define	IPL_SERIAL	0
42 #define	IPL_STATCLOCK	1
43 #define	IPL_CLOCK	2
44 #define	IPL_BIO		3
45 #define	IPL_NET		4
46 #define	IPL_TTY		5
47 #define	_NIPL		6
48 
49 #define	IPL_SOFTSERIAL	1000
50 #define	IPL_SOFTNET	1001
51 #define	IPL_SOFTCLOCK	1002
52 
53 #define	_IMR_SOFT	(MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1)
54 #define	_IMR_VM		(_IMR_SOFT | MIPS_INT_MASK_0)
55 #define	_IMR_SCHED	(_IMR_VM | MIPS_INT_MASK_1 | MIPS_INT_MASK_5)
56 #define	_IMR_SERIAL	(_IMR_SCHED | MIPS_INT_MASK_2)
57 #define	_IMR_HIGH	(MIPS_INT_MASK)
58 
59 #define	splbio()		_splraise(_IMR_VM)
60 #define	splclock()		_splraise(_IMR_SCHED)
61 #define	splhigh()		_splraise(_IMR_HIGH)
62 #define	spllock()		splhigh()
63 #define	splvm()			_splraise(_IMR_VM)
64 #define	splnet()		_splraise(_IMR_VM)
65 #define	splsched()		_splraise(_IMR_SCHED)
66 #define	splserial()		_splraise(_IMR_SERIAL)
67 #define	splsoftclock()		_splraise(_IMR_SOFT)
68 #define	splsoftnet()		_splraise(_IMR_SOFT)
69 #define	splsoftserial()		_splraise(_IMR_SOFT)
70 #define	splstatclock()		_splraise(_IMR_SCHED)
71 #define	spltty()		_splraise(_IMR_VM)
72 
73 #define	spl0()			_spllower(0)
74 #define	spllowersoftclock()	_spllower(_IMR_SOFT)
75 #define	splx(s)			_splset(s)
76 
77 #define	__GENERIC_SOFT_INTERRUPTS
78 
79 void		*softintr_establish(int level, void (*fun)(void *), void *arg);
80 void		softintr_disestablish(void *cookie);
81 void		softintr_schedule(void *cookie);
82 
83 /* for interrupt dispatch code */
84 void		dosoftints(void);
85 
86 /* XXX backward-compat */
87 void		setsoftclock(void);
88 void		setsoftnet(void);
89 
90 extern int		_splraise(int);
91 extern int		_spllower(int);
92 extern int		_splset(int);
93 extern int		_splget(void);
94 extern void		_splnone(void);
95 extern void		_setsoftintr(int);
96 extern void		_clrsoftintr(int);
97 
98 #endif /* _SBMIPS_INTR_H_ */
99