1 /* $NetBSD: siisata.c,v 1.5 2012/01/22 13:08:17 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 34 #include <lib/libsa/stand.h> 35 36 #include "globals.h" 37 38 /* 39 * - no vtophys() translation, vaddr_t == paddr_t. 40 */ 41 #define CSR_READ_4(r) in32rb(r) 42 #define CSR_WRITE_4(r,v) out32rb(r,v) 43 44 static int satapresense(struct dkdev_ata *, int); 45 46 static uint32_t pciiobase = PCI_XIOBASE; 47 48 int 49 siisata_match(unsigned tag, void *data) 50 { 51 unsigned v; 52 53 v = pcicfgread(tag, PCI_ID_REG); 54 switch (v) { 55 case PCI_DEVICE(0x1095, 0x3112): /* SiI 3112 SATALink */ 56 case PCI_DEVICE(0x1095, 0x3512): /* 3512 SATALink */ 57 case PCI_DEVICE(0x1095, 0x3114): /* SiI 3114 SATALink */ 58 return 1; 59 } 60 return 0; 61 } 62 63 void * 64 siisata_init(unsigned tag, void *data) 65 { 66 unsigned idreg; 67 int n, nchan, retries/*waitforspinup*/; 68 struct dkdev_ata *l; 69 70 l = alloc(sizeof(struct dkdev_ata)); 71 memset(l, 0, sizeof(struct dkdev_ata)); 72 l->iobuf = allocaligned(512, 16); 73 l->tag = tag; 74 75 idreg = pcicfgread(tag, PCI_ID_REG); 76 l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01); 77 l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01); 78 l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01); 79 l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01); 80 l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01); 81 l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff; 82 83 if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) { 84 /* 3112/3512 */ 85 l->chan[0].cmd = l->bar[0]; 86 l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02; 87 l->chan[0].dma = l->bar[4] + 0x0; 88 l->chan[1].cmd = l->bar[2]; 89 l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02; 90 l->chan[1].dma = l->bar[4] + 0x8; 91 nchan = 2; 92 } 93 else { 94 /* 3114 - assume BA5 access is possible XXX */ 95 l->chan[0].cmd = l->bar[5] + 0x080; 96 l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02; 97 l->chan[1].cmd = l->bar[5] + 0x0c0; 98 l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02; 99 l->chan[2].cmd = l->bar[5] + 0x280; 100 l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02; 101 l->chan[3].cmd = l->bar[5] + 0x2c0; 102 l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02; 103 nchan = 4; 104 } 105 106 /* configure PIO transfer mode */ 107 pcicfgwrite(tag, 0x80, 0x00); 108 pcicfgwrite(tag, 0x84, 0x00); 109 110 for (n = 0; n < nchan; n++) { 111 l->presense[n] = satapresense(l, n); 112 if (l->presense[n] == 0) { 113 DPRINTF(("port %d not present\n", n)); 114 l->presense[n] = 0; 115 continue; 116 } 117 if (atachkpwr(l, n) != ATA_PWR_ACTIVE) { 118 /* drive is probably sleeping, wake it up */ 119 for (retries = 0; retries < 10; retries++) { 120 wakeup_drive(l, n); 121 DPRINTF(("port %d spinning up...\n", n)); 122 delay(1000 * 1000); 123 l->presense[n] = perform_atareset(l, n); 124 if (atachkpwr(l, n) == ATA_PWR_ACTIVE) 125 break; 126 } 127 } else { 128 /* check to see whether soft reset works */ 129 DPRINTF(("port %d active\n", n)); 130 for (retries = 0; retries < 10; retries++) { 131 l->presense[n] = perform_atareset(l, n); 132 if (l->presense[n] != 0) 133 break; 134 DPRINTF(("port %d cold-starting...\n", n)); 135 delay(1000 * 1000); 136 } 137 } 138 139 if (l->presense[n]) 140 printf("port %d present\n", n); 141 } 142 return l; 143 } 144 145 static int 146 satapresense(struct dkdev_ata *l, int n) 147 { 148 #define VND_CH(n) (((n&02)<<8)+((n&01)<<7)) 149 #define VND_SC(n) (0x100+VND_CH(n)) 150 #define VND_SS(n) (0x104+VND_CH(n)) 151 152 uint32_t sc = l->bar[5] + VND_SC(n); 153 uint32_t ss = l->bar[5] + VND_SS(n); 154 unsigned val; 155 156 val = (00 << 4) | (03 << 8); /* any speed, no pwrmgt */ 157 CSR_WRITE_4(sc, val | 01); /* perform init */ 158 delay(50 * 1000); 159 CSR_WRITE_4(sc, val); 160 delay(50 * 1000); 161 val = CSR_READ_4(ss); /* has completed */ 162 return ((val & 03) == 03); /* active drive found */ 163 } 164