1 /* $NetBSD: rge.c,v 1.7 2012/12/25 17:07:06 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 34 #include <netinet/in.h> 35 #include <netinet/in_systm.h> 36 37 #include <lib/libsa/stand.h> 38 #include <lib/libsa/net.h> 39 40 #include "globals.h" 41 42 /* 43 * - reverse endian access every CSR. 44 * - no vtophys() translation, vaddr_t == paddr_t. 45 * - PIPT writeback cache aware. 46 */ 47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) 48 #define CSR_READ_1(l, r) in8((l)->csr+(r)) 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 53 #define VTOPHYS(va) (uint32_t)(va) 54 #define DEVTOV(pa) (uint32_t)(pa) 55 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 56 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 57 #define DELAY(n) delay(n) 58 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 59 60 struct desc { 61 uint32_t xd0, xd1, xd2, xd3; 62 }; 63 #define T0_OWN 0x80000000 /* loaded for HW to send */ 64 #define T0_EOR 0x40000000 /* end of ring */ 65 #define T0_FS 0x20000000 /* first descriptor */ 66 #define T0_LS 0x10000000 /* last descriptor */ 67 #define T0_FRMASK 0x0000ffff 68 69 #define R0_OWN 0x80000000 /* empty for HW to load anew */ 70 #define R0_EOR 0x40000000 /* end mark to form a ring */ 71 #define R0_BUFLEN 0x00003ff8 /* max frag. size to receive */ 72 #define R0_FS 0x20000000 /* start of frame */ 73 #define R0_LS 0x10000000 /* end of frame */ 74 #define R0_RES 0x00200000 /* Rx error summary */ 75 #define R0_RUNT 0x00100000 /* runt frame received */ 76 #define R0_CRC 0x00080000 /* CRC error found */ 77 #define R0_FRMASK 0x00003fff /* 13:0 frame length */ 78 79 #define RGE_IDR0 0x00 /* MAC address [0] */ 80 #define RGE_IDR1 0x01 /* MAC address [1] */ 81 #define RGE_IDR2 0x02 /* MAC address [2] */ 82 #define RGE_IDR3 0x03 /* MAC address [3] */ 83 #define RGE_IDR4 0x04 /* MAC address [4] */ 84 #define RGE_IDR5 0x05 /* MAC address [5] */ 85 #define RGE_TNPDS 0x20 /* Tx descriptor base paddr */ 86 #define RGE_THPDS 0x28 /* high pro. Tx des. base paddr */ 87 #define RGE_CR 0x37 /* command */ 88 #define CR_RESET (1U << 4) /* reset S1C */ 89 #define CR_RXEN (1U << 3) /* Rx enable */ 90 #define CR_TXEN (1U << 2) /* Tx enable */ 91 #define RGE_TPPOLL 0x38 /* activate desc polling */ 92 #define RGE_IMR 0x3c /* interrupt mask */ 93 #define RGE_ISR 0x3e /* interrupt status */ 94 #define RGE_TCR 0x40 /* Tx control */ 95 #define TCR_MAXDMA 0x0700 /* 10:8 Tx DMA burst size */ 96 #define RGE_RCR 0x44 /* Rx control */ 97 #define RCR_RXTFH 0xe000 /* 15:13 Rx FIFO threshold */ 98 #define RCR_MAXDMA 0x0700 /* 10:8 Rx DMA burst size */ 99 #define RCR_AE (1U << 5) /* accept error frame */ 100 #define RCR_RE (1U << 4) /* accept runt frame */ 101 #define RCR_AB (1U << 3) /* accept broadcast frame */ 102 #define RCR_AM (1U << 2) /* accept multicast frame */ 103 #define RCR_APM (1U << 1) /* accept unicast frame */ 104 #define RCR_AAP (1U << 0) /* promiscuous */ 105 #define RGE_EECMD 0x50 /* EEPROM command register */ 106 #define EECMD_LOCK 0x00 107 #define EECMD_UNLOCK 0xc0 108 #define RGE_PHYAR 0x60 /* PHY access */ 109 #define RGE_PHYSR 0x6c /* PHY status */ 110 #define RGE_RMS 0xda /* Rx maximum frame size */ 111 #define RGE_RDSAR 0xe4 /* Rx descriptor base paddr */ 112 #define RGE_ETTHR 0xec /* Tx threshold */ 113 114 #define FRAMESIZE 1536 115 116 struct local { 117 struct desc txd[2]; /* 256B align */ 118 uint8_t _hole0[256 - 2 * sizeof(struct desc)]; 119 struct desc rxd[2]; /* 256B align */ 120 uint8_t _hole1[256 - 2 * sizeof(struct desc)]; 121 uint8_t rxstore[2][FRAMESIZE]; 122 unsigned csr, tx, rx; 123 unsigned phy, bmsr, anlpar; 124 unsigned tcr, rcr; 125 }; 126 127 static int mii_read(struct local *, int, int); 128 static void mii_write(struct local *, int, int, int); 129 static void mii_initphy(struct local *); 130 static void mii_dealan(struct local *, unsigned); 131 132 int 133 rge_match(unsigned tag, void *data) 134 { 135 unsigned v; 136 137 v = pcicfgread(tag, PCI_ID_REG); 138 switch (v) { 139 case PCI_DEVICE(0x10ec, 0x8167): 140 case PCI_DEVICE(0x10ec, 0x8169): 141 return 1; 142 } 143 return 0; 144 } 145 146 void * 147 rge_init(unsigned tag, void *data) 148 { 149 unsigned val; 150 struct local *l; 151 struct desc *txd, *rxd; 152 uint32_t reg; 153 uint8_t *en; 154 155 l = ALLOC(struct local, 256); /* desc alignment */ 156 memset(l, 0, sizeof(struct local)); 157 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */ 158 159 CSR_WRITE_1(l, RGE_CR, CR_RESET); 160 do { 161 val = CSR_READ_1(l, RGE_CR); 162 } while (val & CR_RESET); 163 164 mii_initphy(l); 165 en = data; 166 167 if (brdtype == BRD_QNAPTS) { 168 /* read the MAC from flash and write it into the ID-Regs */ 169 read_mac_from_flash(en); 170 171 CSR_WRITE_1(l, RGE_EECMD, EECMD_UNLOCK); 172 reg = en[0] | (en[1] << 8) | (en[2] << 16) | (en[3] << 24); 173 CSR_WRITE_4(l, RGE_IDR0, reg); 174 reg = en[4] | (en[5] << 8); 175 CSR_WRITE_4(l, RGE_IDR4, reg); 176 CSR_WRITE_1(l, RGE_EECMD, EECMD_LOCK); 177 } else { 178 /* pretent the ID-Regs have the correct address */ 179 en[0] = CSR_READ_1(l, RGE_IDR0); 180 en[1] = CSR_READ_1(l, RGE_IDR1); 181 en[2] = CSR_READ_1(l, RGE_IDR2); 182 en[3] = CSR_READ_1(l, RGE_IDR3); 183 en[4] = CSR_READ_1(l, RGE_IDR4); 184 en[5] = CSR_READ_1(l, RGE_IDR5); 185 } 186 187 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 188 en[0], en[1], en[2], en[3], en[4], en[5]); 189 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 190 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 191 192 mii_dealan(l, 5); 193 194 /* speed and duplexity can be seen in PHYSR */ 195 val = CSR_READ_1(l, RGE_PHYSR); 196 if (val & (1U << 4)) 197 printf("1000Mbps"); 198 if (val & (1U << 3)) 199 printf("100Mbps"); 200 if (val & (1U << 2)) 201 printf("10Mbps"); 202 if (val & (1U << 0)) 203 printf("-FDX"); 204 printf("\n"); 205 206 txd = &l->txd[0]; 207 txd[1].xd0 = htole32(T0_EOR); 208 rxd = &l->rxd[0]; 209 rxd[0].xd0 = htole32(R0_OWN | FRAMESIZE); 210 rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0])); 211 rxd[1].xd0 = htole32(R0_OWN | R0_EOR | FRAMESIZE); 212 rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1])); 213 wbinv(l, sizeof(struct local)); 214 l->tx = l->rx = 0; 215 216 l->tcr = (03 << 24) | (07 << 8); 217 l->rcr = (07 << 13) | (07 << 8) | RCR_APM; 218 CSR_WRITE_1(l, RGE_CR, CR_TXEN | CR_RXEN); 219 CSR_WRITE_1(l, RGE_ETTHR, 0x3f); 220 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE); 221 CSR_WRITE_4(l, RGE_TCR, l->tcr); 222 CSR_WRITE_4(l, RGE_RCR, l->rcr); 223 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd)); 224 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd)); 225 CSR_WRITE_4(l, RGE_TNPDS + 4, 0); 226 CSR_WRITE_4(l, RGE_RDSAR + 4, 0); 227 CSR_WRITE_2(l, RGE_ISR, ~0); 228 CSR_WRITE_2(l, RGE_IMR, 0); 229 return l; 230 } 231 232 int 233 rge_send(void *dev, char *buf, unsigned len) 234 { 235 struct local *l = dev; 236 volatile struct desc *txd; 237 unsigned loop, ret; 238 239 ret = len; 240 if (len < 60) { 241 memset(buf + len, 0, 60 - len); 242 len = 60; /* RTL does not stretch <60 Tx frame */ 243 } 244 wbinv(buf, len); 245 txd = &l->txd[l->tx]; 246 txd->xd2 = htole32(VTOPHYS(buf)); 247 txd->xd0 &= htole32(T0_EOR); 248 txd->xd0 |= htole32(T0_OWN | T0_FS | T0_LS | (len & T0_FRMASK)); 249 wbinv(txd, sizeof(struct desc)); 250 CSR_WRITE_1(l, RGE_TPPOLL, 0x40); 251 loop = 100; 252 do { 253 if ((le32toh(txd->xd0) & T0_OWN) == 0) 254 goto done; 255 DELAY(10); 256 inv(txd, sizeof(struct desc)); 257 } while (--loop > 0); 258 printf("xmit failed\n"); 259 return -1; 260 done: 261 l->tx ^= 1; 262 return ret; 263 } 264 265 int 266 rge_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 267 { 268 struct local *l = dev; 269 volatile struct desc *rxd; 270 unsigned bound, rxstat, len; 271 uint8_t *ptr; 272 273 bound = 1000 * timo; 274 #if 0 275 printf("recving with %u sec. timeout\n", timo); 276 #endif 277 again: 278 rxd = &l->rxd[l->rx]; 279 do { 280 inv(rxd, sizeof(struct desc)); 281 rxstat = le32toh(rxd->xd0); 282 if ((rxstat & R0_OWN) == 0) 283 goto gotone; 284 DELAY(1000); /* 1 milli second */ 285 } while (--bound > 0); 286 errno = 0; 287 return -1; 288 gotone: 289 if (rxstat & R0_RES) { 290 rxd->xd0 &= htole32(R0_EOR); 291 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE); 292 wbinv(rxd, sizeof(struct desc)); 293 l->rx ^= 1; 294 goto again; 295 } 296 len = rxstat & R0_FRMASK; 297 if (len > maxlen) 298 len = maxlen; 299 ptr = l->rxstore[l->rx]; 300 inv(ptr, len); 301 memcpy(buf, ptr, len); 302 rxd->xd0 &= htole32(R0_EOR); 303 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE); 304 wbinv(rxd, sizeof(struct desc)); 305 l->rx ^= 1; 306 return len; 307 } 308 309 static int 310 mii_read(struct local *l, int phy, int reg) 311 { 312 unsigned v; 313 314 v = reg << 16; 315 CSR_WRITE_4(l, RGE_PHYAR, v); 316 DELAY(1000); 317 do { 318 DELAY(100); 319 v = CSR_READ_4(l, RGE_PHYAR); 320 } while ((v & (1U << 31)) == 0); /* wait for 0 -> 1 */ 321 return v & 0xffff; 322 } 323 324 static void 325 mii_write(struct local *l, int phy, int reg, int data) 326 { 327 unsigned v; 328 329 v = (reg << 16) | (data & 0xffff) | (1U << 31); 330 CSR_WRITE_4(l, RGE_PHYAR, v); 331 DELAY(1000); 332 do { 333 DELAY(100); 334 v = CSR_READ_4(l, RGE_PHYAR); 335 } while (v & (1U << 31)); /* wait for 1 -> 0 */ 336 } 337 338 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 339 #define BMCR_RESET 0x8000 /* reset */ 340 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 341 #define BMCR_ISO 0x0400 /* isolate */ 342 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 343 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 344 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 345 #define BMSR_LINK 0x0004 /* Link status */ 346 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 347 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 348 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 349 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 350 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 351 #define ANAR_10 0x0020 /* local device supports 10bT */ 352 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 353 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 354 #define MII_GTCR 0x09 /* 1000baseT control */ 355 #define GANA_1000TFDX 0x0200 /* advertise 1000baseT FDX */ 356 #define GANA_1000THDX 0x0100 /* advertise 1000baseT HDX */ 357 #define MII_GTSR 0x0a /* 1000baseT status */ 358 #define GLPA_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 359 #define GLPA_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 360 #define GLPA_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ 361 362 static void 363 mii_initphy(struct local *l) 364 { 365 int bound, ctl, phy, sts; 366 367 phy = 7; /* internal rgephy, always at 7 */ 368 ctl = mii_read(l, phy, MII_BMCR); 369 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 370 bound = 100; 371 do { 372 DELAY(10); 373 ctl = mii_read(l, phy, MII_BMCR); 374 if (ctl == 0xffff) { 375 printf("MII: PHY %d has died after reset\n", phy); 376 return; 377 } 378 } while (bound-- > 0 && (ctl & BMCR_RESET)); 379 if (bound == 0) { 380 printf("PHY %d reset failed\n", phy); 381 } 382 ctl &= ~BMCR_ISO; 383 mii_write(l, phy, MII_BMCR, ctl); 384 sts = mii_read(l, phy, MII_BMSR) | 385 mii_read(l, phy, MII_BMSR); /* read twice */ 386 l->phy = phy; 387 l->bmsr = sts; 388 } 389 390 void 391 mii_dealan(struct local *l, unsigned timo) 392 { 393 unsigned anar, gtcr, bound; 394 395 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 396 anar |= ANAR_FC; 397 gtcr = GANA_1000TFDX | GANA_1000THDX; 398 mii_write(l, l->phy, MII_ANAR, anar); 399 mii_write(l, l->phy, MII_GTCR, gtcr); 400 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 401 l->anlpar = 0; 402 bound = getsecs() + timo; 403 do { 404 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 405 mii_read(l, l->phy, MII_BMSR); /* read twice */ 406 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 407 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 408 break; 409 } 410 DELAY(10 * 1000); 411 } while (getsecs() < bound); 412 return; 413 } 414