1/* $NetBSD: entry.S,v 1.1 2011/01/23 01:05:30 nisimura Exp $ */ 2 3#include <powerpc/psl.h> 4#include <powerpc/spr.h> 5#include <powerpc/oea/spr.h> 6#include <powerpc/oea/bat.h> 7#include <powerpc/oea/hid.h> 8 9 .text 10 .globl _start 11_start: 12 mr 30,3 13 mr 31,4 14 mfspr 11,SPR_HID0 15 andi. 0,11,HID0_DCE 16 ori 11,11,HID0_ICE 17 ori 8,11,HID0_ICFI 18 bne 1f /* don't invalidate the D-cache */ 19 ori 8,8,HID0_DCFI /* unless it wasn't enabled */ 201: 21 mfmsr 0 22 andi. 0,0,PSL_DR 23 beq 2f 24 lis 5, 0xfec00000@ha /* CONFIG_ADDR of PCI */ 25 lis 6, 0xfee00000@ha /* CONFIG_DATA of PCI */ 26 mfspr 3,SPR_DBAT0U 27 mfspr 4,SPR_DBAT0L 28 bl dbat_sanity_check 29 beq 3f 30 mfspr 3,SPR_DBAT1U 31 mfspr 4,SPR_DBAT1L 32 bl dbat_sanity_check 33 beq 3f 34 mfspr 3,SPR_DBAT2U 35 mfspr 4,SPR_DBAT2L 36 bl dbat_sanity_check 37 beq 3f 38 mfspr 3,SPR_DBAT3U 39 mfspr 4,SPR_DBAT3L 40 bl dbat_sanity_check 41 beq 3f 42 432: /* Disable D-cache */ 44 li 0,HID0_DCE 45 andc 11,11,0 46 b 4f 47 483: /* Enable D-cache */ 49 ori 11,11,HID0_DCE 50 514: 52 lis 1,BAT123@ha 53 addi 1,1,BAT123@l 54 lwz 3,0(1) 55 lwz 4,4(1) 56 mtdbatl 1,3 57 mtdbatu 1,4 58 lwz 3,8(1) 59 lwz 4,12(1) 60 mtdbatl 2,3 61 mtdbatu 2,4 62 lwz 3,16(1) 63 lwz 4,20(1) 64 mtdbatl 3,3 65 mtdbatu 3,4 66 67 sync 68 mtspr SPR_HID0,8 /* enable and invalidate caches */ 69 sync 70 mtspr SPR_HID0,11 /* enable caches */ 71 sync 72 isync 73 74 /* make sure .bss gets zeroed. */ 75 li 0,0 76 lis 8,edata@ha 77 addi 8,8,edata@l 78 lis 9,end@ha 79 addi 9,9,end@l 805: cmpw 0,8,9 /* edata & end are >= word aligned */ 81 bge 6f 82 stw 0,0(8) 83 addi 8,8,4 84 b 5b 85 866: 87 /* prepare stack at +1MB from _start. */ 88 lis 1,_start@h 89 ori 1,1,_start@l 90 addis 1,1,0x10 91 addi 1,1,-4 92 93 bl brdsetup 94 mr 3,30 95 mr 4,31 96 bl main 97 98hang: b hang 99 /* NOTREACHED */ 100 101dbat_sanity_check: 102 andi. 0,3,BAT_Vs 103 beq 2f 104 andi. 0,4,BAT_I|BAT_PP_RW 105 cmpwi 0,0,BAT_I|BAT_PP_RW 106 bnelr 107 rlwinm 0,3,15,4,14 108 andis. 3,3,0xfffe0000@ha /* BAT_EPI */ 109 andis. 4,4,BAT_RPN@ha 110 cmplw 0,3,4 111 bnelr 112 add 4,4,0 113 oris 4,4,0x0001ffff@ha 114 ori 4,4,0x0001ffff@l 115 cmplw 0,3,5 116 bgt 1f 117 cmplw 0,5,4 118 bgt 1f 119 li 5,0 1201: cmplw 0,3,6 121 bgt 2f 122 cmplw 0,6,4 123 bgt 2f 124 li 6,0 1252: cmplw 0,5,6 126 blr 127 128/* 129 * run(startsym, endsym, howto, bootinfo, entry) 130 */ 131 .globl run 132run: 133 mtctr 7 /* hat trick jump to entry point */ 134 bctr 135 136/* 137 * reverse endian access to mimic outw/outl/inw/inl 138 */ 139 .globl out16rb 140 .globl iohtole16 141out16rb: 142iohtole16: 143 sthbrx 4,0,3 144 eieio 145 blr 146 147 .globl out32rb 148 .globl iohtole32 149out32rb: 150iohtole32: 151 stwbrx 4,0,3 152 eieio 153 blr 154 155 .global in16rb 156 .global iole16toh 157in16rb: 158iole16toh: 159 lhbrx 3,0,3 160 eieio 161 blr 162 163 .global in32rb 164 .global iole32toh 165in32rb: 166iole32toh: 167 lwbrx 3,0,3 168 eieio 169 blr 170 171 .data 172#define xBATL(pa, wimg, pp) \ 173 ((pa) | (wimg) | (pp)) 174#define xBATU(va, len, v) \ 175 ((va) | ((len) & BAT_BL) | ((v) & BAT_V)) 176BAT123: 177 .long xBATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW) 178 .long xBATU(0x80000000, BAT_BL_256M, BAT_Vs) 179 .long xBATL(0xfc000000, BAT_I|BAT_G, BAT_PP_RW) 180 .long xBATU(0xfc000000, BAT_BL_64M, BAT_Vs) 181 .long 0 182 .long 0 183