1*eeda5809Smatt /* $NetBSD: clock.c,v 1.2 2010/03/02 21:52:32 matt Exp $ */
268fe5b6fSgarbled
368fe5b6fSgarbled /*
468fe5b6fSgarbled * Copyright (C) 1995, 1996 Wolfgang Solfrank.
568fe5b6fSgarbled * Copyright (C) 1995, 1996 TooLs GmbH.
668fe5b6fSgarbled * All rights reserved.
768fe5b6fSgarbled *
868fe5b6fSgarbled * Redistribution and use in source and binary forms, with or without
968fe5b6fSgarbled * modification, are permitted provided that the following conditions
1068fe5b6fSgarbled * are met:
1168fe5b6fSgarbled * 1. Redistributions of source code must retain the above copyright
1268fe5b6fSgarbled * notice, this list of conditions and the following disclaimer.
1368fe5b6fSgarbled * 2. Redistributions in binary form must reproduce the above copyright
1468fe5b6fSgarbled * notice, this list of conditions and the following disclaimer in the
1568fe5b6fSgarbled * documentation and/or other materials provided with the distribution.
1668fe5b6fSgarbled * 3. All advertising materials mentioning features or use of this software
1768fe5b6fSgarbled * must display the following acknowledgement:
1868fe5b6fSgarbled * This product includes software developed by TooLs GmbH.
1968fe5b6fSgarbled * 4. The name of TooLs GmbH may not be used to endorse or promote products
2068fe5b6fSgarbled * derived from this software without specific prior written permission.
2168fe5b6fSgarbled *
2268fe5b6fSgarbled * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
2368fe5b6fSgarbled * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
2468fe5b6fSgarbled * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
2568fe5b6fSgarbled * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2668fe5b6fSgarbled * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
2768fe5b6fSgarbled * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
2868fe5b6fSgarbled * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
2968fe5b6fSgarbled * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
3068fe5b6fSgarbled * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
3168fe5b6fSgarbled * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3268fe5b6fSgarbled */
3368fe5b6fSgarbled
3468fe5b6fSgarbled #include <lib/libsa/stand.h>
3568fe5b6fSgarbled #include <dev/isa/isareg.h>
3668fe5b6fSgarbled #include <dev/ic/i8253reg.h>
3768fe5b6fSgarbled #include <powerpc/spr.h>
38*eeda5809Smatt #include <powerpc/oea/spr.h>
3968fe5b6fSgarbled
4068fe5b6fSgarbled #include "boot.h"
4168fe5b6fSgarbled
4268fe5b6fSgarbled u_long ns_per_tick = NS_PER_TICK;
4368fe5b6fSgarbled
4468fe5b6fSgarbled static inline u_quad_t mftb(void);
4568fe5b6fSgarbled static inline void mfrtc(u_long *, u_long *);
4668fe5b6fSgarbled
4768fe5b6fSgarbled static inline u_quad_t
mftb(void)4868fe5b6fSgarbled mftb(void)
4968fe5b6fSgarbled {
5068fe5b6fSgarbled u_long scratch;
5168fe5b6fSgarbled u_quad_t tb;
5268fe5b6fSgarbled
5368fe5b6fSgarbled __asm volatile ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b"
5468fe5b6fSgarbled : "=r"(tb), "=r"(scratch));
5568fe5b6fSgarbled return (tb);
5668fe5b6fSgarbled }
5768fe5b6fSgarbled
5868fe5b6fSgarbled static inline void
mfrtc(u_long * up,u_long * lp)5968fe5b6fSgarbled mfrtc(u_long *up, u_long *lp)
6068fe5b6fSgarbled {
6168fe5b6fSgarbled u_long scratch;
6268fe5b6fSgarbled
6368fe5b6fSgarbled __asm volatile ("1: mfspr %0,%3; mfspr %1,%4; mfspr %2,%3;"
6468fe5b6fSgarbled "cmpw %0,%2; bne 1b"
6568fe5b6fSgarbled : "=r"(*up), "=r"(*lp), "=r"(scratch)
6668fe5b6fSgarbled : "n"(SPR_RTCU_R), "n"(SPR_RTCL_R));
6768fe5b6fSgarbled }
6868fe5b6fSgarbled
6968fe5b6fSgarbled /*
7068fe5b6fSgarbled * Wait for about n microseconds (at least!).
7168fe5b6fSgarbled */
7268fe5b6fSgarbled void
delay(u_int n)7368fe5b6fSgarbled delay(u_int n)
7468fe5b6fSgarbled {
7568fe5b6fSgarbled u_quad_t tb;
7668fe5b6fSgarbled u_long tbh, tbl, scratch;
7768fe5b6fSgarbled unsigned int cpuvers;
7868fe5b6fSgarbled
7968fe5b6fSgarbled __asm volatile ("mfpvr %0" : "=r"(cpuvers));
8068fe5b6fSgarbled cpuvers >>= 16;
8168fe5b6fSgarbled /*cpuvers = MPC601; for now */
8268fe5b6fSgarbled
8368fe5b6fSgarbled if (cpuvers == MPC601) {
8468fe5b6fSgarbled mfrtc(&tbh, &tbl);
8568fe5b6fSgarbled while (n >= 1000000) {
8668fe5b6fSgarbled tbh++;
8768fe5b6fSgarbled n -= 1000000;
8868fe5b6fSgarbled }
8968fe5b6fSgarbled tbl += n * 1000;
9068fe5b6fSgarbled if (tbl >= 1000000000) {
9168fe5b6fSgarbled tbh++;
9268fe5b6fSgarbled tbl -= 1000000000;
9368fe5b6fSgarbled }
9468fe5b6fSgarbled __asm volatile ("1: mfspr %0,%3; cmplw %0,%1; blt 1b; bgt 2f;"
9568fe5b6fSgarbled "mfspr %0,%4; cmplw %0,%2; blt 1b; 2:"
9668fe5b6fSgarbled : "=&r"(scratch)
9768fe5b6fSgarbled : "r"(tbh), "r"(tbl), "n"(SPR_RTCU_R), "n"(SPR_RTCL_R));
9868fe5b6fSgarbled } else {
9968fe5b6fSgarbled tb = mftb();
10068fe5b6fSgarbled tb += (n * 1000 + ns_per_tick - 1) / ns_per_tick;
10168fe5b6fSgarbled tbh = tb >> 32;
10268fe5b6fSgarbled tbl = tb;
10368fe5b6fSgarbled __asm volatile ("1: mftbu %0; cmpw %0,%1; blt 1b; bgt 2f;"
10468fe5b6fSgarbled "mftb %0; cmpw %0,%2; blt 1b; 2:"
10568fe5b6fSgarbled : "=&r"(scratch)
10668fe5b6fSgarbled : "r"(tbh), "r"(tbl));
10768fe5b6fSgarbled }
10868fe5b6fSgarbled }
109