1 /* $NetBSD: sysreg.h,v 1.28 2022/12/03 11:09:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _RISCV_SYSREG_H_ 33 #define _RISCV_SYSREG_H_ 34 35 #ifndef _KERNEL 36 #include <sys/param.h> 37 #endif 38 39 #include <riscv/reg.h> 40 41 #define FCSR_FMASK 0 // no exception bits 42 #define FCSR_FRM __BITS(7, 5) 43 #define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even 44 #define FCSR_FRM_RTZ 0b001 // Round Towards Zero 45 #define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) 46 #define FCSR_FRM_RUP 0b011 // Round UP (+infinity) 47 #define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude 48 #define FCSR_FRM_DYN 0b111 // Dynamic rounding 49 #define FCSR_FFLAGS __BITS(4, 0) // Sticky bits 50 #define FCSR_NV __BIT(4) // iNValid operation 51 #define FCSR_DZ __BIT(3) // Divide by Zero 52 #define FCSR_OF __BIT(2) // OverFlow 53 #define FCSR_UF __BIT(1) // UnderFlow 54 #define FCSR_NX __BIT(0) // iNeXact 55 56 static inline uint32_t 57 riscvreg_fcsr_read(void) 58 { 59 uint32_t __fcsr; 60 __asm("frcsr %0" : "=r"(__fcsr)); 61 return __fcsr; 62 } 63 64 65 static inline uint32_t 66 riscvreg_fcsr_write(uint32_t __new) 67 { 68 uint32_t __old; 69 __asm("fscsr %0, %1" : "=r"(__old) : "r"(__new)); 70 return __old; 71 } 72 73 static inline uint32_t 74 riscvreg_fcsr_read_fflags(void) 75 { 76 uint32_t __old; 77 __asm("frflags %0" : "=r"(__old)); 78 return __SHIFTOUT(__old, FCSR_FFLAGS); 79 } 80 81 static inline uint32_t 82 riscvreg_fcsr_write_fflags(uint32_t __new) 83 { 84 uint32_t __old; 85 __new = __SHIFTIN(__new, FCSR_FFLAGS); 86 __asm("fsflags %0, %1" : "=r"(__old) : "r"(__new)); 87 return __SHIFTOUT(__old, FCSR_FFLAGS); 88 } 89 90 static inline uint32_t 91 riscvreg_fcsr_read_frm(void) 92 { 93 uint32_t __old; 94 __asm("frrm\t%0" : "=r"(__old)); 95 return __SHIFTOUT(__old, FCSR_FRM); 96 } 97 98 static inline uint32_t 99 riscvreg_fcsr_write_frm(uint32_t __new) 100 { 101 uint32_t __old; 102 __new = __SHIFTIN(__new, FCSR_FRM); 103 __asm __volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new)); 104 return __SHIFTOUT(__old, FCSR_FRM); 105 } 106 107 108 #define RISCVREG_READ_INLINE(regname) \ 109 static inline uintptr_t \ 110 csr_##regname##_read(void) \ 111 { \ 112 uintptr_t __rv; \ 113 asm volatile("csrr %0, " #regname : "=r"(__rv) :: "memory"); \ 114 return __rv; \ 115 } 116 117 #define RISCVREG_WRITE_INLINE(regname) \ 118 static inline void \ 119 csr_##regname##_write(uintptr_t __val) \ 120 { \ 121 asm volatile("csrw " #regname ", %0" :: "r"(__val) : "memory"); \ 122 } 123 124 #define RISCVREG_SET_INLINE(regname) \ 125 static inline void \ 126 csr_##regname##_set(uintptr_t __mask) \ 127 { \ 128 if (__builtin_constant_p(__mask) && __mask < 0x20) { \ 129 asm volatile("csrsi " #regname ", %0" :: "i"(__mask) : \ 130 "memory"); \ 131 } else { \ 132 asm volatile("csrs " #regname ", %0" :: "r"(__mask) : \ 133 "memory"); \ 134 } \ 135 } 136 137 #define RISCVREG_CLEAR_INLINE(regname) \ 138 static inline void \ 139 csr_##regname##_clear(uintptr_t __mask) \ 140 { \ 141 if (__builtin_constant_p(__mask) && __mask < 0x20) { \ 142 asm volatile("csrci " #regname ", %0" :: "i"(__mask) : \ 143 "memory"); \ 144 } else { \ 145 asm volatile("csrc " #regname ", %0" :: "r"(__mask) : \ 146 "memory"); \ 147 } \ 148 } 149 150 #define RISCVREG_READ_WRITE_INLINE(regname) \ 151 RISCVREG_READ_INLINE(regname) \ 152 RISCVREG_WRITE_INLINE(regname) 153 #define RISCVREG_SET_CLEAR_INLINE(regname) \ 154 RISCVREG_SET_INLINE(regname) \ 155 RISCVREG_CLEAR_INLINE(regname) 156 #define RISCVREG_READ_SET_CLEAR_INLINE(regname) \ 157 RISCVREG_READ_INLINE(regname) \ 158 RISCVREG_SET_CLEAR_INLINE(regname) 159 #define RISCVREG_READ_WRITE_SET_CLEAR_INLINE(regname) \ 160 RISCVREG_READ_WRITE_INLINE(regname) \ 161 RISCVREG_SET_CLEAR_INLINE(regname) 162 163 /* Supervisor Status Register */ 164 RISCVREG_READ_SET_CLEAR_INLINE(sstatus) // supervisor status register 165 #ifdef _LP64 166 #define SR_WPRI __BITS(62, 34) | __BITS(31, 20) | \ 167 __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ 168 __BIT(0) 169 #define SR_SD __BIT(63) // any of FS or VS or XS dirty 170 /* Bits 62-34 are WPRI */ 171 #define SR_UXL __BITS(33, 32) // U-mode XLEN 172 #define SR_UXL_32 1 // XLEN == 32 173 #define SR_UXL_64 2 // XLEN == 64 174 #define SR_UXL_128 3 // XLEN == 128 175 /* Bits 31-20 are WPRI*/ 176 #else 177 #define SR_WPRI __BITS(30, 20) | \ 178 __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ 179 __BIT(0) 180 #define SR_SD __BIT(31) // any of FS or VS or XS dirty 181 /* Bits 30-20 are WPRI*/ 182 #endif /* _LP64 */ 183 184 /* Both RV32 and RV64 have the bottom 20 bits shared */ 185 #define SR_MXR __BIT(19) // Make eXecutable Readable 186 #define SR_SUM __BIT(18) // permit Supervisor User Memory access 187 /* Bit 17 is WPRI */ 188 #define SR_XS __BITS(16, 15) // Vector extension state 189 #define SR_XS_OFF 0 // All off 190 #define SR_XS_SOME_ON 1 // None dirty or clean, some on 191 #define SR_XS_SOME_CLEAN 2 // None dirty, some clean 192 #define SR_XS_SOME_DIRTY 3 // Some dirty 193 #define SR_FS __BITS(14, 13) // Floating-point unit state 194 #define SR_FS_OFF 0 // Off 195 #define SR_FS_INITIAL 1 // Initial 196 #define SR_FS_CLEAN 2 // Clean 197 #define SR_FS_DIRTY 3 // Dirty 198 /* Bits 12-11 are WPRI */ 199 #define SR_VS __BITS(10, 9) // User-mode extention state 200 #define SR_VS_OFF SR_FS_OFF // Off 201 #define SR_VS_INITIAL SR_FS_INITIAL // Initial 202 #define SR_VS_CLEAN SR_FS_CLEAN // Clean 203 #define SR_VS_DIRTY SR_FS_DIRTY // Dirty 204 #define SR_SPP __BIT(8) // Priv level before supervisor mode 205 /* Bit 7 is WPRI */ 206 #define SR_UBE __BIT(6) // User-mode endianness 207 #define SR_SPIE __BIT(5) // S-Mode interrupts enabled before trap 208 /* Bits 4-2 are WPRI */ 209 #define SR_SIE __BIT(1) // Supervisor mode interrupt enable 210 /* Bit 0 is WPRI */ 211 212 /* Supervisor interrupt registers */ 213 /* ... interrupt pending register (sip) */ 214 RISCVREG_READ_SET_CLEAR_INLINE(sip) // supervisor interrupt pending 215 /* Bit (XLEN-1) - 10 is WIRI */ 216 #define SIP_SEIP __BIT(9) // S-mode interrupt pending 217 /* Bit 8-6 is WIRI */ 218 #define SIP_STIP __BIT(5) // S-mode timer interrupt pending 219 /* Bit 4-2 is WIRI */ 220 #define SIP_SSIP __BIT(1) // S-mode software interrupt pending 221 /* Bit 0 is WIRI */ 222 223 /* ... interrupt-enable register (sie) */ 224 RISCVREG_READ_SET_CLEAR_INLINE(sie) // supervisor interrupt enable 225 /* Bit (XLEN-1) - 10 is WIRI */ 226 #define SIE_SEIE __BIT(9) // S-mode interrupt enable 227 /* Bit 8-6 is WIRI */ 228 #define SIE_STIE __BIT(5) // S-mode timer interrupt enable 229 /* Bit 4-2 is WIRI */ 230 #define SIE_SSIE __BIT(1) // S-mode software interrupt enable 231 /* Bit 0 is WIRI */ 232 233 /* Mask for all interrupts */ 234 #define SIE_IM (SIE_SEI |SIE_STIE | SIE_SSIE) 235 236 #ifdef _LP64 237 #define SR_USER64 (SR_SPIE | SR_UXL_64) // 64-bit U-mode sstatus 238 #define SR_USER32 (SR_SPIE | SR_UXL_32) // 32-bit U-mode sstatus 239 #else 240 #define SR_USER (SR_SPIE) // U-mode sstatus 241 #endif 242 243 // Cause register 244 #define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN - 1)) 245 #define CAUSE_CODE(cause) ((cause) & __BITS(XLEN - 2, 0)) 246 247 // Cause register - exceptions 248 #define CAUSE_FETCH_MISALIGNED 0 249 #define CAUSE_FETCH_ACCESS 1 250 #define CAUSE_ILLEGAL_INSTRUCTION 2 251 #define CAUSE_BREAKPOINT 3 252 #define CAUSE_LOAD_MISALIGNED 4 253 #define CAUSE_LOAD_ACCESS 5 254 #define CAUSE_STORE_MISALIGNED 6 255 #define CAUSE_STORE_ACCESS 7 256 #define CAUSE_USER_ECALL 8 257 #define CAUSE_SYSCALL CAUSE_USER_ECALL /* convenience alias */ 258 #define CAUSE_SUPERVISOR_ECALL 9 259 /* 10 is reserved */ 260 #define CAUSE_MACHINE_ECALL 11 261 #define CAUSE_FETCH_PAGE_FAULT 12 262 #define CAUSE_LOAD_PAGE_FAULT 13 263 /* 14 is Reserved */ 264 #define CAUSE_STORE_PAGE_FAULT 15 265 /* >= 16 is reserved/custom */ 266 267 // Cause register - interrupts 268 #define IRQ_SUPERVISOR_SOFTWARE 1 269 #define IRQ_MACHINE_SOFTWARE 3 270 #define IRQ_SUPERVISOR_TIMER 5 271 #define IRQ_MACHINE_TIMER 7 272 #define IRQ_SUPERVISOR_EXTERNAL 9 273 #define IRQ_MACHINE_EXTERNAL 11 274 275 RISCVREG_READ_INLINE(time) 276 #ifdef _LP64 277 RISCVREG_READ_INLINE(cycle) 278 #else /* !_LP64 */ 279 static inline uint64_t 280 csr_cycle_read(void) 281 { 282 uint32_t __hi0, __hi1, __lo0; 283 do { 284 __asm __volatile( 285 "csrr\t%[__hi0], cycleh" 286 "\n\t" "csrr\t%[__lo0], cycle" 287 "\n\t" "csrr\t%[__hi1], cycleh" 288 : [__hi0] "=r"(__hi0), 289 [__lo0] "=r"(__lo0), 290 [__hi1] "=r"(__hi1)); 291 } while (__hi0 != __hi1); 292 return 293 __SHIFTIN(__hi0, __BITS(63, 32)) | 294 __SHIFTIN(__lo0, __BITS(31, 0)); 295 } 296 #endif /* !_LP64 */ 297 298 #ifdef _LP64 299 #define SATP_MODE __BITS(63, 60) // Translation mode 300 #define SATP_MODE_BARE 0 // No translation or protection 301 /* modes 1-7 reserved for standard use */ 302 #define SATP_MODE_SV39 8 // Page-based 39-bit virt addr 303 #define SATP_MODE_SV48 9 // Page-based 48-bit virt addr 304 #define SATP_MODE_SV57 10 // Page-based 57-bit virt addr 305 #define SATP_MODE_SV64 11 // Page-based 64-bit virt addr 306 /* modes 12-13 reserved for standard use */ 307 /* modes 14-15 designated for custom use */ 308 #define SATP_ASID __BITS(59, 44) // Address Space Identifier 309 #define SATP_PPN __BITS(43, 0) // Physical Page Number 310 #else 311 #define SATP_MODE __BIT(31) // Translation mode 312 #define SATP_MODE_BARE 0 // No translation or protection 313 #define SATP_MODE_SV32 1 // Page-based 32-bit virt addr 314 #define SATP_ASID __BITS(30, 22) // Address Space Identifier 315 #define SATP_PPN __BITS(21, 0) // Physical Page Number 316 #endif 317 318 RISCVREG_READ_WRITE_INLINE(satp) 319 320 /* Fake "ASID" CSR (a field of SATP register) functions */ 321 static inline uint32_t 322 csr_asid_read(void) 323 { 324 uintptr_t satp = csr_satp_read(); 325 return __SHIFTOUT(satp, SATP_ASID); 326 } 327 328 static inline void 329 csr_asid_write(uint32_t asid) 330 { 331 uintptr_t satp = csr_satp_read(); 332 satp &= ~SATP_ASID; 333 satp |= __SHIFTIN(asid, SATP_ASID); 334 csr_satp_write(satp); 335 } 336 337 #endif /* _RISCV_SYSREG_H_ */ 338