1 /* $NetBSD: locore.h,v 1.10 2021/10/05 11:01:49 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _RISCV_LOCORE_H_ 33 #define _RISCV_LOCORE_H_ 34 35 #include <sys/lwp.h> 36 #include <sys/userret.h> 37 38 #include <riscv/reg.h> 39 #include <riscv/sysreg.h> 40 41 struct trapframe { 42 struct reg tf_regs; 43 register_t tf_tval; 44 register_t tf_cause; 45 register_t tf_sr; 46 #define tf_reg tf_regs.r_reg 47 #define tf_pc tf_regs.r_pc 48 #define tf_ra tf_reg[_X_RA] 49 #define tf_sp tf_reg[_X_SP] 50 #define tf_gp tf_reg[_X_GP] 51 #define tf_tp tf_reg[_X_TP] 52 #define tf_t0 tf_reg[_X_T0] 53 #define tf_t1 tf_reg[_X_T1] 54 #define tf_t2 tf_reg[_X_T2] 55 #define tf_s0 tf_reg[_X_S0] 56 #define tf_s1 tf_reg[_X_S1] 57 #define tf_a0 tf_reg[_X_A0] 58 #define tf_a1 tf_reg[_X_A1] 59 #define tf_a2 tf_reg[_X_A2] 60 #define tf_a3 tf_reg[_X_A3] 61 #define tf_a4 tf_reg[_X_A4] 62 #define tf_a5 tf_reg[_X_A5] 63 #define tf_a6 tf_reg[_X_A6] 64 #define tf_a7 tf_reg[_X_A7] 65 #define tf_s2 tf_reg[_X_S2] 66 #define tf_s3 tf_reg[_X_S3] 67 #define tf_s4 tf_reg[_X_S4] 68 #define tf_s5 tf_reg[_X_S5] 69 #define tf_s6 tf_reg[_X_S6] 70 #define tf_s7 tf_reg[_X_S7] 71 #define tf_s8 tf_reg[_X_S8] 72 #define tf_s9 tf_reg[_X_S9] 73 #define tf_s10 tf_reg[_X_S10] 74 #define tf_s11 tf_reg[_X_S11] 75 #define tf_t3 tf_reg[_X_T3] 76 #define tf_t4 tf_reg[_X_T4] 77 #define tf_t5 tf_reg[_X_T5] 78 #define tf_t6 tf_reg[_X_T6] 79 }; 80 81 #ifdef _LP64 82 // For COMPAT_NETBSD32 coredumps 83 struct trapframe32 { 84 struct reg32 tf_regs; 85 register32_t tf_tval; 86 register32_t tf_cause; 87 register32_t tf_sr; 88 }; 89 #endif 90 91 #define FB_A0 0 92 #define FB_RA 1 93 #define FB_SP 2 94 #define FB_GP 3 95 #define FB_S0 4 96 #define FB_S1 5 97 #define FB_S2 6 98 #define FB_S3 7 99 #define FB_S4 8 100 #define FB_S5 9 101 #define FB_S6 10 102 #define FB_S7 11 103 #define FB_S8 12 104 #define FB_S9 13 105 #define FB_S10 14 106 #define FB_S11 15 107 #define FB_MAX 16 108 109 struct faultbuf { 110 register_t fb_reg[FB_MAX]; 111 register_t fb_sr; 112 }; 113 114 CTASSERT(sizeof(label_t) == sizeof(struct faultbuf)); 115 116 struct mainbus_attach_args { 117 const char *maa_name; 118 u_int maa_instance; 119 }; 120 121 #ifdef _KERNEL 122 extern int cpu_printfataltraps; 123 124 #ifdef FPE 125 extern const pcu_ops_t pcu_fpu_ops; 126 #endif 127 128 static inline vaddr_t 129 stack_align(vaddr_t sp) 130 { 131 return sp & ~STACK_ALIGNBYTES; 132 } 133 134 static inline void 135 userret(struct lwp *l) 136 { 137 mi_userret(l); 138 } 139 140 static inline void 141 fpu_load(void) 142 { 143 #ifdef FPE 144 pcu_load(&pcu_fpu_ops); 145 #endif 146 } 147 148 static inline void 149 fpu_save(lwp_t *l) 150 { 151 #ifdef FPE 152 pcu_save(&pcu_fpu_ops, l); 153 #endif 154 } 155 156 static inline void 157 fpu_discard(lwp_t *l) 158 { 159 #ifdef FPE 160 pcu_discard(&pcu_fpu_ops, l, false); 161 #endif 162 } 163 164 static inline void 165 fpu_replace(lwp_t *l) 166 { 167 #ifdef FPE 168 pcu_discard(&pcu_fpu_ops, l, true); 169 #endif 170 } 171 172 static inline bool 173 fpu_valid_p(lwp_t *l) 174 { 175 #ifdef FPE 176 return pcu_valid_p(&pcu_fpu_ops, l); 177 #else 178 return false; 179 #endif 180 } 181 182 void __syncicache(const void *, size_t); 183 184 int cpu_set_onfault(struct faultbuf *, register_t) __returns_twice; 185 void cpu_jump_onfault(struct trapframe *, const struct faultbuf *); 186 187 static inline void 188 cpu_unset_onfault(void) 189 { 190 curlwp->l_md.md_onfault = NULL; 191 } 192 193 static inline struct faultbuf * 194 cpu_disable_onfault(void) 195 { 196 struct faultbuf * const fb = curlwp->l_md.md_onfault; 197 curlwp->l_md.md_onfault = NULL; 198 return fb; 199 } 200 201 static inline void 202 cpu_enable_onfault(struct faultbuf *fb) 203 { 204 curlwp->l_md.md_onfault = fb; 205 } 206 207 void cpu_intr(struct trapframe */*tf*/, register_t /*epc*/, 208 register_t /*status*/, register_t /*cause*/); 209 void cpu_trap(struct trapframe */*tf*/, register_t /*epc*/, 210 register_t /*status*/, register_t /*cause*/, 211 register_t /*badvaddr*/); 212 void cpu_ast(struct trapframe *); 213 void cpu_fast_switchto(struct lwp *, int); 214 215 void cpu_lwp_trampoline(void); 216 217 void * cpu_sendsig_getframe(struct lwp *, int, bool *); 218 219 void init_riscv(vaddr_t, vaddr_t); 220 #endif 221 222 #endif /* _RISCV_LOCORE_H_ */ 223