1 /* $NetBSD: locore.h,v 1.2 2015/03/28 16:13:56 matt Exp $ */ 2 /*- 3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _RISCV_LOCORE_H_ 32 #define _RISCV_LOCORE_H_ 33 34 #include <sys/lwp.h> 35 #include <sys/userret.h> 36 37 #include <riscv/reg.h> 38 #include <riscv/sysreg.h> 39 40 struct trapframe { 41 struct reg tf_regs; 42 register_t tf_badaddr; 43 uint32_t tf_cause; // 32-bit register 44 uint32_t tf_sr; // 32-bit register 45 #define tf_reg tf_regs.r_reg 46 #define tf_pc tf_regs.r_pc 47 #define tf_ra tf_reg[_X_RA] 48 #define tf_sp tf_reg[_X_SP] 49 #define tf_gp tf_reg[_X_GP] 50 #define tf_tp tf_reg[_X_TP] 51 #define tf_t0 tf_reg[_X_T0] 52 #define tf_t1 tf_reg[_X_T1] 53 #define tf_t2 tf_reg[_X_T2] 54 #define tf_s0 tf_reg[_X_S0] 55 #define tf_s1 tf_reg[_X_S1] 56 #define tf_a0 tf_reg[_X_A0] 57 #define tf_a1 tf_reg[_X_A1] 58 #define tf_a2 tf_reg[_X_A2] 59 #define tf_a3 tf_reg[_X_A3] 60 #define tf_a4 tf_reg[_X_A4] 61 #define tf_a5 tf_reg[_X_A5] 62 #define tf_a6 tf_reg[_X_A6] 63 #define tf_a7 tf_reg[_X_A7] 64 #define tf_s2 tf_reg[_X_S2] 65 #define tf_s3 tf_reg[_X_S3] 66 #define tf_s4 tf_reg[_X_S4] 67 #define tf_s5 tf_reg[_X_S5] 68 #define tf_s6 tf_reg[_X_S6] 69 #define tf_s7 tf_reg[_X_S7] 70 #define tf_s8 tf_reg[_X_S8] 71 #define tf_s9 tf_reg[_X_S9] 72 #define tf_s10 tf_reg[_X_S10] 73 #define tf_s11 tf_reg[_X_S11] 74 #define tf_t3 tf_reg[_X_T3] 75 #define tf_t4 tf_reg[_X_T4] 76 #define tf_t5 tf_reg[_X_T5] 77 #define tf_t6 tf_reg[_X_T6] 78 }; 79 80 // For COMPAT_NETBDS32 coredumps 81 struct trapframe32 { 82 struct reg32 tf_regs; 83 register32_t tf_badaddr; 84 uint32_t tf_cause; // 32-bit register 85 uint32_t tf_sr; // 32-bit register 86 }; 87 88 #define FB_A0 0 89 #define FB_RA 1 90 #define FB_SP 2 91 #define FB_GP 3 92 #define FB_S0 4 93 #define FB_S1 5 94 #define FB_S2 6 95 #define FB_S3 7 96 #define FB_S4 8 97 #define FB_S5 9 98 #define FB_S6 10 99 #define FB_S7 11 100 #define FB_S8 12 101 #define FB_S9 13 102 #define FB_S10 14 103 #define FB_S11 15 104 #define FB_MAX 16 105 106 struct faultbuf { 107 register_t fb_reg[FB_MAX]; 108 uint32_t fb_sr; 109 }; 110 111 CTASSERT(sizeof(label_t) == sizeof(struct faultbuf)); 112 113 struct mainbus_attach_args { 114 const char *maa_name; 115 u_int maa_instance; 116 }; 117 118 #ifdef _KERNEL 119 extern int cpu_printfataltraps; 120 extern const pcu_ops_t pcu_fpu_ops; 121 122 static inline vaddr_t 123 stack_align(vaddr_t sp) 124 { 125 return sp & ~STACK_ALIGNBYTES; 126 } 127 128 static inline void 129 userret(struct lwp *l) 130 { 131 mi_userret(l); 132 } 133 134 static inline void 135 fpu_load(void) 136 { 137 pcu_load(&pcu_fpu_ops); 138 } 139 140 static inline void 141 fpu_save(void) 142 { 143 pcu_save(&pcu_fpu_ops); 144 } 145 146 static inline void 147 fpu_discard(void) 148 { 149 pcu_discard(&pcu_fpu_ops, false); 150 } 151 152 static inline void 153 fpu_replace(void) 154 { 155 pcu_discard(&pcu_fpu_ops, true); 156 } 157 158 static inline bool 159 fpu_valid_p(void) 160 { 161 return pcu_valid_p(&pcu_fpu_ops); 162 } 163 164 void __syncicache(const void *, size_t); 165 166 int cpu_set_onfault(struct faultbuf *, register_t) __returns_twice; 167 void cpu_jump_onfault(struct trapframe *, const struct faultbuf *); 168 169 static inline void 170 cpu_unset_onfault(void) 171 { 172 curlwp->l_md.md_onfault = NULL; 173 } 174 175 static inline struct faultbuf * 176 cpu_disable_onfault(void) 177 { 178 struct faultbuf * const fb = curlwp->l_md.md_onfault; 179 curlwp->l_md.md_onfault = NULL; 180 return fb; 181 } 182 183 static inline void 184 cpu_enable_onfault(struct faultbuf *fb) 185 { 186 curlwp->l_md.md_onfault = fb; 187 } 188 189 void cpu_intr(struct trapframe */*tf*/, register_t /*epc*/, 190 register_t /*status*/, register_t /*cause*/); 191 void cpu_trap(struct trapframe */*tf*/, register_t /*epc*/, 192 register_t /*status*/, register_t /*cause*/, 193 register_t /*badvaddr*/); 194 void cpu_ast(struct trapframe *); 195 void cpu_fast_switchto(struct lwp *, int); 196 197 void cpu_lwp_trampoline(void); 198 199 void * cpu_sendsig_getframe(struct lwp *, int, bool *); 200 201 void init_riscv(vaddr_t, vaddr_t); 202 #endif 203 204 #endif /* _RISCV_LOCORE_H_ */ 205