1 /* $NetBSD: bus_defs.h,v 1.2 2022/11/19 12:16:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _RISCV_BUS_DEFS_H_ 65 #define _RISCV_BUS_DEFS_H_ 66 67 /* 68 * Addresses (in bus space). 69 */ 70 typedef paddr_t bus_addr_t; 71 typedef psize_t bus_size_t; 72 73 #define PRIxBUSADDR PRIxPADDR 74 #define PRIxBUSSIZE PRIxPSIZE 75 #define PRIuBUSSIZE PRIuPSIZE 76 77 typedef struct bus_space *bus_space_tag_t; 78 typedef uintptr_t bus_space_handle_t; 79 80 #define PRIxBSH PRIxPTR 81 82 /* 83 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 84 * bus_size_t size, int flags, bus_space_handle_t *bshp); 85 * 86 * Map a region of bus space. 87 */ 88 #define BUS_SPACE_MAP_BUS1 __BIT(8) 89 #define BUS_SPACE_MAP_BUS2 __BIT(9) 90 #define BUS_SPACE_MAP_BUS3 __BIT(10) 91 #define BUS_SPACE_MAP_BUS4 __BIT(11) 92 93 struct bus_space { 94 int bs_stride; /* offset <<= bs_stride (if needed) */ 95 96 /* mapping/unmapping */ 97 int (*bs_map)(void *, bus_addr_t, bus_size_t, 98 int, bus_space_handle_t *); 99 void (*bs_unmap)(void *, bus_space_handle_t, 100 bus_size_t); 101 int (*bs_subregion)(void *, bus_space_handle_t, 102 bus_size_t, bus_size_t, bus_space_handle_t *); 103 104 /* allocation/deallocation */ 105 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 106 bus_size_t, bus_size_t, bus_size_t, int, 107 bus_addr_t *, bus_space_handle_t *); 108 void (*bs_free)(void *, bus_space_handle_t, 109 bus_size_t); 110 111 /* get kernel virtual address */ 112 void * (*bs_vaddr)(void *, bus_space_handle_t); 113 114 /* mmap bus space for user */ 115 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 116 117 /* barrier */ 118 void (*bs_barrier)(void *, bus_space_handle_t, 119 bus_size_t, bus_size_t, int); 120 121 /* read (single) */ 122 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 123 bus_size_t); 124 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 125 bus_size_t); 126 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 127 bus_size_t); 128 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 129 bus_size_t); 130 131 /* read multiple */ 132 void (*bs_rm_1)(void *, bus_space_handle_t, 133 bus_size_t, uint8_t *, bus_size_t); 134 void (*bs_rm_2)(void *, bus_space_handle_t, 135 bus_size_t, uint16_t *, bus_size_t); 136 void (*bs_rm_4)(void *, bus_space_handle_t, 137 bus_size_t, uint32_t *, bus_size_t); 138 void (*bs_rm_8)(void *, bus_space_handle_t, 139 bus_size_t, uint64_t *, bus_size_t); 140 141 /* read region */ 142 void (*bs_rr_1)(void *, bus_space_handle_t, 143 bus_size_t, uint8_t *, bus_size_t); 144 void (*bs_rr_2)(void *, bus_space_handle_t, 145 bus_size_t, uint16_t *, bus_size_t); 146 void (*bs_rr_4)(void *, bus_space_handle_t, 147 bus_size_t, uint32_t *, bus_size_t); 148 void (*bs_rr_8)(void *, bus_space_handle_t, 149 bus_size_t, uint64_t *, bus_size_t); 150 151 /* write (single) */ 152 void (*bs_w_1)(void *, bus_space_handle_t, 153 bus_size_t, uint8_t); 154 void (*bs_w_2)(void *, bus_space_handle_t, 155 bus_size_t, uint16_t); 156 void (*bs_w_4)(void *, bus_space_handle_t, 157 bus_size_t, uint32_t); 158 void (*bs_w_8)(void *, bus_space_handle_t, 159 bus_size_t, uint64_t); 160 161 /* write multiple */ 162 void (*bs_wm_1)(void *, bus_space_handle_t, 163 bus_size_t, const uint8_t *, bus_size_t); 164 void (*bs_wm_2)(void *, bus_space_handle_t, 165 bus_size_t, const uint16_t *, bus_size_t); 166 void (*bs_wm_4)(void *, bus_space_handle_t, 167 bus_size_t, const uint32_t *, bus_size_t); 168 void (*bs_wm_8)(void *, bus_space_handle_t, 169 bus_size_t, const uint64_t *, bus_size_t); 170 171 /* write region */ 172 void (*bs_wr_1)(void *, bus_space_handle_t, 173 bus_size_t, const uint8_t *, bus_size_t); 174 void (*bs_wr_2)(void *, bus_space_handle_t, 175 bus_size_t, const uint16_t *, bus_size_t); 176 void (*bs_wr_4)(void *, bus_space_handle_t, 177 bus_size_t, const uint32_t *, bus_size_t); 178 void (*bs_wr_8)(void *, bus_space_handle_t, 179 bus_size_t, const uint64_t *, bus_size_t); 180 181 /* set multiple */ 182 void (*bs_sm_1)(void *, bus_space_handle_t, 183 bus_size_t, uint8_t, bus_size_t); 184 void (*bs_sm_2)(void *, bus_space_handle_t, 185 bus_size_t, uint16_t, bus_size_t); 186 void (*bs_sm_4)(void *, bus_space_handle_t, 187 bus_size_t, uint32_t, bus_size_t); 188 void (*bs_sm_8)(void *, bus_space_handle_t, 189 bus_size_t, uint64_t, bus_size_t); 190 191 /* set region */ 192 void (*bs_sr_1)(void *, bus_space_handle_t, 193 bus_size_t, uint8_t, bus_size_t); 194 void (*bs_sr_2)(void *, bus_space_handle_t, 195 bus_size_t, uint16_t, bus_size_t); 196 void (*bs_sr_4)(void *, bus_space_handle_t, 197 bus_size_t, uint32_t, bus_size_t); 198 void (*bs_sr_8)(void *, bus_space_handle_t, 199 bus_size_t, uint64_t, bus_size_t); 200 201 /* copy */ 202 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 203 bus_space_handle_t, bus_size_t, bus_size_t); 204 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 205 bus_space_handle_t, bus_size_t, bus_size_t); 206 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 207 bus_space_handle_t, bus_size_t, bus_size_t); 208 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 209 bus_space_handle_t, bus_size_t, bus_size_t); 210 211 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 212 /* read stream (single) */ 213 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 214 bus_size_t); 215 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 216 bus_size_t); 217 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 218 bus_size_t); 219 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 220 bus_size_t); 221 222 /* read multiple stream */ 223 void (*bs_rm_1_s)(void *, bus_space_handle_t, 224 bus_size_t, uint8_t *, bus_size_t); 225 void (*bs_rm_2_s)(void *, bus_space_handle_t, 226 bus_size_t, uint16_t *, bus_size_t); 227 void (*bs_rm_4_s)(void *, bus_space_handle_t, 228 bus_size_t, uint32_t *, bus_size_t); 229 void (*bs_rm_8_s)(void *, bus_space_handle_t, 230 bus_size_t, uint64_t *, bus_size_t); 231 232 /* read region stream */ 233 void (*bs_rr_1_s)(void *, bus_space_handle_t, 234 bus_size_t, uint8_t *, bus_size_t); 235 void (*bs_rr_2_s)(void *, bus_space_handle_t, 236 bus_size_t, uint16_t *, bus_size_t); 237 void (*bs_rr_4_s)(void *, bus_space_handle_t, 238 bus_size_t, uint32_t *, bus_size_t); 239 void (*bs_rr_8_s)(void *, bus_space_handle_t, 240 bus_size_t, uint64_t *, bus_size_t); 241 242 /* write stream (single) */ 243 void (*bs_w_1_s)(void *, bus_space_handle_t, 244 bus_size_t, uint8_t); 245 void (*bs_w_2_s)(void *, bus_space_handle_t, 246 bus_size_t, uint16_t); 247 void (*bs_w_4_s)(void *, bus_space_handle_t, 248 bus_size_t, uint32_t); 249 void (*bs_w_8_s)(void *, bus_space_handle_t, 250 bus_size_t, uint64_t); 251 252 /* write multiple stream */ 253 void (*bs_wm_1_s)(void *, bus_space_handle_t, 254 bus_size_t, const uint8_t *, bus_size_t); 255 void (*bs_wm_2_s)(void *, bus_space_handle_t, 256 bus_size_t, const uint16_t *, bus_size_t); 257 void (*bs_wm_4_s)(void *, bus_space_handle_t, 258 bus_size_t, const uint32_t *, bus_size_t); 259 void (*bs_wm_8_s)(void *, bus_space_handle_t, 260 bus_size_t, const uint64_t *, bus_size_t); 261 262 /* write region stream */ 263 void (*bs_wr_1_s)(void *, bus_space_handle_t, 264 bus_size_t, const uint8_t *, bus_size_t); 265 void (*bs_wr_2_s)(void *, bus_space_handle_t, 266 bus_size_t, const uint16_t *, bus_size_t); 267 void (*bs_wr_4_s)(void *, bus_space_handle_t, 268 bus_size_t, const uint32_t *, bus_size_t); 269 void (*bs_wr_8_s)(void *, bus_space_handle_t, 270 bus_size_t, const uint64_t *, bus_size_t); 271 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 272 273 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 274 /* peek */ 275 int (*bs_pe_1)(void *, bus_space_handle_t, 276 bus_size_t, uint8_t *); 277 int (*bs_pe_2)(void *, bus_space_handle_t, 278 bus_size_t, uint16_t *); 279 int (*bs_pe_4)(void *, bus_space_handle_t, 280 bus_size_t, uint32_t *); 281 int (*bs_pe_8)(void *, bus_space_handle_t, 282 bus_size_t, uint64_t *); 283 284 /* poke */ 285 int (*bs_po_1)(void *, bus_space_handle_t, 286 bus_size_t, uint8_t); 287 int (*bs_po_2)(void *, bus_space_handle_t, 288 bus_size_t, uint16_t); 289 int (*bs_po_4)(void *, bus_space_handle_t, 290 bus_size_t, uint32_t); 291 int (*bs_po_8)(void *, bus_space_handle_t, 292 bus_size_t, uint64_t); 293 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 294 }; 295 296 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 297 298 /* Bus Space DMA macros */ 299 300 /* 301 * Private flags stored in the DMA map. 302 */ 303 #define _BUS_DMAMAP_COHERENT __BIT(16) /* no cache flush necessary on sync */ 304 #define _BUS_DMAMAP_IS_BOUNCING __BIT(17) /* is bouncing current xfer */ 305 #define _BUS_DMAMAP_NOALLOC __BIT(18) /* don't alloc memory from this range */ 306 307 /* Forwards needed by prototypes below. */ 308 struct mbuf; 309 struct uio; 310 311 typedef struct riscv_bus_dma_tag *bus_dma_tag_t; 312 typedef struct riscv_bus_dmamap *bus_dmamap_t; 313 314 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 315 316 /* 317 * bus_dma_segment_t 318 * 319 * Describes a single contiguous DMA transaction. Values 320 * are suitable for programming into DMA registers. 321 */ 322 struct riscv_bus_dma_segment { 323 /* 324 * PUBLIC MEMBERS: these are used by machine-independent code. 325 */ 326 bus_addr_t ds_addr; /* DMA address */ 327 bus_size_t ds_len; /* length of transfer */ 328 329 /* 330 * PRIVATE MEMBERS: 331 */ 332 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 333 }; 334 typedef struct riscv_bus_dma_segment bus_dma_segment_t; 335 336 /* 337 * riscv_dma_range 338 * 339 * This structure describes a valid DMA range. 340 */ 341 struct riscv_dma_range { 342 paddr_t dr_sysbase; /* system base address */ 343 bus_addr_t dr_busbase; /* appears here on bus */ 344 bus_size_t dr_len; /* length of range */ 345 uint32_t dr_flags; /* flags for range */ 346 }; 347 348 /* 349 * bus_dma_tag_t 350 * 351 * A machine-dependent opaque type describing the implementation of 352 * DMA for a given bus. 353 */ 354 355 struct riscv_bus_dma_tag { 356 /* 357 * DMA range for this tag. If the page doesn't fall within 358 * one of these ranges, an error is returned. The caller 359 * may then decide what to do with the transfer. If the 360 * range pointer is NULL, it is ignored. 361 */ 362 struct riscv_dma_range *_ranges; 363 int _nranges; 364 365 /* 366 * Opaque cookie for use by back-end. 367 */ 368 void *_cookie; 369 370 /* 371 * DMA mapping methods. 372 */ 373 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 374 bus_size_t, bus_size_t, int, bus_dmamap_t *); 375 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 376 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 377 bus_size_t, struct proc *, int); 378 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 379 struct mbuf *, int); 380 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 381 struct uio *, int); 382 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 383 bus_dma_segment_t *, int, bus_size_t, int); 384 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 385 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 386 bus_addr_t, bus_size_t, int); 387 388 /* 389 * DMA memory utility functions. 390 */ 391 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 392 bus_size_t, bus_dma_segment_t *, int, int *, int); 393 void (*_dmamem_free)(bus_dma_tag_t, 394 bus_dma_segment_t *, int); 395 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 396 int, size_t, void **, int); 397 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 398 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 399 int, off_t, int, int); 400 401 /* 402 * DMA tag utility functions 403 */ 404 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 405 bus_dma_tag_t *, int); 406 void (*_dmatag_destroy)(bus_dma_tag_t); 407 408 /* 409 * State for bounce buffers 410 */ 411 int _tag_needs_free; 412 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 413 }; 414 415 /* 416 * bus_dmamap_t 417 * 418 * Describes a DMA mapping. 419 */ 420 struct riscv_bus_dmamap { 421 /* 422 * PRIVATE MEMBERS: not for use by machine-independent code. 423 */ 424 bus_size_t _dm_size; /* largest DMA transfer mappable */ 425 int _dm_segcnt; /* number of segs this map can map */ 426 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 427 bus_size_t _dm_boundary; /* don't cross this */ 428 int _dm_flags; /* misc. flags */ 429 430 void *_dm_origbuf; /* pointer to original buffer */ 431 int _dm_buftype; /* type of buffer */ 432 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 433 434 void *_dm_cookie; /* cookie for bus-specific functions */ 435 436 /* 437 * PUBLIC MEMBERS: these are used by machine-independent code. 438 */ 439 440 bus_size_t dm_maxsegsz; /* largest possible segment */ 441 bus_size_t dm_mapsize; /* size of the mapping */ 442 int dm_nsegs; /* # valid segments in mapping */ 443 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 444 }; 445 446 /* _dm_buftype */ 447 #define _BUS_DMA_BUFTYPE_INVALID 0 448 #define _BUS_DMA_BUFTYPE_LINEAR 1 449 #define _BUS_DMA_BUFTYPE_MBUF 2 450 #define _BUS_DMA_BUFTYPE_UIO 3 451 #define _BUS_DMA_BUFTYPE_RAW 4 452 453 #ifdef _RISCV_BUS_DMA_PRIVATE 454 /* 455 * Cookie used for bounce buffers. A pointer to one of these it stashed in 456 * the DMA map. 457 */ 458 struct riscv_bus_dma_cookie { 459 int id_flags; /* flags; see below */ 460 461 /* 462 * Information about the original buffer used during 463 * DMA map syncs. Note that origibuflen is only used 464 * for ID_BUFTYPE_LINEAR. 465 */ 466 union { 467 void *un_origbuf; /* pointer to orig buffer if 468 bouncing */ 469 char *un_linearbuf; 470 struct mbuf *un_mbuf; 471 struct uio *un_uio; 472 } id_origbuf_un; 473 #define id_origbuf id_origbuf_un.un_origbuf 474 #define id_origlinearbuf id_origbuf_un.un_linearbuf 475 #define id_origmbuf id_origbuf_un.un_mbuf 476 #define id_origuio id_origbuf_un.un_uio 477 bus_size_t id_origbuflen; /* ...and size */ 478 479 void *id_bouncebuf; /* pointer to the bounce buffer */ 480 bus_size_t id_bouncebuflen; /* ...and size */ 481 int id_nbouncesegs; /* number of valid bounce segs */ 482 bus_dma_segment_t 483 id_bouncesegs[0];/* array of bounce buffer */ 484 /* ... physical memory segments */ 485 }; 486 487 /* id_flags */ 488 #define _BUS_DMA_IS_BOUNCING __BIT(2) /* is bouncing current xfer */ 489 #define _BUS_DMA_HAS_BOUNCE __BIT(1) /* has bounce buffers */ 490 #endif /* _RISCV_BUS_DMA_PRIVATE */ 491 #define _BUS_DMA_MIGHT_NEED_BOUNCE __BIT(0) /* may need bounce buffers */ 492 493 #endif /* _RISCV_BUS_DEFS_H_ */ 494