1 /* $NetBSD: oea_machdep.c,v 1.73 2016/05/30 13:04:24 chs Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.73 2016/05/30 13:04:24 chs Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/boot_flag.h> 49 #include <sys/exec.h> 50 #include <sys/kernel.h> 51 #include <sys/mbuf.h> 52 #include <sys/mount.h> 53 #include <sys/msgbuf.h> 54 #include <sys/proc.h> 55 #include <sys/reboot.h> 56 #include <sys/syscallargs.h> 57 #include <sys/syslog.h> 58 #include <sys/systm.h> 59 #include <sys/cpu.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #ifdef DDB 64 #include <powerpc/db_machdep.h> 65 #include <ddb/db_extern.h> 66 #endif 67 68 #ifdef KGDB 69 #include <sys/kgdb.h> 70 #endif 71 72 #ifdef IPKDB 73 #include <ipkdb/ipkdb.h> 74 #endif 75 76 #include <machine/powerpc.h> 77 78 #include <powerpc/trap.h> 79 #include <powerpc/spr.h> 80 #include <powerpc/pte.h> 81 #include <powerpc/altivec.h> 82 #include <powerpc/pcb.h> 83 84 #include <powerpc/oea/bat.h> 85 #include <powerpc/oea/cpufeat.h> 86 #include <powerpc/oea/spr.h> 87 #include <powerpc/oea/sr_601.h> 88 89 char machine[] = MACHINE; /* from <machine/param.h> */ 90 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 91 92 struct vm_map *phys_map = NULL; 93 94 /* 95 * Global variables used here and there 96 */ 97 static void trap0(void *); 98 99 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 100 struct bat battable[BAT_VA2IDX(0xffffffff)+1]; 101 102 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 103 #ifndef MSGBUFADDR 104 paddr_t msgbuf_paddr; 105 #endif 106 107 extern int dsitrap_fix_dbat4[]; 108 extern int dsitrap_fix_dbat5[]; 109 extern int dsitrap_fix_dbat6[]; 110 extern int dsitrap_fix_dbat7[]; 111 112 void 113 oea_init(void (*handler)(void)) 114 { 115 extern int trapcode[], trapsize[]; 116 extern int sctrap[], scsize[]; 117 extern int alitrap[], alisize[]; 118 extern int dsitrap[], dsisize[]; 119 extern int trapstart[], trapend[]; 120 #ifdef PPC_OEA601 121 extern int dsi601trap[], dsi601size[]; 122 #endif 123 extern int decrint[], decrsize[]; 124 extern int tlbimiss[], tlbimsize[]; 125 extern int tlbdlmiss[], tlbdlmsize[]; 126 extern int tlbdsmiss[], tlbdsmsize[]; 127 #if defined(DDB) || defined(KGDB) 128 extern int ddblow[], ddbsize[]; 129 #endif 130 #ifdef IPKDB 131 extern int ipkdblow[], ipkdbsize[]; 132 #endif 133 #ifdef ALTIVEC 134 register_t msr; 135 #endif 136 uintptr_t exc, exc_base; 137 #if defined(ALTIVEC) || defined(PPC_OEA) 138 register_t scratch; 139 #endif 140 unsigned int cpuvers; 141 size_t size; 142 struct cpu_info * const ci = &cpu_info[0]; 143 144 #ifdef PPC_HIGH_VEC 145 exc_base = EXC_HIGHVEC; 146 #else 147 exc_base = 0; 148 #endif 149 KASSERT(mfspr(SPR_SPRG0) == (uintptr_t)ci); 150 151 #if defined (PPC_OEA64_BRIDGE) && defined (PPC_OEA) 152 if (oeacpufeat & OEACPU_64_BRIDGE) 153 pmap_setup64bridge(); 154 else 155 pmap_setup32(); 156 #endif 157 158 159 cpuvers = mfpvr() >> 16; 160 161 /* 162 * Initialize proc0 and current pcb and pmap pointers. 163 */ 164 (void) ci; 165 KASSERT(ci != NULL); 166 KASSERT(curcpu() == ci); 167 KASSERT(lwp0.l_cpu == ci); 168 169 curpcb = lwp_getpcb(&lwp0); 170 memset(curpcb, 0, sizeof(struct pcb)); 171 172 #ifdef ALTIVEC 173 /* 174 * Initialize the vectors with NaNs 175 */ 176 for (scratch = 0; scratch < 32; scratch++) { 177 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 178 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 179 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 180 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 181 } 182 #endif 183 curpm = curpcb->pcb_pm = pmap_kernel(); 184 185 /* 186 * Cause a PGM trap if we branch to 0. 187 * 188 * XXX GCC4.1 complains about memset on address zero, so 189 * don't use the builtin. 190 */ 191 #undef memset 192 memset(0, 0, 0x100); 193 194 /* 195 * Set up trap vectors. Don't assume vectors are on 0x100. 196 */ 197 for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) { 198 switch (exc - exc_base) { 199 default: 200 size = (size_t)trapsize; 201 memcpy((void *)exc, trapcode, size); 202 break; 203 #if 0 204 case EXC_EXI: 205 /* 206 * This one is (potentially) installed during autoconf 207 */ 208 break; 209 #endif 210 case EXC_SC: 211 size = (size_t)scsize; 212 memcpy((void *)exc, sctrap, size); 213 break; 214 case EXC_ALI: 215 size = (size_t)alisize; 216 memcpy((void *)exc, alitrap, size); 217 break; 218 case EXC_DSI: 219 #ifdef PPC_OEA601 220 if (cpuvers == MPC601) { 221 size = (size_t)dsi601size; 222 memcpy((void *)exc, dsi601trap, size); 223 break; 224 } else 225 #endif /* PPC_OEA601 */ 226 if (oeacpufeat & OEACPU_NOBAT) { 227 size = (size_t)alisize; 228 memcpy((void *)exc, alitrap, size); 229 } else { 230 size = (size_t)dsisize; 231 memcpy((void *)exc, dsitrap, size); 232 } 233 break; 234 case EXC_DECR: 235 size = (size_t)decrsize; 236 memcpy((void *)exc, decrint, size); 237 break; 238 case EXC_IMISS: 239 size = (size_t)tlbimsize; 240 memcpy((void *)exc, tlbimiss, size); 241 break; 242 case EXC_DLMISS: 243 size = (size_t)tlbdlmsize; 244 memcpy((void *)exc, tlbdlmiss, size); 245 break; 246 case EXC_DSMISS: 247 size = (size_t)tlbdsmsize; 248 memcpy((void *)exc, tlbdsmiss, size); 249 break; 250 case EXC_PERF: 251 size = (size_t)trapsize; 252 memcpy((void *)exc, trapcode, size); 253 memcpy((void *)(exc_base + EXC_VEC), trapcode, size); 254 break; 255 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 256 case EXC_RUNMODETRC: 257 #ifdef PPC_OEA601 258 if (cpuvers != MPC601) { 259 #endif 260 size = (size_t)trapsize; 261 memcpy((void *)exc, trapcode, size); 262 break; 263 #ifdef PPC_OEA601 264 } 265 /* FALLTHROUGH */ 266 #endif 267 case EXC_PGM: 268 case EXC_TRC: 269 case EXC_BPT: 270 #if defined(DDB) || defined(KGDB) 271 size = (size_t)ddbsize; 272 memcpy((void *)exc, ddblow, size); 273 #if defined(IPKDB) 274 #error "cannot enable IPKDB with DDB or KGDB" 275 #endif 276 #else 277 size = (size_t)ipkdbsize; 278 memcpy((void *)exc, ipkdblow, size); 279 #endif 280 break; 281 #endif /* DDB || IPKDB || KGDB */ 282 } 283 #if 0 284 exc += roundup(size, 32); 285 #endif 286 } 287 288 /* 289 * Install a branch absolute to trap0 to force a panic. 290 */ 291 if ((uintptr_t)trap0 < 0x2000000) { 292 *(volatile uint32_t *) 0 = 0x7c6802a6; 293 *(volatile uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 294 } 295 296 /* 297 * Get the cache sizes because install_extint calls __syncicache. 298 */ 299 cpu_probe_cache(); 300 301 #define MxSPR_MASK 0x7c1fffff 302 #define MFSPR_MQ 0x7c0002a6 303 #define MTSPR_MQ 0x7c0003a6 304 #define MTSPR_IBAT0L 0x7c1183a6 305 #define MTSPR_IBAT1L 0x7c1383a6 306 #define NOP 0x60000000 307 #define B 0x48000000 308 #define TLBSYNC 0x7c00046c 309 #define SYNC 0x7c0004ac 310 #ifdef PPC_OEA64_BRIDGE 311 #define MFMSR_MASK 0xfc1fffff 312 #define MFMSR 0x7c0000a6 313 #define MTMSRD_MASK 0xfc1effff 314 #define MTMSRD 0x7c000164 315 #define RLDICL_MASK 0xfc00001c 316 #define RLDICL 0x78000000 317 #define RFID 0x4c000024 318 #define RFI 0x4c000064 319 #endif 320 321 #ifdef ALTIVEC 322 #define MFSPR_VRSAVE 0x7c0042a6 323 #define MTSPR_VRSAVE 0x7c0043a6 324 325 /* 326 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 327 * not on a AltiVec capable processor. 328 */ 329 __asm volatile ( 330 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 331 "mfmsr %1; mtmsr %0; isync" 332 : "=r"(msr), "=r"(scratch) 333 : "J"(PSL_VEC)); 334 335 /* 336 * If we aren't on an AltiVec capable processor, we need to zap any of 337 * the sequences we save/restore the VRSAVE SPR into NOPs. 338 */ 339 if (scratch & PSL_VEC) { 340 cpu_altivec = 1; 341 } else { 342 for (int *ip = trapstart; ip < trapend; ip++) { 343 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 344 ip[0] = NOP; /* mfspr */ 345 ip[1] = NOP; /* stw */ 346 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 347 ip[-1] = NOP; /* lwz */ 348 ip[0] = NOP; /* mtspr */ 349 } 350 } 351 } 352 #endif 353 354 /* XXX It would seem like this code could be elided ifndef 601, but 355 * doing so breaks my power3 machine. 356 */ 357 /* 358 * If we aren't on a MPC601 processor, we need to zap any of the 359 * sequences we save/restore the MQ SPR into NOPs, and skip over the 360 * sequences where we zap/restore BAT registers on kernel exit/entry. 361 */ 362 if (cpuvers != MPC601) { 363 for (int *ip = trapstart; ip < trapend; ip++) { 364 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 365 ip[0] = NOP; /* mfspr */ 366 ip[1] = NOP; /* stw */ 367 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 368 ip[-1] = NOP; /* lwz */ 369 ip[0] = NOP; /* mtspr */ 370 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 371 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 372 ip[-1] = B | 0x14; /* li */ 373 else 374 ip[-4] = B | 0x24; /* lis */ 375 } 376 } 377 } 378 379 #ifdef PPC_OEA64_BRIDGE 380 if ((oeacpufeat & OEACPU_64_BRIDGE) == 0) { 381 for (int *ip = (int *)exc_base; 382 (uintptr_t)ip <= exc_base + EXC_LAST; 383 ip++) { 384 if ((ip[0] & MFMSR_MASK) == MFMSR 385 && (ip[1] & RLDICL_MASK) == RLDICL 386 && (ip[2] & MTMSRD_MASK) == MTMSRD) { 387 *ip++ = NOP; 388 *ip++ = NOP; 389 ip[0] = NOP; 390 } else if (*ip == RFID) { 391 *ip = RFI; 392 } 393 } 394 395 /* 396 * Now replace each rfid instruction with a rfi instruction. 397 */ 398 for (int *ip = trapstart; ip < trapend; ip++) { 399 if ((ip[0] & MFMSR_MASK) == MFMSR 400 && (ip[1] & RLDICL_MASK) == RLDICL 401 && (ip[2] & MTMSRD_MASK) == MTMSRD) { 402 *ip++ = NOP; 403 *ip++ = NOP; 404 ip[0] = NOP; 405 } else if (*ip == RFID) { 406 *ip = RFI; 407 } 408 } 409 } 410 #endif /* PPC_OEA64_BRIDGE */ 411 412 /* 413 * Sync the changed instructions. 414 */ 415 __syncicache((void *) trapstart, 416 (uintptr_t) trapend - (uintptr_t) trapstart); 417 __syncicache(dsitrap_fix_dbat4, 16); 418 __syncicache(dsitrap_fix_dbat7, 8); 419 #ifdef PPC_OEA601 420 421 /* 422 * If we are on a MPC601 processor, we need to zap any tlbsync 423 * instructions into sync. This differs from the above in 424 * examing all kernel text, as opposed to just the exception handling. 425 * We sync the icache on every instruction found since there are 426 * only very few of them. 427 */ 428 if (cpuvers == MPC601) { 429 extern int kernel_text[], etext[]; 430 int *ip; 431 432 for (ip = kernel_text; ip < etext; ip++) { 433 if (*ip == TLBSYNC) { 434 *ip = SYNC; 435 __syncicache(ip, sizeof(*ip)); 436 } 437 } 438 } 439 #endif /* PPC_OEA601 */ 440 441 /* 442 * Configure a PSL user mask matching this processor. 443 * Don't allow to set PSL_FP/PSL_VEC, since that will affect PCU. 444 */ 445 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 446 cpu_pslusermod = PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 447 #ifdef PPC_OEA601 448 if (cpuvers == MPC601) { 449 cpu_psluserset &= PSL_601_MASK; 450 cpu_pslusermod &= PSL_601_MASK; 451 } 452 #endif 453 #ifdef PPC_HIGH_VEC 454 cpu_psluserset |= PSL_IP; /* XXX ok? */ 455 #endif 456 457 /* 458 * external interrupt handler install 459 */ 460 if (handler) 461 oea_install_extint(handler); 462 463 __syncicache((void *)exc_base, EXC_LAST + 0x100); 464 465 /* 466 * Now enable translation (and machine checks/recoverable interrupts). 467 */ 468 #ifdef PPC_OEA 469 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 470 : "=r"(scratch) 471 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 472 #endif 473 474 /* 475 * Let's take all the indirect calls via our stubs and patch 476 * them to be direct calls. 477 */ 478 cpu_fixup_stubs(); 479 480 KASSERT(curcpu() == ci); 481 } 482 483 #ifdef PPC_OEA601 484 void 485 mpc601_ioseg_add(paddr_t pa, register_t len) 486 { 487 const u_int i = pa >> ADDR_SR_SHFT; 488 489 if (len != BAT_BL_256M) 490 panic("mpc601_ioseg_add: len != 256M"); 491 492 /* 493 * Translate into an I/O segment, load it, and stash away for use 494 * in pmap_bootstrap(). 495 */ 496 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 497 498 /* 499 * XXX Setting segment register 0xf on my powermac 7200 500 * wedges machine so set later in pmap.c 501 */ 502 /* 503 __asm volatile ("mtsrin %0,%1" 504 :: "r"(iosrtable[i]), 505 "r"(pa)); 506 */ 507 } 508 #endif /* PPC_OEA601 */ 509 510 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 511 #define DBAT_SET(n, batl, batu) \ 512 do { \ 513 mtspr(SPR_DBAT##n##L, (batl)); \ 514 mtspr(SPR_DBAT##n##U, (batu)); \ 515 } while (/*CONSTCOND*/ 0) 516 #define DBAT_RESET(n) DBAT_SET(n, 0, 0) 517 #define DBATU_GET(n) mfspr(SPR_DBAT##n##U) 518 #define IBAT_SET(n, batl, batu) \ 519 do { \ 520 mtspr(SPR_IBAT##n##L, (batl)); \ 521 mtspr(SPR_IBAT##n##U, (batu)); \ 522 } while (/*CONSTCOND*/ 0) 523 #define IBAT_RESET(n) IBAT_SET(n, 0, 0) 524 525 void 526 oea_iobat_add(paddr_t pa, register_t len) 527 { 528 static int z = 1; 529 const u_int n = BAT_BL_TO_SIZE(len) / BAT_BL_TO_SIZE(BAT_BL_8M); 530 const u_int i = BAT_VA2IDX(pa) & -n; /* in case pa was in the middle */ 531 const int after_bat3 = (oeacpufeat & OEACPU_HIGHBAT) ? 4 : 8; 532 533 KASSERT(len >= BAT_BL_8M); 534 535 /* 536 * If the caller wanted a bigger BAT than the hardware supports, 537 * split it into smaller BATs. 538 */ 539 if (len > BAT_BL_256M && (oeacpufeat & OEACPU_XBSEN) == 0) { 540 u_int xn = BAT_BL_TO_SIZE(len) >> 28; 541 while (xn-- > 0) { 542 oea_iobat_add(pa, BAT_BL_256M); 543 pa += 0x10000000; 544 } 545 return; 546 } 547 548 const register_t batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 549 const register_t batu = BATU(pa, len, BAT_Vs); 550 551 for (u_int j = 0; j < n; j++) { 552 battable[i + j].batl = batl; 553 battable[i + j].batu = batu; 554 } 555 556 /* 557 * Let's start loading the BAT registers. 558 */ 559 switch (z) { 560 case 1: 561 DBAT_SET(1, batl, batu); 562 z = 2; 563 break; 564 case 2: 565 DBAT_SET(2, batl, batu); 566 z = 3; 567 break; 568 case 3: 569 DBAT_SET(3, batl, batu); 570 z = after_bat3; /* no highbat, skip to end */ 571 break; 572 case 4: 573 DBAT_SET(4, batl, batu); 574 z = 5; 575 break; 576 case 5: 577 DBAT_SET(5, batl, batu); 578 z = 6; 579 break; 580 case 6: 581 DBAT_SET(6, batl, batu); 582 z = 7; 583 break; 584 case 7: 585 DBAT_SET(7, batl, batu); 586 z = 8; 587 break; 588 default: 589 break; 590 } 591 } 592 593 void 594 oea_iobat_remove(paddr_t pa) 595 { 596 const u_int i = BAT_VA2IDX(pa); 597 598 if (!BAT_VA_MATCH_P(battable[i].batu, pa) || 599 !BAT_VALID_P(battable[i].batu, PSL_PR)) 600 return; 601 const int n = 602 __SHIFTOUT(battable[i].batu, (BAT_XBL|BAT_BL) & ~BAT_BL_8M) + 1; 603 KASSERT((n & (n-1)) == 0); /* power of 2 */ 604 KASSERT((i & (n-1)) == 0); /* multiple of n */ 605 606 memset(&battable[i], 0, n*sizeof(battable[0])); 607 608 const int maxbat = oeacpufeat & OEACPU_HIGHBAT ? 8 : 4; 609 for (u_int k = 1 ; k < maxbat; k++) { 610 register_t batu; 611 switch (k) { 612 case 1: 613 batu = DBATU_GET(1); 614 if (BAT_VA_MATCH_P(batu, pa) && 615 BAT_VALID_P(batu, PSL_PR)) 616 DBAT_RESET(1); 617 break; 618 case 2: 619 batu = DBATU_GET(2); 620 if (BAT_VA_MATCH_P(batu, pa) && 621 BAT_VALID_P(batu, PSL_PR)) 622 DBAT_RESET(2); 623 break; 624 case 3: 625 batu = DBATU_GET(3); 626 if (BAT_VA_MATCH_P(batu, pa) && 627 BAT_VALID_P(batu, PSL_PR)) 628 DBAT_RESET(3); 629 break; 630 case 4: 631 batu = DBATU_GET(4); 632 if (BAT_VA_MATCH_P(batu, pa) && 633 BAT_VALID_P(batu, PSL_PR)) 634 DBAT_RESET(4); 635 break; 636 case 5: 637 batu = DBATU_GET(5); 638 if (BAT_VA_MATCH_P(batu, pa) && 639 BAT_VALID_P(batu, PSL_PR)) 640 DBAT_RESET(5); 641 break; 642 case 6: 643 batu = DBATU_GET(6); 644 if (BAT_VA_MATCH_P(batu, pa) && 645 BAT_VALID_P(batu, PSL_PR)) 646 DBAT_RESET(6); 647 break; 648 case 7: 649 batu = DBATU_GET(7); 650 if (BAT_VA_MATCH_P(batu, pa) && 651 BAT_VALID_P(batu, PSL_PR)) 652 DBAT_RESET(7); 653 break; 654 default: 655 break; 656 } 657 } 658 } 659 660 void 661 oea_batinit(paddr_t pa, ...) 662 { 663 struct mem_region *allmem, *availmem, *mp; 664 register_t msr = mfmsr(); 665 va_list ap; 666 #ifdef PPC_OEA601 667 unsigned int cpuvers; 668 669 cpuvers = mfpvr() >> 16; 670 #endif /* PPC_OEA601 */ 671 672 /* 673 * we need to call this before zapping BATs so OF calls work 674 */ 675 mem_regions(&allmem, &availmem); 676 677 /* 678 * Initialize BAT registers to unmapped to not generate 679 * overlapping mappings below. 680 * 681 * The 601's implementation differs in the Valid bit being situated 682 * in the lower BAT register, and in being a unified BAT only whose 683 * four entries are accessed through the IBAT[0-3] SPRs. 684 * 685 * Also, while the 601 does distinguish between supervisor/user 686 * protection keys, it does _not_ distinguish between validity in 687 * supervisor/user mode. 688 */ 689 if ((msr & (PSL_IR|PSL_DR)) == 0) { 690 #ifdef PPC_OEA601 691 if (cpuvers == MPC601) { 692 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 693 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 694 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 695 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 696 } else 697 #endif /* PPC_OEA601 */ 698 { 699 DBAT_RESET(0); IBAT_RESET(0); 700 DBAT_RESET(1); IBAT_RESET(1); 701 DBAT_RESET(2); IBAT_RESET(2); 702 DBAT_RESET(3); IBAT_RESET(3); 703 if (oeacpufeat & OEACPU_HIGHBAT) { 704 DBAT_RESET(4); IBAT_RESET(4); 705 DBAT_RESET(5); IBAT_RESET(5); 706 DBAT_RESET(6); IBAT_RESET(6); 707 DBAT_RESET(7); IBAT_RESET(7); 708 709 /* 710 * Change the first instruction to branch to 711 * dsitrap_fix_dbat6 712 */ 713 dsitrap_fix_dbat4[0] &= ~0xfffc; 714 dsitrap_fix_dbat4[0] 715 += (uintptr_t)dsitrap_fix_dbat6 716 - (uintptr_t)&dsitrap_fix_dbat4[0]; 717 718 /* 719 * Change the second instruction to branch to 720 * dsitrap_fix_dbat5 if bit 30 (aka bit 1) is 721 * true. 722 */ 723 dsitrap_fix_dbat4[1] = 0x419e0000 724 + (uintptr_t)dsitrap_fix_dbat5 725 - (uintptr_t)&dsitrap_fix_dbat4[1]; 726 727 /* 728 * Change it to load dbat4 instead of dbat2 729 */ 730 dsitrap_fix_dbat4[2] = 0x7fd88ba6; 731 dsitrap_fix_dbat4[3] = 0x7ff98ba6; 732 733 /* 734 * Change it to load dbat7 instead of dbat3 735 */ 736 dsitrap_fix_dbat7[0] = 0x7fde8ba6; 737 dsitrap_fix_dbat7[1] = 0x7fff8ba6; 738 } 739 } 740 } 741 742 /* 743 * Set up BAT to map physical memory 744 */ 745 #ifdef PPC_OEA601 746 if (cpuvers == MPC601) { 747 int i; 748 749 /* 750 * Set up battable to map the lowest 256 MB area. 751 * Map the lowest 32 MB area via BAT[0-3]; 752 * BAT[01] are fixed, BAT[23] are floating. 753 */ 754 for (i = 0; i < 32; i++) { 755 battable[i].batl = BATL601(i << 23, 756 BAT601_BSM_8M, BAT601_V); 757 battable[i].batu = BATU601(i << 23, 758 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 759 } 760 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 761 :: "r"(battable[0x00000000 >> 23].batl), 762 "r"(battable[0x00000000 >> 23].batu)); 763 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 764 :: "r"(battable[0x00800000 >> 23].batl), 765 "r"(battable[0x00800000 >> 23].batu)); 766 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 767 :: "r"(battable[0x01000000 >> 23].batl), 768 "r"(battable[0x01000000 >> 23].batu)); 769 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 770 :: "r"(battable[0x01800000 >> 23].batl), 771 "r"(battable[0x01800000 >> 23].batu)); 772 } 773 #endif /* PPC_OEA601 */ 774 775 /* 776 * Now setup other fixed bat registers 777 * 778 * Note that we still run in real mode, and the BAT 779 * registers were cleared above. 780 */ 781 782 va_start(ap, pa); 783 784 /* 785 * Add any I/O BATs specificed; 786 * use I/O segments on the BAT-starved 601. 787 */ 788 #ifdef PPC_OEA601 789 if (cpuvers == MPC601) { 790 while (pa != 0) { 791 register_t len = va_arg(ap, register_t); 792 mpc601_ioseg_add(pa, len); 793 pa = va_arg(ap, paddr_t); 794 } 795 } else 796 #endif 797 { 798 while (pa != 0) { 799 register_t len = va_arg(ap, register_t); 800 oea_iobat_add(pa, len); 801 pa = va_arg(ap, paddr_t); 802 } 803 } 804 805 va_end(ap); 806 807 /* 808 * Set up battable to map all RAM regions. 809 */ 810 #ifdef PPC_OEA601 811 if (cpuvers == MPC601) { 812 for (mp = allmem; mp->size; mp++) { 813 paddr_t paddr = mp->start & 0xff800000; 814 paddr_t end = mp->start + mp->size; 815 816 do { 817 u_int ix = paddr >> 23; 818 819 battable[ix].batl = 820 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 821 battable[ix].batu = 822 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 823 paddr += (1 << 23); 824 } while (paddr < end); 825 } 826 } else 827 #endif 828 { 829 const register_t bat_inc = BAT_IDX2VA(1); 830 for (mp = allmem; mp->size; mp++) { 831 paddr_t paddr = mp->start & -bat_inc; 832 paddr_t end = roundup2(mp->start + mp->size, bat_inc); 833 834 /* 835 * If the next entries are adjacent, merge them 836 * into this one 837 */ 838 while (mp[1].size && end == (mp[1].start & -bat_inc)) { 839 mp++; 840 end = roundup2(mp->start + mp->size, bat_inc); 841 } 842 843 while (paddr < end) { 844 register_t bl = (oeacpufeat & OEACPU_XBSEN 845 ? BAT_BL_2G 846 : BAT_BL_256M); 847 psize_t size = BAT_BL_TO_SIZE(bl); 848 u_int n = BAT_VA2IDX(size); 849 u_int i = BAT_VA2IDX(paddr); 850 851 while ((paddr & (size - 1)) 852 || paddr + size > end) { 853 size >>= 1; 854 bl = (bl >> 1) & (BAT_XBL|BAT_BL); 855 n >>= 1; 856 } 857 858 KASSERT(size >= bat_inc); 859 KASSERT(n >= 1); 860 KASSERT(bl >= BAT_BL_8M); 861 862 register_t batl = BATL(paddr, BAT_M, BAT_PP_RW); 863 register_t batu = BATU(paddr, bl, BAT_Vs); 864 865 for (; n-- > 0; i++) { 866 battable[i].batl = batl; 867 battable[i].batu = batu; 868 } 869 paddr += size; 870 } 871 } 872 /* 873 * Set up BAT0 to only map the lowest area. 874 */ 875 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 876 "mtdbatl 0,%0; mtdbatu 0,%1;" 877 :: "r"(battable[0].batl), "r"(battable[0].batu)); 878 } 879 } 880 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 881 882 void 883 oea_install_extint(void (*handler)(void)) 884 { 885 extern int extint[], extsize[]; 886 extern int extint_call[]; 887 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 888 #ifdef PPC_HIGH_VEC 889 const uintptr_t exc_exi_base = EXC_HIGHVEC + EXC_EXI; 890 #else 891 const uintptr_t exc_exi_base = EXC_EXI; 892 #endif 893 int omsr, msr; 894 895 #ifdef DIAGNOSTIC 896 if (offset > 0x1ffffff) 897 panic("install_extint: %p too far away (%#lx)", handler, 898 (unsigned long) offset); 899 #endif 900 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 901 : "=r" (omsr), "=r" (msr) 902 : "K" ((u_short)~PSL_EE)); 903 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 904 __syncicache((void *)extint_call, sizeof extint_call[0]); 905 memcpy((void *)exc_exi_base, extint, (size_t)extsize); 906 #ifdef PPC_OEA64_BRIDGE 907 if ((oeacpufeat & OEACPU_64_BRIDGE) == 0) { 908 for (int *ip = (int *)exc_exi_base; 909 (uintptr_t)ip <= exc_exi_base + (size_t)extsize; 910 ip++) { 911 if ((ip[0] & MFMSR_MASK) == MFMSR 912 && (ip[1] & RLDICL_MASK) == RLDICL 913 && (ip[2] & MTMSRD_MASK) == MTMSRD) { 914 *ip++ = NOP; 915 *ip++ = NOP; 916 ip[0] = NOP; 917 } else if (*ip == RFID) { 918 *ip = RFI; 919 } 920 } 921 } 922 #endif 923 __syncicache((void *)exc_exi_base, (size_t)extsize); 924 925 __asm volatile ("mtmsr %0" :: "r"(omsr)); 926 } 927 928 /* 929 * Machine dependent startup code. 930 */ 931 void 932 oea_startup(const char *model) 933 { 934 uintptr_t sz; 935 void *v; 936 vaddr_t minaddr, maxaddr; 937 char pbuf[9], mstr[128]; 938 939 KASSERT(curcpu() != NULL); 940 KASSERT(lwp0.l_cpu != NULL); 941 KASSERT(curcpu()->ci_idepth == -1); 942 943 sz = round_page(MSGBUFSIZE); 944 #ifdef MSGBUFADDR 945 v = (void *) MSGBUFADDR; 946 #else 947 /* 948 * If the msgbuf is not in segment 0, allocate KVA for it and access 949 * it via mapped pages. [This prevents unneeded BAT switches.] 950 */ 951 v = (void *) msgbuf_paddr; 952 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 953 u_int i; 954 955 minaddr = 0; 956 if (uvm_map(kernel_map, &minaddr, sz, 957 NULL, UVM_UNKNOWN_OFFSET, 0, 958 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 959 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 960 panic("startup: cannot allocate VM for msgbuf"); 961 v = (void *)minaddr; 962 for (i = 0; i < sz; i += PAGE_SIZE) { 963 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 964 VM_PROT_READ|VM_PROT_WRITE, 0); 965 } 966 pmap_update(pmap_kernel()); 967 } 968 #endif 969 initmsgbuf(v, sz); 970 971 printf("%s%s", copyright, version); 972 if (model != NULL) 973 printf("Model: %s\n", model); 974 cpu_identify(mstr, sizeof(mstr)); 975 cpu_setmodel("%s", mstr); 976 977 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 978 printf("total memory = %s\n", pbuf); 979 980 /* 981 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 982 * the bufpages are allocated in case they overlap since it's not 983 * fatal if we can't allocate these. 984 */ 985 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 986 int error; 987 minaddr = 0xDEAC0000; 988 error = uvm_map(kernel_map, &minaddr, 0x30000, 989 NULL, UVM_UNKNOWN_OFFSET, 0, 990 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 991 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 992 if (error != 0 || minaddr != 0xDEAC0000) 993 printf("oea_startup: failed to allocate DEAD " 994 "ZONE: error=%d\n", error); 995 } 996 997 minaddr = 0; 998 999 /* 1000 * Allocate a submap for physio 1001 */ 1002 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1003 VM_PHYS_SIZE, 0, false, NULL); 1004 1005 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1006 printf("avail memory = %s\n", pbuf); 1007 1008 #ifdef MULTIPROCESSOR 1009 kcpuset_create(&cpuset_info.cpus_running, true); 1010 kcpuset_create(&cpuset_info.cpus_hatched, true); 1011 kcpuset_create(&cpuset_info.cpus_paused, true); 1012 kcpuset_create(&cpuset_info.cpus_resumed, true); 1013 kcpuset_create(&cpuset_info.cpus_halted, true); 1014 1015 kcpuset_set(cpuset_info.cpus_running, cpu_number()); 1016 #endif 1017 } 1018 1019 /* 1020 * Crash dump handling. 1021 */ 1022 1023 void 1024 oea_dumpsys(void) 1025 { 1026 printf("dumpsys: TBD\n"); 1027 } 1028 1029 /* 1030 * Convert kernel VA to physical address 1031 */ 1032 paddr_t 1033 kvtop(void *addr) 1034 { 1035 vaddr_t va; 1036 paddr_t pa; 1037 uintptr_t off; 1038 extern char end[]; 1039 1040 if (addr < (void *)end) 1041 return (paddr_t)addr; 1042 1043 va = trunc_page((vaddr_t)addr); 1044 off = (uintptr_t)addr - va; 1045 1046 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 1047 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 1048 return (paddr_t)addr; 1049 } 1050 1051 return(pa + off); 1052 } 1053 1054 /* 1055 * Allocate vm space and mapin the I/O address 1056 */ 1057 void * 1058 mapiodev(paddr_t pa, psize_t len, bool prefetchable) 1059 { 1060 paddr_t faddr; 1061 vaddr_t taddr, va; 1062 int off; 1063 1064 faddr = trunc_page(pa); 1065 off = pa - faddr; 1066 len = round_page(off + len); 1067 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 1068 1069 if (va == 0) 1070 return NULL; 1071 1072 for (; len > 0; len -= PAGE_SIZE) { 1073 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE, 1074 (prefetchable ? PMAP_MD_PREFETCHABLE : PMAP_NOCACHE)); 1075 faddr += PAGE_SIZE; 1076 taddr += PAGE_SIZE; 1077 } 1078 pmap_update(pmap_kernel()); 1079 return (void *)(va + off); 1080 } 1081 1082 void 1083 unmapiodev(vaddr_t va, vsize_t len) 1084 { 1085 paddr_t faddr; 1086 1087 if (! va) 1088 return; 1089 1090 faddr = trunc_page(va); 1091 len = round_page(va - faddr + len); 1092 1093 pmap_kremove(faddr, len); 1094 pmap_update(pmap_kernel()); 1095 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 1096 } 1097 1098 void 1099 trap0(void *lr) 1100 { 1101 panic("call to null-ptr from %p", lr); 1102 } 1103