1 /* $NetBSD: cpu_subr.c,v 1.99 2019/02/06 07:32:50 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.99 2019/02/06 07:32:50 mrg Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 extern void init_scom_speedctl(void); 77 78 int cpu = -1; 79 int ncpus; 80 81 struct fmttab { 82 register_t fmt_mask; 83 register_t fmt_value; 84 const char *fmt_string; 85 }; 86 87 /* 88 * This should be one per CPU but since we only support it on 750 variants it 89 * doesn't really matter since none of them support SMP 90 */ 91 envsys_data_t sensor; 92 93 static const struct fmttab cpu_7450_l2cr_formats[] = { 94 { L2CR_L2E, 0, " disabled" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 97 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 98 { L2CR_L2E, ~0, " 256KB L2 cache" }, 99 { L2CR_L2PE, 0, " no parity" }, 100 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 101 { 0, 0, NULL } 102 }; 103 104 static const struct fmttab cpu_7448_l2cr_formats[] = { 105 { L2CR_L2E, 0, " disabled" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 108 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 109 { L2CR_L2E, ~0, " 1MB L2 cache" }, 110 { L2CR_L2PE, 0, " no parity" }, 111 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 112 { 0, 0, NULL } 113 }; 114 115 static const struct fmttab cpu_7457_l2cr_formats[] = { 116 { L2CR_L2E, 0, " disabled" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 118 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 119 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 120 { L2CR_L2E, ~0, " 512KB L2 cache" }, 121 { L2CR_L2PE, 0, " no parity" }, 122 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 123 { 0, 0, NULL } 124 }; 125 126 static const struct fmttab cpu_7450_l3cr_formats[] = { 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 128 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 129 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 130 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 131 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 133 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 134 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 135 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 136 { L3CR_L3SIZ, ~0, " L3 cache" }, 137 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 138 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 139 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 140 { L3CR_L3CLK, ~0, " at" }, 141 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 142 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 143 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 144 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 145 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 146 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 147 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 148 { L3CR_L3CLK, ~0, " ratio" }, 149 { 0, 0, NULL }, 150 }; 151 152 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 153 { L2CR_L2E, 0, " disabled" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 157 { 0, ~0, " 512KB" }, 158 { L2CR_L2WT, L2CR_L2WT, " WT" }, 159 { L2CR_L2WT, 0, " WB" }, 160 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 161 { 0, ~0, " L2 cache" }, 162 { 0, 0, NULL } 163 }; 164 165 static const struct fmttab cpu_l2cr_formats[] = { 166 { L2CR_L2E, 0, " disabled" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 168 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 169 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 170 { L2CR_L2PE, L2CR_L2PE, " parity" }, 171 { L2CR_L2PE, 0, " no-parity" }, 172 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 173 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 174 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 175 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 176 { L2CR_L2WT, L2CR_L2WT, " WT" }, 177 { L2CR_L2WT, 0, " WB" }, 178 { L2CR_L2E, ~0, " L2 cache" }, 179 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 180 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 181 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 182 { L2CR_L2CLK, ~0, " at" }, 183 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 184 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 185 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 186 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 187 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 188 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 189 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 190 { L2CR_L2CLK, ~0, " ratio" }, 191 { 0, 0, NULL } 192 }; 193 194 static void cpu_fmttab_print(const struct fmttab *, register_t); 195 196 struct cputab { 197 const char name[8]; 198 uint16_t version; 199 uint16_t revfmt; 200 }; 201 #define REVFMT_MAJMIN 1 /* %u.%u */ 202 #define REVFMT_HEX 2 /* 0x%04x */ 203 #define REVFMT_DEC 3 /* %u */ 204 static const struct cputab models[] = { 205 { "601", MPC601, REVFMT_DEC }, 206 { "602", MPC602, REVFMT_DEC }, 207 { "603", MPC603, REVFMT_MAJMIN }, 208 { "603e", MPC603e, REVFMT_MAJMIN }, 209 { "603ev", MPC603ev, REVFMT_MAJMIN }, 210 { "G2", MPCG2, REVFMT_MAJMIN }, 211 { "604", MPC604, REVFMT_MAJMIN }, 212 { "604e", MPC604e, REVFMT_MAJMIN }, 213 { "604ev", MPC604ev, REVFMT_MAJMIN }, 214 { "620", MPC620, REVFMT_HEX }, 215 { "750", MPC750, REVFMT_MAJMIN }, 216 { "750FX", IBM750FX, REVFMT_MAJMIN }, 217 { "750GX", IBM750GX, REVFMT_MAJMIN }, 218 { "7400", MPC7400, REVFMT_MAJMIN }, 219 { "7410", MPC7410, REVFMT_MAJMIN }, 220 { "7450", MPC7450, REVFMT_MAJMIN }, 221 { "7455", MPC7455, REVFMT_MAJMIN }, 222 { "7457", MPC7457, REVFMT_MAJMIN }, 223 { "7447A", MPC7447A, REVFMT_MAJMIN }, 224 { "7448", MPC7448, REVFMT_MAJMIN }, 225 { "8240", MPC8240, REVFMT_MAJMIN }, 226 { "8245", MPC8245, REVFMT_MAJMIN }, 227 { "970", IBM970, REVFMT_MAJMIN }, 228 { "970FX", IBM970FX, REVFMT_MAJMIN }, 229 { "970MP", IBM970MP, REVFMT_MAJMIN }, 230 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 231 { "", 0, REVFMT_HEX } 232 }; 233 234 #ifdef MULTIPROCESSOR 235 struct cpu_info cpu_info[CPU_MAXNUM] = { 236 [0] = { 237 .ci_curlwp = &lwp0, 238 }, 239 }; 240 volatile struct cpu_hatch_data *cpu_hatch_data; 241 volatile int cpu_hatch_stack; 242 #define HATCH_STACK_SIZE 0x1000 243 extern int ticks_per_intr; 244 #include <powerpc/oea/bat.h> 245 #include <powerpc/pic/picvar.h> 246 #include <powerpc/pic/ipivar.h> 247 extern struct bat battable[]; 248 #else 249 struct cpu_info cpu_info[1] = { 250 [0] = { 251 .ci_curlwp = &lwp0, 252 }, 253 }; 254 #endif /*MULTIPROCESSOR*/ 255 256 int cpu_altivec; 257 register_t cpu_psluserset; 258 register_t cpu_pslusermod; 259 register_t cpu_pslusermask = 0xffff; 260 261 /* This is to be called from locore.S, and nowhere else. */ 262 263 void 264 cpu_model_init(void) 265 { 266 u_int pvr, vers; 267 268 pvr = mfpvr(); 269 vers = pvr >> 16; 270 271 oeacpufeat = 0; 272 273 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 274 vers == IBMCELL || vers == IBMPOWER6P5) { 275 oeacpufeat |= OEACPU_64; 276 oeacpufeat |= OEACPU_64_BRIDGE; 277 oeacpufeat |= OEACPU_NOBAT; 278 279 } else if (vers == MPC601) { 280 oeacpufeat |= OEACPU_601; 281 282 } else if (MPC745X_P(vers)) { 283 register_t hid1 = mfspr(SPR_HID1); 284 285 if (vers != MPC7450) { 286 register_t hid0 = mfspr(SPR_HID0); 287 288 /* Enable more SPRG registers */ 289 oeacpufeat |= OEACPU_HIGHSPRG; 290 291 /* Enable more BAT registers */ 292 oeacpufeat |= OEACPU_HIGHBAT; 293 hid0 |= HID0_HIGH_BAT_EN; 294 295 /* Enable larger BAT registers */ 296 oeacpufeat |= OEACPU_XBSEN; 297 hid0 |= HID0_XBSEN; 298 299 mtspr(SPR_HID0, hid0); 300 __asm volatile("sync;isync"); 301 } 302 303 /* Enable address broadcasting for MP systems */ 304 hid1 |= HID1_SYNCBE | HID1_ABE; 305 306 mtspr(SPR_HID1, hid1); 307 __asm volatile("sync;isync"); 308 309 } else if (vers == IBM750FX || vers == IBM750GX) { 310 oeacpufeat |= OEACPU_HIGHBAT; 311 } 312 } 313 314 void 315 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 316 { 317 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 318 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 319 (data & fmt->fmt_mask) == fmt->fmt_value) 320 aprint_normal("%s", fmt->fmt_string); 321 } 322 } 323 324 void 325 cpu_idlespin(void) 326 { 327 register_t msr; 328 329 if (powersave <= 0) 330 return; 331 332 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 333 if (cpu_altivec) 334 __asm volatile("dssall"); 335 #endif 336 337 __asm volatile( 338 "sync;" 339 "mfmsr %0;" 340 "oris %0,%0,%1@h;" /* enter power saving mode */ 341 "mtmsr %0;" 342 "isync;" 343 : "=r"(msr) 344 : "J"(PSL_POW)); 345 } 346 347 void 348 cpu_probe_cache(void) 349 { 350 u_int assoc, pvr, vers; 351 352 pvr = mfpvr(); 353 vers = pvr >> 16; 354 355 356 /* Presently common across almost all implementations. */ 357 curcpu()->ci_ci.dcache_line_size = 32; 358 curcpu()->ci_ci.icache_line_size = 32; 359 360 361 switch (vers) { 362 #define K *1024 363 case IBM750FX: 364 case IBM750GX: 365 case MPC601: 366 case MPC750: 367 case MPC7400: 368 case MPC7447A: 369 case MPC7448: 370 case MPC7450: 371 case MPC7455: 372 case MPC7457: 373 curcpu()->ci_ci.dcache_size = 32 K; 374 curcpu()->ci_ci.icache_size = 32 K; 375 assoc = 8; 376 break; 377 case MPC603: 378 curcpu()->ci_ci.dcache_size = 8 K; 379 curcpu()->ci_ci.icache_size = 8 K; 380 assoc = 2; 381 break; 382 case MPC603e: 383 case MPC603ev: 384 case MPC604: 385 case MPC8240: 386 case MPC8245: 387 case MPCG2: 388 curcpu()->ci_ci.dcache_size = 16 K; 389 curcpu()->ci_ci.icache_size = 16 K; 390 assoc = 4; 391 break; 392 case MPC604e: 393 case MPC604ev: 394 curcpu()->ci_ci.dcache_size = 32 K; 395 curcpu()->ci_ci.icache_size = 32 K; 396 assoc = 4; 397 break; 398 case IBMPOWER3II: 399 curcpu()->ci_ci.dcache_size = 64 K; 400 curcpu()->ci_ci.icache_size = 32 K; 401 curcpu()->ci_ci.dcache_line_size = 128; 402 curcpu()->ci_ci.icache_line_size = 128; 403 assoc = 128; /* not a typo */ 404 break; 405 case IBM970: 406 case IBM970FX: 407 case IBM970MP: 408 curcpu()->ci_ci.dcache_size = 32 K; 409 curcpu()->ci_ci.icache_size = 64 K; 410 curcpu()->ci_ci.dcache_line_size = 128; 411 curcpu()->ci_ci.icache_line_size = 128; 412 assoc = 2; 413 break; 414 415 default: 416 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 417 curcpu()->ci_ci.icache_size = PAGE_SIZE; 418 assoc = 1; 419 #undef K 420 } 421 422 /* 423 * Possibly recolor. 424 */ 425 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 426 } 427 428 struct cpu_info * 429 cpu_attach_common(device_t self, int id) 430 { 431 struct cpu_info *ci; 432 u_int pvr, vers; 433 434 ci = &cpu_info[id]; 435 #ifndef MULTIPROCESSOR 436 /* 437 * If this isn't the primary CPU, print an error message 438 * and just bail out. 439 */ 440 if (id != 0) { 441 aprint_naive("\n"); 442 aprint_normal(": ID %d\n", id); 443 aprint_normal_dev(self, 444 "processor off-line; " 445 "multiprocessor support not present in kernel\n"); 446 return (NULL); 447 } 448 #endif 449 450 ci->ci_cpuid = id; 451 ci->ci_idepth = -1; 452 ci->ci_dev = self; 453 ci->ci_idlespin = cpu_idlespin; 454 455 pvr = mfpvr(); 456 vers = (pvr >> 16) & 0xffff; 457 458 switch (id) { 459 case 0: 460 /* load my cpu_number to PIR */ 461 switch (vers) { 462 case MPC601: 463 case MPC604: 464 case MPC604e: 465 case MPC604ev: 466 case MPC7400: 467 case MPC7410: 468 case MPC7447A: 469 case MPC7448: 470 case MPC7450: 471 case MPC7455: 472 case MPC7457: 473 mtspr(SPR_PIR, id); 474 } 475 cpu_setup(self, ci); 476 break; 477 default: 478 aprint_naive("\n"); 479 if (id >= CPU_MAXNUM) { 480 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 481 panic("cpuattach"); 482 } 483 #ifndef MULTIPROCESSOR 484 aprint_normal(" not configured\n"); 485 return NULL; 486 #else 487 mi_cpu_attach(ci); 488 break; 489 #endif 490 } 491 return (ci); 492 } 493 494 void 495 cpu_setup(device_t self, struct cpu_info *ci) 496 { 497 u_int pvr, vers; 498 const char * const xname = device_xname(self); 499 const char *bitmask; 500 char hidbuf[128]; 501 char model[80]; 502 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 503 char hidbuf_u[128]; 504 const char *bitmasku = NULL; 505 volatile uint64_t hid64_0, hid64_0_save; 506 #endif 507 #if !defined(_ARCH_PPC64) 508 register_t hid0 = 0, hid0_save = 0; 509 #endif 510 511 pvr = mfpvr(); 512 vers = (pvr >> 16) & 0xffff; 513 514 cpu_identify(model, sizeof(model)); 515 aprint_naive("\n"); 516 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 517 cpu_number() == 0 ? " (primary)" : ""); 518 519 /* set the cpu number */ 520 ci->ci_cpuid = cpu_number(); 521 #if defined(_ARCH_PPC64) 522 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 523 hid64_0_save = hid64_0; 524 #else 525 #if defined(PPC_OEA64_BRIDGE) 526 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 527 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 528 else 529 #endif 530 hid0_save = hid0 = mfspr(SPR_HID0); 531 #endif 532 533 534 cpu_probe_cache(); 535 536 /* 537 * Configure power-saving mode. 538 */ 539 switch (vers) { 540 #if !defined(_ARCH_PPC64) 541 case MPC604: 542 case MPC604e: 543 case MPC604ev: 544 /* 545 * Do not have HID0 support settings, but can support 546 * MSR[POW] off 547 */ 548 powersave = 1; 549 break; 550 551 case MPC603: 552 case MPC603e: 553 case MPC603ev: 554 case MPC7400: 555 case MPC7410: 556 case MPC8240: 557 case MPC8245: 558 case MPCG2: 559 /* Select DOZE mode. */ 560 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 561 hid0 |= HID0_DOZE | HID0_DPM; 562 powersave = 1; 563 break; 564 565 case MPC750: 566 case IBM750FX: 567 case IBM750GX: 568 /* Select NAP mode. */ 569 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 570 hid0 |= HID0_NAP | HID0_DPM; 571 powersave = 1; 572 break; 573 574 case MPC7447A: 575 case MPC7448: 576 case MPC7457: 577 case MPC7455: 578 case MPC7450: 579 /* Enable the 7450 branch caches */ 580 hid0 |= HID0_SGE | HID0_BTIC; 581 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 582 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 583 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 584 hid0 &= ~HID0_BTIC; 585 /* Select NAP mode. */ 586 hid0 &= ~HID0_SLEEP; 587 hid0 |= HID0_NAP | HID0_DPM; 588 powersave = 1; 589 break; 590 #endif 591 592 case IBM970: 593 case IBM970FX: 594 case IBM970MP: 595 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 596 #if !defined(_ARCH_PPC64) 597 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 598 #endif 599 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 600 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 601 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 602 powersave = 1; 603 break; 604 #endif 605 case IBMPOWER3II: 606 default: 607 /* No power-saving mode is available. */ ; 608 } 609 610 #ifdef NAPMODE 611 switch (vers) { 612 case IBM750FX: 613 case IBM750GX: 614 case MPC750: 615 case MPC7400: 616 /* Select NAP mode. */ 617 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 618 hid0 |= HID0_NAP; 619 break; 620 } 621 #endif 622 623 switch (vers) { 624 case IBM750FX: 625 case IBM750GX: 626 case MPC750: 627 hid0 &= ~HID0_DBP; /* XXX correct? */ 628 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 629 break; 630 631 case MPC7400: 632 case MPC7410: 633 hid0 &= ~HID0_SPD; 634 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 635 hid0 |= HID0_EIEC; 636 break; 637 } 638 639 /* 640 * according to the 603e manual this is necessary for an external L2 641 * cache to work properly 642 */ 643 switch (vers) { 644 case MPC603e: 645 hid0 |= HID0_ABE; 646 } 647 648 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 649 #if defined(PPC_OEA64_BRIDGE) 650 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 651 #endif 652 if (hid64_0 != hid64_0_save) { 653 mtspr64(SPR_HID0, hid64_0); 654 } 655 #if defined(PPC_OEA64_BRIDGE) 656 } else { 657 #endif 658 #endif 659 660 #if !defined(_ARCH_PPC64) 661 if (hid0 != hid0_save) { 662 mtspr(SPR_HID0, hid0); 663 __asm volatile("sync;isync"); 664 } 665 #endif 666 #if defined(PPC_OEA64_BRIDGE) 667 } 668 #endif 669 670 switch (vers) { 671 case MPC601: 672 bitmask = HID0_601_BITMASK; 673 break; 674 case MPC7447A: 675 case MPC7448: 676 case MPC7450: 677 case MPC7455: 678 case MPC7457: 679 bitmask = HID0_7450_BITMASK; 680 break; 681 case IBM970: 682 case IBM970FX: 683 case IBM970MP: 684 bitmask = HID0_970_BITMASK; 685 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 686 bitmasku = HID0_970_BITMASK_U; 687 #endif 688 break; 689 default: 690 bitmask = HID0_BITMASK; 691 break; 692 } 693 694 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 695 if (bitmasku != NULL) { 696 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 697 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 698 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 699 hidbuf_u, hidbuf, powersave); 700 } else 701 #endif 702 { 703 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 704 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 705 hidbuf, powersave); 706 } 707 708 ci->ci_khz = 0; 709 710 /* 711 * Display speed and cache configuration. 712 */ 713 switch (vers) { 714 case MPC604: 715 case MPC604e: 716 case MPC604ev: 717 case MPC750: 718 case IBM750FX: 719 case IBM750GX: 720 case MPC7400: 721 case MPC7410: 722 case MPC7447A: 723 case MPC7448: 724 case MPC7450: 725 case MPC7455: 726 case MPC7457: 727 aprint_normal_dev(self, ""); 728 cpu_probe_speed(ci); 729 aprint_normal("%u.%02u MHz", 730 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 731 switch (vers) { 732 case MPC7450: /* 7441 does not have L3! */ 733 case MPC7455: /* 7445 does not have L3! */ 734 case MPC7457: /* 7447 does not have L3! */ 735 cpu_config_l3cr(vers); 736 break; 737 case IBM750FX: 738 case IBM750GX: 739 case MPC750: 740 case MPC7400: 741 case MPC7410: 742 case MPC7447A: 743 case MPC7448: 744 cpu_config_l2cr(pvr); 745 break; 746 default: 747 break; 748 } 749 aprint_normal("\n"); 750 break; 751 } 752 753 #if NSYSMON_ENVSYS > 0 754 /* 755 * Attach MPC750 temperature sensor to the envsys subsystem. 756 * XXX the 74xx series also has this sensor, but it is not 757 * XXX supported by Motorola and may return values that are off by 758 * XXX 35-55 degrees C. 759 */ 760 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 761 cpu_tau_setup(ci); 762 #endif 763 764 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 765 if (vers == IBM970MP) 766 init_scom_speedctl(); 767 #endif 768 769 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 770 NULL, xname, "clock"); 771 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 772 NULL, xname, "traps"); 773 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 774 &ci->ci_ev_traps, xname, "kernel DSI traps"); 775 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 776 &ci->ci_ev_traps, xname, "user DSI traps"); 777 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 778 &ci->ci_ev_udsi, xname, "user DSI failures"); 779 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 780 &ci->ci_ev_traps, xname, "kernel ISI traps"); 781 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 782 &ci->ci_ev_traps, xname, "user ISI traps"); 783 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 784 &ci->ci_ev_isi, xname, "user ISI failures"); 785 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 786 &ci->ci_ev_traps, xname, "system call traps"); 787 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 788 &ci->ci_ev_traps, xname, "PGM traps"); 789 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 790 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 791 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 792 &ci->ci_ev_fpu, xname, "FPU context switches"); 793 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 794 &ci->ci_ev_traps, xname, "user alignment traps"); 795 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 796 &ci->ci_ev_ali, xname, "user alignment traps"); 797 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 798 &ci->ci_ev_umchk, xname, "user MCHK failures"); 799 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 800 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 801 #ifdef ALTIVEC 802 if (cpu_altivec) { 803 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 804 &ci->ci_ev_vec, xname, "AltiVec context switches"); 805 } 806 #endif 807 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 808 NULL, xname, "IPIs"); 809 } 810 811 /* 812 * According to a document labeled "PVR Register Settings": 813 ** For integrated microprocessors the PVR register inside the device 814 ** will identify the version of the microprocessor core. You must also 815 ** read the Device ID, PCI register 02, to identify the part and the 816 ** Revision ID, PCI register 08, to identify the revision of the 817 ** integrated microprocessor. 818 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 819 */ 820 821 void 822 cpu_identify(char *str, size_t len) 823 { 824 u_int pvr, major, minor; 825 uint16_t vers, rev, revfmt; 826 const struct cputab *cp; 827 size_t n; 828 829 pvr = mfpvr(); 830 vers = pvr >> 16; 831 rev = pvr; 832 833 switch (vers) { 834 case MPC7410: 835 minor = (pvr >> 0) & 0xff; 836 major = minor <= 4 ? 1 : 2; 837 break; 838 case MPCG2: /*XXX see note above */ 839 major = (pvr >> 4) & 0xf; 840 minor = (pvr >> 0) & 0xf; 841 break; 842 default: 843 major = (pvr >> 8) & 0xf; 844 minor = (pvr >> 0) & 0xf; 845 } 846 847 for (cp = models; cp->name[0] != '\0'; cp++) { 848 if (cp->version == vers) 849 break; 850 } 851 852 if (cpu == -1) 853 cpu = vers; 854 855 revfmt = cp->revfmt; 856 if (rev == MPC750 && pvr == 15) { 857 revfmt = REVFMT_HEX; 858 } 859 860 if (cp->name[0] != '\0') { 861 n = snprintf(str, len, "%s (Revision ", cp->name); 862 } else { 863 n = snprintf(str, len, "Version %#x (Revision ", vers); 864 } 865 if (len > n) { 866 switch (revfmt) { 867 case REVFMT_MAJMIN: 868 snprintf(str + n, len - n, "%u.%u)", major, minor); 869 break; 870 case REVFMT_HEX: 871 snprintf(str + n, len - n, "0x%04x)", rev); 872 break; 873 case REVFMT_DEC: 874 snprintf(str + n, len - n, "%u)", rev); 875 break; 876 } 877 } 878 } 879 880 #ifdef L2CR_CONFIG 881 u_int l2cr_config = L2CR_CONFIG; 882 #else 883 u_int l2cr_config = 0; 884 #endif 885 886 #ifdef L3CR_CONFIG 887 u_int l3cr_config = L3CR_CONFIG; 888 #else 889 u_int l3cr_config = 0; 890 #endif 891 892 void 893 cpu_enable_l2cr(register_t l2cr) 894 { 895 register_t msr, x; 896 uint16_t vers; 897 898 vers = mfpvr() >> 16; 899 900 /* Disable interrupts and set the cache config bits. */ 901 msr = mfmsr(); 902 mtmsr(msr & ~PSL_EE); 903 #ifdef ALTIVEC 904 if (cpu_altivec) 905 __asm volatile("dssall"); 906 #endif 907 __asm volatile("sync"); 908 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 909 __asm volatile("sync"); 910 911 /* Wait for L2 clock to be stable (640 L2 clocks). */ 912 delay(100); 913 914 /* Invalidate all L2 contents. */ 915 if (MPC745X_P(vers)) { 916 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 917 do { 918 x = mfspr(SPR_L2CR); 919 } while (x & L2CR_L2I); 920 } else { 921 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 922 do { 923 x = mfspr(SPR_L2CR); 924 } while (x & L2CR_L2IP); 925 } 926 /* Enable L2 cache. */ 927 l2cr |= L2CR_L2E; 928 mtspr(SPR_L2CR, l2cr); 929 mtmsr(msr); 930 } 931 932 void 933 cpu_enable_l3cr(register_t l3cr) 934 { 935 register_t x; 936 937 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 938 939 /* 940 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 941 * L3CLKEN. (also mask off reserved bits in case they were included 942 * in L3CR_CONFIG) 943 */ 944 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 945 mtspr(SPR_L3CR, l3cr); 946 947 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 948 l3cr |= 0x04000000; 949 mtspr(SPR_L3CR, l3cr); 950 951 /* 3: Set L3CLKEN to 1*/ 952 l3cr |= L3CR_L3CLKEN; 953 mtspr(SPR_L3CR, l3cr); 954 955 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 956 __asm volatile("dssall;sync"); 957 /* L3 cache is already disabled, no need to clear L3E */ 958 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 959 do { 960 x = mfspr(SPR_L3CR); 961 } while (x & L3CR_L3I); 962 963 /* 6: Clear L3CLKEN to 0 */ 964 l3cr &= ~L3CR_L3CLKEN; 965 mtspr(SPR_L3CR, l3cr); 966 967 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 968 __asm volatile("sync"); 969 delay(100); 970 971 /* 8: Set L3E and L3CLKEN */ 972 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 973 mtspr(SPR_L3CR, l3cr); 974 975 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 976 __asm volatile("sync"); 977 delay(100); 978 } 979 980 void 981 cpu_config_l2cr(int pvr) 982 { 983 register_t l2cr; 984 u_int vers = (pvr >> 16) & 0xffff; 985 986 l2cr = mfspr(SPR_L2CR); 987 988 /* 989 * For MP systems, the firmware may only configure the L2 cache 990 * on the first CPU. In this case, assume that the other CPUs 991 * should use the same value for L2CR. 992 */ 993 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 994 l2cr_config = l2cr; 995 } 996 997 /* 998 * Configure L2 cache if not enabled. 999 */ 1000 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1001 cpu_enable_l2cr(l2cr_config); 1002 l2cr = mfspr(SPR_L2CR); 1003 } 1004 1005 if ((l2cr & L2CR_L2E) == 0) { 1006 aprint_normal(" L2 cache present but not enabled "); 1007 return; 1008 } 1009 aprint_normal(","); 1010 1011 switch (vers) { 1012 case IBM750FX: 1013 case IBM750GX: 1014 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1015 break; 1016 case MPC750: 1017 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1018 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1019 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1020 else 1021 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1022 break; 1023 case MPC7447A: 1024 case MPC7457: 1025 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1026 return; 1027 case MPC7448: 1028 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1029 return; 1030 case MPC7450: 1031 case MPC7455: 1032 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1033 break; 1034 default: 1035 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1036 break; 1037 } 1038 } 1039 1040 void 1041 cpu_config_l3cr(int vers) 1042 { 1043 register_t l2cr; 1044 register_t l3cr; 1045 1046 l2cr = mfspr(SPR_L2CR); 1047 1048 /* 1049 * For MP systems, the firmware may only configure the L2 cache 1050 * on the first CPU. In this case, assume that the other CPUs 1051 * should use the same value for L2CR. 1052 */ 1053 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1054 l2cr_config = l2cr; 1055 } 1056 1057 /* 1058 * Configure L2 cache if not enabled. 1059 */ 1060 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1061 cpu_enable_l2cr(l2cr_config); 1062 l2cr = mfspr(SPR_L2CR); 1063 } 1064 1065 aprint_normal(","); 1066 switch (vers) { 1067 case MPC7447A: 1068 case MPC7457: 1069 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1070 return; 1071 case MPC7448: 1072 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1073 return; 1074 default: 1075 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1076 break; 1077 } 1078 1079 l3cr = mfspr(SPR_L3CR); 1080 1081 /* 1082 * For MP systems, the firmware may only configure the L3 cache 1083 * on the first CPU. In this case, assume that the other CPUs 1084 * should use the same value for L3CR. 1085 */ 1086 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1087 l3cr_config = l3cr; 1088 } 1089 1090 /* 1091 * Configure L3 cache if not enabled. 1092 */ 1093 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1094 cpu_enable_l3cr(l3cr_config); 1095 l3cr = mfspr(SPR_L3CR); 1096 } 1097 1098 if (l3cr & L3CR_L3E) { 1099 aprint_normal(","); 1100 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1101 } 1102 } 1103 1104 void 1105 cpu_probe_speed(struct cpu_info *ci) 1106 { 1107 uint64_t cps; 1108 1109 mtspr(SPR_MMCR0, MMCR0_FC); 1110 mtspr(SPR_PMC1, 0); 1111 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1112 delay(100000); 1113 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1114 1115 mtspr(SPR_MMCR0, MMCR0_FC); 1116 1117 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1118 } 1119 1120 /* 1121 * Read the Dynamic Frequency Switching state and return a divisor for 1122 * the maximum frequency. 1123 */ 1124 int 1125 cpu_get_dfs(void) 1126 { 1127 u_int pvr, vers; 1128 1129 pvr = mfpvr(); 1130 vers = pvr >> 16; 1131 1132 switch (vers) { 1133 case MPC7448: 1134 if (mfspr(SPR_HID1) & HID1_DFS4) 1135 return 4; 1136 /* FALLTHROUGH */ 1137 case MPC7447A: 1138 if (mfspr(SPR_HID1) & HID1_DFS2) 1139 return 2; 1140 } 1141 return 1; 1142 } 1143 1144 /* 1145 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1146 */ 1147 void 1148 cpu_set_dfs(int div) 1149 { 1150 u_int dfs_mask, pvr, vers; 1151 1152 pvr = mfpvr(); 1153 vers = pvr >> 16; 1154 dfs_mask = 0; 1155 1156 switch (vers) { 1157 case MPC7448: 1158 dfs_mask |= HID1_DFS4; 1159 /* FALLTHROUGH */ 1160 case MPC7447A: 1161 dfs_mask |= HID1_DFS2; 1162 break; 1163 default: 1164 printf("cpu_set_dfs: DFS not supported\n"); 1165 return; 1166 1167 } 1168 #ifdef MULTIPROCESSOR 1169 uint64_t where; 1170 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1171 xc_wait(where); 1172 #else 1173 cpu_set_dfs_xcall(&div, &dfs_mask); 1174 #endif 1175 } 1176 1177 static void 1178 cpu_set_dfs_xcall(void *arg1, void *arg2) 1179 { 1180 u_int dfs_mask, hid1, old_hid1; 1181 int *divisor, s; 1182 1183 divisor = arg1; 1184 dfs_mask = *(u_int *)arg2; 1185 1186 s = splhigh(); 1187 hid1 = old_hid1 = mfspr(SPR_HID1); 1188 1189 switch (*divisor) { 1190 case 1: 1191 hid1 &= ~dfs_mask; 1192 break; 1193 case 2: 1194 hid1 &= ~(dfs_mask & HID1_DFS4); 1195 hid1 |= dfs_mask & HID1_DFS2; 1196 break; 1197 case 4: 1198 hid1 &= ~(dfs_mask & HID1_DFS2); 1199 hid1 |= dfs_mask & HID1_DFS4; 1200 break; 1201 } 1202 1203 if (hid1 != old_hid1) { 1204 __asm volatile("sync"); 1205 mtspr(SPR_HID1, hid1); 1206 __asm volatile("sync;isync"); 1207 } 1208 1209 splx(s); 1210 } 1211 1212 #if NSYSMON_ENVSYS > 0 1213 void 1214 cpu_tau_setup(struct cpu_info *ci) 1215 { 1216 struct sysmon_envsys *sme; 1217 int error, therm_delay; 1218 1219 mtspr(SPR_THRM1, SPR_THRM_VALID); 1220 mtspr(SPR_THRM2, 0); 1221 1222 /* 1223 * we need to figure out how much 20+us in units of CPU clock cycles 1224 * are 1225 */ 1226 1227 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1228 1229 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1230 1231 sme = sysmon_envsys_create(); 1232 1233 sensor.units = ENVSYS_STEMP; 1234 sensor.state = ENVSYS_SINVALID; 1235 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1236 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1237 sysmon_envsys_destroy(sme); 1238 return; 1239 } 1240 1241 sme->sme_name = device_xname(ci->ci_dev); 1242 sme->sme_cookie = ci; 1243 sme->sme_refresh = cpu_tau_refresh; 1244 1245 if ((error = sysmon_envsys_register(sme)) != 0) { 1246 aprint_error_dev(ci->ci_dev, 1247 " unable to register with sysmon (%d)\n", error); 1248 sysmon_envsys_destroy(sme); 1249 } 1250 } 1251 1252 /* Find the temperature of the CPU. */ 1253 void 1254 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1255 { 1256 int i, threshold, count; 1257 1258 threshold = 64; /* Half of the 7-bit sensor range */ 1259 1260 /* Successive-approximation code adapted from Motorola 1261 * application note AN1800/D, "Programming the Thermal Assist 1262 * Unit in the MPC750 Microprocessor". 1263 */ 1264 for (i = 5; i >= 0 ; i--) { 1265 mtspr(SPR_THRM1, 1266 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1267 count = 0; 1268 while ((count < 100000) && 1269 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1270 count++; 1271 delay(1); 1272 } 1273 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1274 /* The interrupt bit was set, meaning the 1275 * temperature was above the threshold 1276 */ 1277 threshold += 1 << i; 1278 } else { 1279 /* Temperature was below the threshold */ 1280 threshold -= 1 << i; 1281 } 1282 } 1283 threshold += 2; 1284 1285 /* Convert the temperature in degrees C to microkelvin */ 1286 edata->value_cur = (threshold * 1000000) + 273150000; 1287 edata->state = ENVSYS_SVALID; 1288 } 1289 #endif /* NSYSMON_ENVSYS > 0 */ 1290 1291 #ifdef MULTIPROCESSOR 1292 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1293 1294 int 1295 cpu_spinup(device_t self, struct cpu_info *ci) 1296 { 1297 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1298 struct pglist mlist; 1299 int i, error; 1300 char *hp; 1301 1302 KASSERT(ci != curcpu()); 1303 1304 /* Now allocate a hatch stack */ 1305 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1306 &mlist, 1, 1); 1307 if (error) { 1308 aprint_error(": unable to allocate hatch stack\n"); 1309 return -1; 1310 } 1311 1312 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1313 memset(hp, 0, HATCH_STACK_SIZE); 1314 1315 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1316 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1317 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1318 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1319 1320 cpu_hatch_data = h; 1321 h->hatch_running = 0; 1322 h->hatch_self = self; 1323 h->hatch_ci = ci; 1324 h->hatch_pir = ci->ci_cpuid; 1325 1326 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1327 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1328 1329 /* copy special registers */ 1330 1331 h->hatch_hid0 = mfspr(SPR_HID0); 1332 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1333 h->hatch_hid1 = mfspr(SPR_HID1); 1334 h->hatch_hid4 = mfspr(SPR_HID4); 1335 h->hatch_hid5 = mfspr(SPR_HID5); 1336 #endif 1337 1338 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1339 for (i = 0; i < 16; i++) { 1340 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1341 "r"(i << ADDR_SR_SHFT)); 1342 } 1343 if (oeacpufeat & OEACPU_64) 1344 h->hatch_asr = mfspr(SPR_ASR); 1345 else 1346 h->hatch_asr = 0; 1347 1348 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1349 /* copy the bat regs */ 1350 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1351 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1352 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1353 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1354 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1355 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1356 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1357 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1358 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1359 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1360 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1361 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1362 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1363 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1364 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1365 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1366 __asm volatile ("sync; isync"); 1367 } 1368 1369 if (md_setup_trampoline(h, ci) == -1) 1370 return -1; 1371 md_presync_timebase(h); 1372 md_start_timebase(h); 1373 1374 /* wait for secondary printf */ 1375 1376 delay(200000); 1377 1378 #ifdef CACHE_PROTO_MEI 1379 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1380 __asm volatile ("sync; isync"); 1381 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1382 __asm volatile ("sync; isync"); 1383 #endif 1384 if (h->hatch_running < 1) { 1385 #ifdef CACHE_PROTO_MEI 1386 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1387 __asm volatile ("sync; isync"); 1388 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1389 __asm volatile ("sync; isync"); 1390 #endif 1391 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1392 ci->ci_cpuid, cpu_spinstart_ack); 1393 Debugger(); 1394 return -1; 1395 } 1396 1397 /* Register IPI Interrupt */ 1398 if (ipiops.ppc_establish_ipi) 1399 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1400 1401 return 0; 1402 } 1403 1404 static volatile int start_secondary_cpu; 1405 1406 register_t 1407 cpu_hatch(void) 1408 { 1409 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1410 struct cpu_info * const ci = h->hatch_ci; 1411 struct pcb *pcb; 1412 u_int msr; 1413 int i; 1414 1415 /* Initialize timebase. */ 1416 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1417 1418 /* 1419 * Set PIR (Processor Identification Register). i.e. whoami 1420 * Note that PIR is read-only on some CPU versions, so we write to it 1421 * only if it has a different value than we need. 1422 */ 1423 1424 msr = mfspr(SPR_PIR); 1425 if (msr != h->hatch_pir) 1426 mtspr(SPR_PIR, h->hatch_pir); 1427 1428 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1429 curlwp = ci->ci_curlwp; 1430 cpu_spinstart_ack = 0; 1431 1432 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1433 /* Initialize MMU. */ 1434 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1435 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1436 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1437 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1438 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1439 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1440 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1441 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1442 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1443 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1444 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1445 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1446 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1447 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1448 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1449 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1450 } 1451 1452 #ifdef PPC_OEA64_BRIDGE 1453 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1454 1455 mtspr64(SPR_HID0, h->hatch_hid0); 1456 mtspr64(SPR_HID1, h->hatch_hid1); 1457 mtspr64(SPR_HID4, h->hatch_hid4); 1458 mtspr64(SPR_HID5, h->hatch_hid5); 1459 mtspr64(SPR_HIOR, 0); 1460 } else 1461 #endif 1462 mtspr(SPR_HID0, h->hatch_hid0); 1463 1464 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1465 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1466 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1467 } 1468 1469 __asm volatile ("sync"); 1470 for (i = 0; i < 16; i++) 1471 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1472 __asm volatile ("sync; isync"); 1473 1474 if (oeacpufeat & OEACPU_64) 1475 mtspr(SPR_ASR, h->hatch_asr); 1476 1477 cpu_spinstart_ack = 1; 1478 __asm ("ptesync"); 1479 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1480 __asm volatile ("sync; isync"); 1481 1482 cpu_spinstart_ack = 5; 1483 for (i = 0; i < 16; i++) 1484 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1485 "r"(i << ADDR_SR_SHFT)); 1486 1487 /* Enable I/D address translations. */ 1488 msr = mfmsr(); 1489 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1490 mtmsr(msr); 1491 __asm volatile ("sync; isync"); 1492 cpu_spinstart_ack = 2; 1493 1494 md_sync_timebase(h); 1495 1496 cpu_setup(h->hatch_self, ci); 1497 1498 h->hatch_running = 1; 1499 __asm volatile ("sync; isync"); 1500 1501 while (start_secondary_cpu == 0) 1502 ; 1503 1504 __asm volatile ("sync; isync"); 1505 1506 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1507 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1508 1509 md_setup_interrupts(); 1510 1511 ci->ci_ipending = 0; 1512 ci->ci_cpl = 0; 1513 1514 mtmsr(mfmsr() | PSL_EE); 1515 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1516 return pcb->pcb_sp; 1517 } 1518 1519 void 1520 cpu_boot_secondary_processors(void) 1521 { 1522 start_secondary_cpu = 1; 1523 __asm volatile ("sync"); 1524 } 1525 1526 #endif /*MULTIPROCESSOR*/ 1527