1 /* $NetBSD: cpu_subr.c,v 1.66 2011/06/17 19:03:04 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.66 2011/06/17 19:03:04 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/malloc.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/spr.h> 56 #include <powerpc/oea/hid.h> 57 #include <powerpc/oea/hid_601.h> 58 #include <powerpc/oea/spr.h> 59 #include <powerpc/oea/cpufeat.h> 60 61 #include <dev/sysmon/sysmonvar.h> 62 63 static void cpu_enable_l2cr(register_t); 64 static void cpu_enable_l3cr(register_t); 65 static void cpu_config_l2cr(int); 66 static void cpu_config_l3cr(int); 67 static void cpu_probe_speed(struct cpu_info *); 68 static void cpu_idlespin(void); 69 static void cpu_set_dfs_xcall(void *, void *); 70 #if NSYSMON_ENVSYS > 0 71 static void cpu_tau_setup(struct cpu_info *); 72 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 73 #endif 74 75 int cpu; 76 int ncpus; 77 78 struct fmttab { 79 register_t fmt_mask; 80 register_t fmt_value; 81 const char *fmt_string; 82 }; 83 84 /* 85 * This should be one per CPU but since we only support it on 750 variants it 86 * doesn't realy matter since none of them supports SMP 87 */ 88 envsys_data_t sensor; 89 90 static const struct fmttab cpu_7450_l2cr_formats[] = { 91 { L2CR_L2E, 0, " disabled" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 95 { L2CR_L2E, ~0, " 256KB L2 cache" }, 96 { L2CR_L2PE, 0, " no parity" }, 97 { L2CR_L2PE, ~0, " parity enabled" }, 98 { 0, 0, NULL } 99 }; 100 101 static const struct fmttab cpu_7448_l2cr_formats[] = { 102 { L2CR_L2E, 0, " disabled" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 106 { L2CR_L2E, ~0, " 1MB L2 cache" }, 107 { L2CR_L2PE, 0, " no parity" }, 108 { L2CR_L2PE, ~0, " parity enabled" }, 109 { 0, 0, NULL } 110 }; 111 112 static const struct fmttab cpu_7457_l2cr_formats[] = { 113 { L2CR_L2E, 0, " disabled" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 117 { L2CR_L2E, ~0, " 512KB L2 cache" }, 118 { L2CR_L2PE, 0, " no parity" }, 119 { L2CR_L2PE, ~0, " parity enabled" }, 120 { 0, 0, NULL } 121 }; 122 123 static const struct fmttab cpu_7450_l3cr_formats[] = { 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 127 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 128 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 133 { L3CR_L3SIZ, ~0, " L3 cache" }, 134 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 135 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 136 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 137 { L3CR_L3CLK, ~0, " at" }, 138 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 139 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 140 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 141 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 142 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 143 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 144 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 145 { L3CR_L3CLK, ~0, " ratio" }, 146 { 0, 0, NULL }, 147 }; 148 149 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 150 { L2CR_L2E, 0, " disabled" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 154 { 0, ~0, " 512KB" }, 155 { L2CR_L2WT, L2CR_L2WT, " WT" }, 156 { L2CR_L2WT, 0, " WB" }, 157 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 158 { 0, ~0, " L2 cache" }, 159 { 0, 0, NULL } 160 }; 161 162 static const struct fmttab cpu_l2cr_formats[] = { 163 { L2CR_L2E, 0, " disabled" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 167 { L2CR_L2PE, L2CR_L2PE, " parity" }, 168 { L2CR_L2PE, 0, " no-parity" }, 169 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 170 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 171 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 172 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 173 { L2CR_L2WT, L2CR_L2WT, " WT" }, 174 { L2CR_L2WT, 0, " WB" }, 175 { L2CR_L2E, ~0, " L2 cache" }, 176 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 177 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 179 { L2CR_L2CLK, ~0, " at" }, 180 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 181 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 182 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 183 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 184 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 185 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 186 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 187 { L2CR_L2CLK, ~0, " ratio" }, 188 { 0, 0, NULL } 189 }; 190 191 static void cpu_fmttab_print(const struct fmttab *, register_t); 192 193 struct cputab { 194 const char name[8]; 195 uint16_t version; 196 uint16_t revfmt; 197 }; 198 #define REVFMT_MAJMIN 1 /* %u.%u */ 199 #define REVFMT_HEX 2 /* 0x%04x */ 200 #define REVFMT_DEC 3 /* %u */ 201 static const struct cputab models[] = { 202 { "601", MPC601, REVFMT_DEC }, 203 { "602", MPC602, REVFMT_DEC }, 204 { "603", MPC603, REVFMT_MAJMIN }, 205 { "603e", MPC603e, REVFMT_MAJMIN }, 206 { "603ev", MPC603ev, REVFMT_MAJMIN }, 207 { "G2", MPCG2, REVFMT_MAJMIN }, 208 { "604", MPC604, REVFMT_MAJMIN }, 209 { "604e", MPC604e, REVFMT_MAJMIN }, 210 { "604ev", MPC604ev, REVFMT_MAJMIN }, 211 { "620", MPC620, REVFMT_HEX }, 212 { "750", MPC750, REVFMT_MAJMIN }, 213 { "750FX", IBM750FX, REVFMT_MAJMIN }, 214 { "750GX", IBM750GX, REVFMT_MAJMIN }, 215 { "7400", MPC7400, REVFMT_MAJMIN }, 216 { "7410", MPC7410, REVFMT_MAJMIN }, 217 { "7450", MPC7450, REVFMT_MAJMIN }, 218 { "7455", MPC7455, REVFMT_MAJMIN }, 219 { "7457", MPC7457, REVFMT_MAJMIN }, 220 { "7447A", MPC7447A, REVFMT_MAJMIN }, 221 { "7448", MPC7448, REVFMT_MAJMIN }, 222 { "8240", MPC8240, REVFMT_MAJMIN }, 223 { "8245", MPC8245, REVFMT_MAJMIN }, 224 { "970", IBM970, REVFMT_MAJMIN }, 225 { "970FX", IBM970FX, REVFMT_MAJMIN }, 226 { "970MP", IBM970MP, REVFMT_MAJMIN }, 227 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 228 { "", 0, REVFMT_HEX } 229 }; 230 231 #ifdef MULTIPROCESSOR 232 struct cpu_info cpu_info[CPU_MAXNUM] = { 233 [0] = { 234 .ci_curlwp = &lwp0, 235 }, 236 }; 237 volatile struct cpu_hatch_data *cpu_hatch_data; 238 volatile int cpu_hatch_stack; 239 extern int ticks_per_intr; 240 #include <powerpc/oea/bat.h> 241 #include <arch/powerpc/pic/picvar.h> 242 #include <arch/powerpc/pic/ipivar.h> 243 extern struct bat battable[]; 244 #else 245 struct cpu_info cpu_info[1] = { 246 [0] = { 247 .ci_curlwp = &lwp0, 248 }, 249 }; 250 #endif /*MULTIPROCESSOR*/ 251 252 int cpu_altivec; 253 int cpu_psluserset, cpu_pslusermod; 254 char cpu_model[80]; 255 256 /* This is to be called from locore.S, and nowhere else. */ 257 258 void 259 cpu_model_init(void) 260 { 261 u_int pvr, vers; 262 263 pvr = mfpvr(); 264 vers = pvr >> 16; 265 266 oeacpufeat = 0; 267 268 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 269 vers == IBMCELL || vers == IBMPOWER6P5) 270 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 271 272 else if (vers == MPC601) 273 oeacpufeat |= OEACPU_601; 274 275 else if (MPC745X_P(vers) && vers != MPC7450) 276 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 277 278 else if (vers == IBM750FX || vers == IBM750GX) 279 oeacpufeat |= OEACPU_HIGHBAT; 280 } 281 282 void 283 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 284 { 285 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 286 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 287 (data & fmt->fmt_mask) == fmt->fmt_value) 288 aprint_normal("%s", fmt->fmt_string); 289 } 290 } 291 292 void 293 cpu_idlespin(void) 294 { 295 register_t msr; 296 297 if (powersave <= 0) 298 return; 299 300 __asm volatile( 301 "sync;" 302 "mfmsr %0;" 303 "oris %0,%0,%1@h;" /* enter power saving mode */ 304 "mtmsr %0;" 305 "isync;" 306 : "=r"(msr) 307 : "J"(PSL_POW)); 308 } 309 310 void 311 cpu_probe_cache(void) 312 { 313 u_int assoc, pvr, vers; 314 315 pvr = mfpvr(); 316 vers = pvr >> 16; 317 318 319 /* Presently common across almost all implementations. */ 320 curcpu()->ci_ci.dcache_line_size = 32; 321 curcpu()->ci_ci.icache_line_size = 32; 322 323 324 switch (vers) { 325 #define K *1024 326 case IBM750FX: 327 case IBM750GX: 328 case MPC601: 329 case MPC750: 330 case MPC7400: 331 case MPC7447A: 332 case MPC7448: 333 case MPC7450: 334 case MPC7455: 335 case MPC7457: 336 curcpu()->ci_ci.dcache_size = 32 K; 337 curcpu()->ci_ci.icache_size = 32 K; 338 assoc = 8; 339 break; 340 case MPC603: 341 curcpu()->ci_ci.dcache_size = 8 K; 342 curcpu()->ci_ci.icache_size = 8 K; 343 assoc = 2; 344 break; 345 case MPC603e: 346 case MPC603ev: 347 case MPC604: 348 case MPC8240: 349 case MPC8245: 350 case MPCG2: 351 curcpu()->ci_ci.dcache_size = 16 K; 352 curcpu()->ci_ci.icache_size = 16 K; 353 assoc = 4; 354 break; 355 case MPC604e: 356 case MPC604ev: 357 curcpu()->ci_ci.dcache_size = 32 K; 358 curcpu()->ci_ci.icache_size = 32 K; 359 assoc = 4; 360 break; 361 case IBMPOWER3II: 362 curcpu()->ci_ci.dcache_size = 64 K; 363 curcpu()->ci_ci.icache_size = 32 K; 364 curcpu()->ci_ci.dcache_line_size = 128; 365 curcpu()->ci_ci.icache_line_size = 128; 366 assoc = 128; /* not a typo */ 367 break; 368 case IBM970: 369 case IBM970FX: 370 case IBM970MP: 371 curcpu()->ci_ci.dcache_size = 32 K; 372 curcpu()->ci_ci.icache_size = 64 K; 373 curcpu()->ci_ci.dcache_line_size = 128; 374 curcpu()->ci_ci.icache_line_size = 128; 375 assoc = 2; 376 break; 377 378 default: 379 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 380 curcpu()->ci_ci.icache_size = PAGE_SIZE; 381 assoc = 1; 382 #undef K 383 } 384 385 /* 386 * Possibly recolor. 387 */ 388 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 389 } 390 391 struct cpu_info * 392 cpu_attach_common(device_t self, int id) 393 { 394 struct cpu_info *ci; 395 u_int pvr, vers; 396 397 ci = &cpu_info[id]; 398 #ifndef MULTIPROCESSOR 399 /* 400 * If this isn't the primary CPU, print an error message 401 * and just bail out. 402 */ 403 if (id != 0) { 404 aprint_normal(": ID %d\n", id); 405 aprint_normal_dev(self, 406 "processor off-line; " 407 "multiprocessor support not present in kernel\n"); 408 return (NULL); 409 } 410 #endif 411 412 ci->ci_cpuid = id; 413 ci->ci_idepth = -1; 414 ci->ci_dev = self; 415 ci->ci_idlespin = cpu_idlespin; 416 417 pvr = mfpvr(); 418 vers = (pvr >> 16) & 0xffff; 419 420 switch (id) { 421 case 0: 422 /* load my cpu_number to PIR */ 423 switch (vers) { 424 case MPC601: 425 case MPC604: 426 case MPC604e: 427 case MPC604ev: 428 case MPC7400: 429 case MPC7410: 430 case MPC7447A: 431 case MPC7448: 432 case MPC7450: 433 case MPC7455: 434 case MPC7457: 435 mtspr(SPR_PIR, id); 436 } 437 cpu_setup(self, ci); 438 break; 439 default: 440 if (id >= CPU_MAXNUM) { 441 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 442 panic("cpuattach"); 443 } 444 #ifndef MULTIPROCESSOR 445 aprint_normal(" not configured\n"); 446 return NULL; 447 #else 448 mi_cpu_attach(ci); 449 break; 450 #endif 451 } 452 return (ci); 453 } 454 455 void 456 cpu_setup(device_t self, struct cpu_info *ci) 457 { 458 u_int hid0, hid0_save, pvr, vers; 459 const char * const xname = device_xname(self); 460 const char *bitmask; 461 char hidbuf[128]; 462 char model[80]; 463 464 pvr = mfpvr(); 465 vers = (pvr >> 16) & 0xffff; 466 467 cpu_identify(model, sizeof(model)); 468 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 469 cpu_number() == 0 ? " (primary)" : ""); 470 471 /* set the cpu number */ 472 ci->ci_cpuid = cpu_number(); 473 hid0_save = hid0 = mfspr(SPR_HID0); 474 475 cpu_probe_cache(); 476 477 /* 478 * Configure power-saving mode. 479 */ 480 switch (vers) { 481 case MPC604: 482 case MPC604e: 483 case MPC604ev: 484 /* 485 * Do not have HID0 support settings, but can support 486 * MSR[POW] off 487 */ 488 powersave = 1; 489 break; 490 491 case MPC603: 492 case MPC603e: 493 case MPC603ev: 494 case MPC7400: 495 case MPC7410: 496 case MPC8240: 497 case MPC8245: 498 case MPCG2: 499 /* Select DOZE mode. */ 500 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 501 hid0 |= HID0_DOZE | HID0_DPM; 502 powersave = 1; 503 break; 504 505 case MPC750: 506 case IBM750FX: 507 case IBM750GX: 508 /* Select NAP mode. */ 509 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 510 hid0 |= HID0_NAP | HID0_DPM; 511 powersave = 1; 512 break; 513 514 case MPC7447A: 515 case MPC7448: 516 case MPC7457: 517 case MPC7455: 518 case MPC7450: 519 /* Enable the 7450 branch caches */ 520 hid0 |= HID0_SGE | HID0_BTIC; 521 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 522 /* Enable more and larger BAT registers */ 523 if (oeacpufeat & OEACPU_XBSEN) 524 hid0 |= HID0_XBSEN; 525 if (oeacpufeat & OEACPU_HIGHBAT) 526 hid0 |= HID0_HIGH_BAT_EN; 527 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 528 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 529 hid0 &= ~HID0_BTIC; 530 /* Select NAP mode. */ 531 hid0 &= ~HID0_SLEEP; 532 hid0 |= HID0_NAP | HID0_DPM; 533 powersave = 1; 534 break; 535 536 case IBM970: 537 case IBM970FX: 538 case IBM970MP: 539 case IBMPOWER3II: 540 default: 541 /* No power-saving mode is available. */ ; 542 } 543 544 #ifdef NAPMODE 545 switch (vers) { 546 case IBM750FX: 547 case IBM750GX: 548 case MPC750: 549 case MPC7400: 550 /* Select NAP mode. */ 551 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 552 hid0 |= HID0_NAP; 553 break; 554 } 555 #endif 556 557 switch (vers) { 558 case IBM750FX: 559 case IBM750GX: 560 case MPC750: 561 hid0 &= ~HID0_DBP; /* XXX correct? */ 562 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 563 break; 564 565 case MPC7400: 566 case MPC7410: 567 hid0 &= ~HID0_SPD; 568 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 569 hid0 |= HID0_EIEC; 570 break; 571 } 572 573 if (hid0 != hid0_save) { 574 mtspr(SPR_HID0, hid0); 575 __asm volatile("sync;isync"); 576 } 577 578 579 switch (vers) { 580 case MPC601: 581 bitmask = HID0_601_BITMASK; 582 break; 583 case MPC7450: 584 case MPC7455: 585 case MPC7457: 586 bitmask = HID0_7450_BITMASK; 587 break; 588 case IBM970: 589 case IBM970FX: 590 case IBM970MP: 591 bitmask = 0; 592 break; 593 default: 594 bitmask = HID0_BITMASK; 595 break; 596 } 597 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 598 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 599 600 ci->ci_khz = 0; 601 602 /* 603 * Display speed and cache configuration. 604 */ 605 switch (vers) { 606 case MPC604: 607 case MPC604e: 608 case MPC604ev: 609 case MPC750: 610 case IBM750FX: 611 case IBM750GX: 612 case MPC7400: 613 case MPC7410: 614 case MPC7447A: 615 case MPC7448: 616 case MPC7450: 617 case MPC7455: 618 case MPC7457: 619 aprint_normal_dev(self, ""); 620 cpu_probe_speed(ci); 621 aprint_normal("%u.%02u MHz", 622 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 623 switch (vers) { 624 case MPC7450: /* 7441 does not have L3! */ 625 case MPC7455: /* 7445 does not have L3! */ 626 case MPC7457: /* 7447 does not have L3! */ 627 cpu_config_l3cr(vers); 628 break; 629 case IBM750FX: 630 case IBM750GX: 631 case MPC750: 632 case MPC7400: 633 case MPC7410: 634 case MPC7447A: 635 case MPC7448: 636 cpu_config_l2cr(pvr); 637 break; 638 default: 639 break; 640 } 641 aprint_normal("\n"); 642 break; 643 } 644 645 #if NSYSMON_ENVSYS > 0 646 /* 647 * Attach MPC750 temperature sensor to the envsys subsystem. 648 * XXX the 74xx series also has this sensor, but it is not 649 * XXX supported by Motorola and may return values that are off by 650 * XXX 35-55 degrees C. 651 */ 652 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 653 cpu_tau_setup(ci); 654 #endif 655 656 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 657 NULL, xname, "clock"); 658 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 659 NULL, xname, "soft clock"); 660 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 661 NULL, xname, "soft net"); 662 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 663 NULL, xname, "soft serial"); 664 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 665 NULL, xname, "traps"); 666 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 667 &ci->ci_ev_traps, xname, "kernel DSI traps"); 668 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 669 &ci->ci_ev_traps, xname, "user DSI traps"); 670 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 671 &ci->ci_ev_udsi, xname, "user DSI failures"); 672 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 673 &ci->ci_ev_traps, xname, "kernel ISI traps"); 674 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 675 &ci->ci_ev_traps, xname, "user ISI traps"); 676 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 677 &ci->ci_ev_isi, xname, "user ISI failures"); 678 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 679 &ci->ci_ev_traps, xname, "system call traps"); 680 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 681 &ci->ci_ev_traps, xname, "PGM traps"); 682 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 683 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 684 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 685 &ci->ci_ev_fpu, xname, "FPU context switches"); 686 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 687 &ci->ci_ev_traps, xname, "user alignment traps"); 688 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 689 &ci->ci_ev_ali, xname, "user alignment traps"); 690 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 691 &ci->ci_ev_umchk, xname, "user MCHK failures"); 692 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 693 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 694 #ifdef ALTIVEC 695 if (cpu_altivec) { 696 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 697 &ci->ci_ev_vec, xname, "AltiVec context switches"); 698 } 699 #endif 700 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 701 NULL, xname, "IPIs"); 702 } 703 704 /* 705 * According to a document labeled "PVR Register Settings": 706 ** For integrated microprocessors the PVR register inside the device 707 ** will identify the version of the microprocessor core. You must also 708 ** read the Device ID, PCI register 02, to identify the part and the 709 ** Revision ID, PCI register 08, to identify the revision of the 710 ** integrated microprocessor. 711 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 712 */ 713 714 void 715 cpu_identify(char *str, size_t len) 716 { 717 u_int pvr, major, minor; 718 uint16_t vers, rev, revfmt; 719 const struct cputab *cp; 720 const char *name; 721 size_t n; 722 723 pvr = mfpvr(); 724 vers = pvr >> 16; 725 rev = pvr; 726 727 switch (vers) { 728 case MPC7410: 729 minor = (pvr >> 0) & 0xff; 730 major = minor <= 4 ? 1 : 2; 731 break; 732 case MPCG2: /*XXX see note above */ 733 major = (pvr >> 4) & 0xf; 734 minor = (pvr >> 0) & 0xf; 735 break; 736 default: 737 major = (pvr >> 8) & 0xf; 738 minor = (pvr >> 0) & 0xf; 739 } 740 741 for (cp = models; cp->name[0] != '\0'; cp++) { 742 if (cp->version == vers) 743 break; 744 } 745 746 if (str == NULL) { 747 str = cpu_model; 748 len = sizeof(cpu_model); 749 cpu = vers; 750 } 751 752 revfmt = cp->revfmt; 753 name = cp->name; 754 if (rev == MPC750 && pvr == 15) { 755 name = "755"; 756 revfmt = REVFMT_HEX; 757 } 758 759 if (cp->name[0] != '\0') { 760 n = snprintf(str, len, "%s (Revision ", cp->name); 761 } else { 762 n = snprintf(str, len, "Version %#x (Revision ", vers); 763 } 764 if (len > n) { 765 switch (revfmt) { 766 case REVFMT_MAJMIN: 767 snprintf(str + n, len - n, "%u.%u)", major, minor); 768 break; 769 case REVFMT_HEX: 770 snprintf(str + n, len - n, "0x%04x)", rev); 771 break; 772 case REVFMT_DEC: 773 snprintf(str + n, len - n, "%u)", rev); 774 break; 775 } 776 } 777 } 778 779 #ifdef L2CR_CONFIG 780 u_int l2cr_config = L2CR_CONFIG; 781 #else 782 u_int l2cr_config = 0; 783 #endif 784 785 #ifdef L3CR_CONFIG 786 u_int l3cr_config = L3CR_CONFIG; 787 #else 788 u_int l3cr_config = 0; 789 #endif 790 791 void 792 cpu_enable_l2cr(register_t l2cr) 793 { 794 register_t msr, x; 795 uint16_t vers; 796 797 vers = mfpvr() >> 16; 798 799 /* Disable interrupts and set the cache config bits. */ 800 msr = mfmsr(); 801 mtmsr(msr & ~PSL_EE); 802 #ifdef ALTIVEC 803 if (cpu_altivec) 804 __asm volatile("dssall"); 805 #endif 806 __asm volatile("sync"); 807 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 808 __asm volatile("sync"); 809 810 /* Wait for L2 clock to be stable (640 L2 clocks). */ 811 delay(100); 812 813 /* Invalidate all L2 contents. */ 814 if (MPC745X_P(vers)) { 815 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 816 do { 817 x = mfspr(SPR_L2CR); 818 } while (x & L2CR_L2I); 819 } else { 820 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 821 do { 822 x = mfspr(SPR_L2CR); 823 } while (x & L2CR_L2IP); 824 } 825 /* Enable L2 cache. */ 826 l2cr |= L2CR_L2E; 827 mtspr(SPR_L2CR, l2cr); 828 mtmsr(msr); 829 } 830 831 void 832 cpu_enable_l3cr(register_t l3cr) 833 { 834 register_t x; 835 836 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 837 838 /* 839 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 840 * L3CLKEN. (also mask off reserved bits in case they were included 841 * in L3CR_CONFIG) 842 */ 843 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 844 mtspr(SPR_L3CR, l3cr); 845 846 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 847 l3cr |= 0x04000000; 848 mtspr(SPR_L3CR, l3cr); 849 850 /* 3: Set L3CLKEN to 1*/ 851 l3cr |= L3CR_L3CLKEN; 852 mtspr(SPR_L3CR, l3cr); 853 854 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 855 __asm volatile("dssall;sync"); 856 /* L3 cache is already disabled, no need to clear L3E */ 857 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 858 do { 859 x = mfspr(SPR_L3CR); 860 } while (x & L3CR_L3I); 861 862 /* 6: Clear L3CLKEN to 0 */ 863 l3cr &= ~L3CR_L3CLKEN; 864 mtspr(SPR_L3CR, l3cr); 865 866 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 867 __asm volatile("sync"); 868 delay(100); 869 870 /* 8: Set L3E and L3CLKEN */ 871 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 872 mtspr(SPR_L3CR, l3cr); 873 874 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 875 __asm volatile("sync"); 876 delay(100); 877 } 878 879 void 880 cpu_config_l2cr(int pvr) 881 { 882 register_t l2cr; 883 u_int vers = (pvr >> 16) & 0xffff; 884 885 l2cr = mfspr(SPR_L2CR); 886 887 /* 888 * For MP systems, the firmware may only configure the L2 cache 889 * on the first CPU. In this case, assume that the other CPUs 890 * should use the same value for L2CR. 891 */ 892 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 893 l2cr_config = l2cr; 894 } 895 896 /* 897 * Configure L2 cache if not enabled. 898 */ 899 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 900 cpu_enable_l2cr(l2cr_config); 901 l2cr = mfspr(SPR_L2CR); 902 } 903 904 if ((l2cr & L2CR_L2E) == 0) { 905 aprint_normal(" L2 cache present but not enabled "); 906 return; 907 } 908 aprint_normal(","); 909 910 switch (vers) { 911 case IBM750FX: 912 case IBM750GX: 913 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 914 break; 915 case MPC750: 916 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 917 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 918 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 919 else 920 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 921 break; 922 case MPC7447A: 923 case MPC7457: 924 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 925 return; 926 case MPC7448: 927 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 928 return; 929 case MPC7450: 930 case MPC7455: 931 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 932 break; 933 default: 934 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 935 break; 936 } 937 } 938 939 void 940 cpu_config_l3cr(int vers) 941 { 942 register_t l2cr; 943 register_t l3cr; 944 945 l2cr = mfspr(SPR_L2CR); 946 947 /* 948 * For MP systems, the firmware may only configure the L2 cache 949 * on the first CPU. In this case, assume that the other CPUs 950 * should use the same value for L2CR. 951 */ 952 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 953 l2cr_config = l2cr; 954 } 955 956 /* 957 * Configure L2 cache if not enabled. 958 */ 959 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 960 cpu_enable_l2cr(l2cr_config); 961 l2cr = mfspr(SPR_L2CR); 962 } 963 964 aprint_normal(","); 965 switch (vers) { 966 case MPC7447A: 967 case MPC7457: 968 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 969 return; 970 case MPC7448: 971 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 972 return; 973 default: 974 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 975 break; 976 } 977 978 l3cr = mfspr(SPR_L3CR); 979 980 /* 981 * For MP systems, the firmware may only configure the L3 cache 982 * on the first CPU. In this case, assume that the other CPUs 983 * should use the same value for L3CR. 984 */ 985 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 986 l3cr_config = l3cr; 987 } 988 989 /* 990 * Configure L3 cache if not enabled. 991 */ 992 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 993 cpu_enable_l3cr(l3cr_config); 994 l3cr = mfspr(SPR_L3CR); 995 } 996 997 if (l3cr & L3CR_L3E) { 998 aprint_normal(","); 999 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1000 } 1001 } 1002 1003 void 1004 cpu_probe_speed(struct cpu_info *ci) 1005 { 1006 uint64_t cps; 1007 1008 mtspr(SPR_MMCR0, MMCR0_FC); 1009 mtspr(SPR_PMC1, 0); 1010 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1011 delay(100000); 1012 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1013 1014 mtspr(SPR_MMCR0, MMCR0_FC); 1015 1016 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1017 } 1018 1019 /* 1020 * Read the Dynamic Frequency Switching state and return a divisor for 1021 * the maximum frequency. 1022 */ 1023 int 1024 cpu_get_dfs(void) 1025 { 1026 u_int pvr, vers; 1027 1028 pvr = mfpvr(); 1029 vers = pvr >> 16; 1030 1031 switch (vers) { 1032 case MPC7448: 1033 if (mfspr(SPR_HID1) & HID1_DFS4) 1034 return 4; 1035 case MPC7447A: 1036 if (mfspr(SPR_HID1) & HID1_DFS2) 1037 return 2; 1038 } 1039 return 1; 1040 } 1041 1042 /* 1043 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1044 */ 1045 void 1046 cpu_set_dfs(int div) 1047 { 1048 uint64_t where; 1049 u_int dfs_mask, pvr, vers; 1050 1051 pvr = mfpvr(); 1052 vers = pvr >> 16; 1053 dfs_mask = 0; 1054 1055 switch (vers) { 1056 case MPC7448: 1057 dfs_mask |= HID1_DFS4; 1058 case MPC7447A: 1059 dfs_mask |= HID1_DFS2; 1060 break; 1061 default: 1062 printf("cpu_set_dfs: DFS not supported\n"); 1063 return; 1064 1065 } 1066 1067 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1068 xc_wait(where); 1069 } 1070 1071 static void 1072 cpu_set_dfs_xcall(void *arg1, void *arg2) 1073 { 1074 u_int dfs_mask, hid1, old_hid1; 1075 int *divisor, s; 1076 1077 divisor = arg1; 1078 dfs_mask = *(u_int *)arg2; 1079 1080 s = splhigh(); 1081 hid1 = old_hid1 = mfspr(SPR_HID1); 1082 1083 switch (*divisor) { 1084 case 1: 1085 hid1 &= ~dfs_mask; 1086 break; 1087 case 2: 1088 hid1 &= ~(dfs_mask & HID1_DFS4); 1089 hid1 |= dfs_mask & HID1_DFS2; 1090 break; 1091 case 4: 1092 hid1 &= ~(dfs_mask & HID1_DFS2); 1093 hid1 |= dfs_mask & HID1_DFS4; 1094 break; 1095 } 1096 1097 if (hid1 != old_hid1) { 1098 __asm volatile("sync"); 1099 mtspr(SPR_HID1, hid1); 1100 __asm volatile("sync;isync"); 1101 } 1102 1103 splx(s); 1104 } 1105 1106 #if NSYSMON_ENVSYS > 0 1107 void 1108 cpu_tau_setup(struct cpu_info *ci) 1109 { 1110 struct sysmon_envsys *sme; 1111 int error, therm_delay; 1112 1113 mtspr(SPR_THRM1, SPR_THRM_VALID); 1114 mtspr(SPR_THRM2, 0); 1115 1116 /* 1117 * we need to figure out how much 20+us in units of CPU clock cycles 1118 * are 1119 */ 1120 1121 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1122 1123 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1124 1125 sme = sysmon_envsys_create(); 1126 1127 sensor.units = ENVSYS_STEMP; 1128 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1129 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1130 sysmon_envsys_destroy(sme); 1131 return; 1132 } 1133 1134 sme->sme_name = device_xname(ci->ci_dev); 1135 sme->sme_cookie = ci; 1136 sme->sme_refresh = cpu_tau_refresh; 1137 1138 if ((error = sysmon_envsys_register(sme)) != 0) { 1139 aprint_error_dev(ci->ci_dev, 1140 " unable to register with sysmon (%d)\n", error); 1141 sysmon_envsys_destroy(sme); 1142 } 1143 } 1144 1145 1146 /* Find the temperature of the CPU. */ 1147 void 1148 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1149 { 1150 int i, threshold, count; 1151 1152 threshold = 64; /* Half of the 7-bit sensor range */ 1153 1154 /* Successive-approximation code adapted from Motorola 1155 * application note AN1800/D, "Programming the Thermal Assist 1156 * Unit in the MPC750 Microprocessor". 1157 */ 1158 for (i = 5; i >= 0 ; i--) { 1159 mtspr(SPR_THRM1, 1160 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1161 count = 0; 1162 while ((count < 100000) && 1163 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1164 count++; 1165 delay(1); 1166 } 1167 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1168 /* The interrupt bit was set, meaning the 1169 * temperature was above the threshold 1170 */ 1171 threshold += 1 << i; 1172 } else { 1173 /* Temperature was below the threshold */ 1174 threshold -= 1 << i; 1175 } 1176 1177 } 1178 threshold += 2; 1179 1180 /* Convert the temperature in degrees C to microkelvin */ 1181 edata->value_cur = (threshold * 1000000) + 273150000; 1182 edata->state = ENVSYS_SVALID; 1183 } 1184 #endif /* NSYSMON_ENVSYS > 0 */ 1185 1186 #ifdef MULTIPROCESSOR 1187 extern volatile u_int cpu_spinstart_ack; 1188 1189 int 1190 cpu_spinup(device_t self, struct cpu_info *ci) 1191 { 1192 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1193 struct pglist mlist; 1194 int i, error, pvr, vers; 1195 char *hp; 1196 1197 pvr = mfpvr(); 1198 vers = pvr >> 16; 1199 KASSERT(ci != curcpu()); 1200 1201 /* Now allocate a hatch stack */ 1202 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1203 &mlist, 1, 1); 1204 if (error) { 1205 aprint_error(": unable to allocate hatch stack\n"); 1206 return -1; 1207 } 1208 1209 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1210 memset(hp, 0, 0x1000); 1211 1212 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1213 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1214 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1215 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1216 1217 cpu_hatch_data = h; 1218 h->running = 0; 1219 h->self = self; 1220 h->ci = ci; 1221 h->pir = ci->ci_cpuid; 1222 1223 cpu_hatch_stack = (uint32_t)hp; 1224 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1225 1226 /* copy special registers */ 1227 1228 h->hid0 = mfspr(SPR_HID0); 1229 1230 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1231 for (i = 0; i < 16; i++) { 1232 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1233 "r"(i << ADDR_SR_SHFT)); 1234 } 1235 if (oeacpufeat & OEACPU_64) 1236 h->asr = mfspr(SPR_ASR); 1237 else 1238 h->asr = 0; 1239 1240 /* copy the bat regs */ 1241 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1242 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1243 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1244 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1245 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1246 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1247 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1248 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1249 __asm volatile ("sync; isync"); 1250 1251 if (md_setup_trampoline(h, ci) == -1) 1252 return -1; 1253 md_presync_timebase(h); 1254 md_start_timebase(h); 1255 1256 /* wait for secondary printf */ 1257 1258 delay(200000); 1259 1260 if (h->running < 1) { 1261 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1262 ci->ci_cpuid, cpu_spinstart_ack); 1263 Debugger(); 1264 return -1; 1265 } 1266 1267 /* Register IPI Interrupt */ 1268 if (ipiops.ppc_establish_ipi) 1269 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1270 1271 return 0; 1272 } 1273 1274 static volatile int start_secondary_cpu; 1275 extern void tlbia(void); 1276 1277 register_t 1278 cpu_hatch(void) 1279 { 1280 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1281 struct cpu_info * const ci = h->ci; 1282 struct pcb *pcb; 1283 u_int msr; 1284 int i; 1285 1286 /* Initialize timebase. */ 1287 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1288 1289 /* 1290 * Set PIR (Processor Identification Register). i.e. whoami 1291 * Note that PIR is read-only on some CPU versions, so we write to it 1292 * only if it has a different value than we need. 1293 */ 1294 1295 msr = mfspr(SPR_PIR); 1296 if (msr != h->pir) 1297 mtspr(SPR_PIR, h->pir); 1298 1299 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1300 curlwp = ci->ci_curlwp; 1301 cpu_spinstart_ack = 0; 1302 1303 /* Initialize MMU. */ 1304 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1305 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1306 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1307 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1308 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1309 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1310 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1311 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1312 1313 mtspr(SPR_HID0, h->hid0); 1314 1315 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1316 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1317 1318 __asm volatile ("sync"); 1319 for (i = 0; i < 16; i++) 1320 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1321 __asm volatile ("sync; isync"); 1322 1323 if (oeacpufeat & OEACPU_64) 1324 mtspr(SPR_ASR, h->asr); 1325 1326 cpu_spinstart_ack = 1; 1327 __asm ("ptesync"); 1328 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1329 __asm volatile ("sync; isync"); 1330 1331 cpu_spinstart_ack = 5; 1332 for (i = 0; i < 16; i++) 1333 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1334 "r"(i << ADDR_SR_SHFT)); 1335 1336 /* Enable I/D address translations. */ 1337 msr = mfmsr(); 1338 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1339 mtmsr(msr); 1340 __asm volatile ("sync; isync"); 1341 cpu_spinstart_ack = 2; 1342 1343 md_sync_timebase(h); 1344 1345 cpu_setup(h->self, ci); 1346 1347 h->running = 1; 1348 __asm volatile ("sync; isync"); 1349 1350 while (start_secondary_cpu == 0) 1351 ; 1352 1353 __asm volatile ("sync; isync"); 1354 1355 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1356 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1357 1358 md_setup_interrupts(); 1359 1360 ci->ci_ipending = 0; 1361 ci->ci_cpl = 0; 1362 1363 mtmsr(mfmsr() | PSL_EE); 1364 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1365 return pcb->pcb_sp; 1366 } 1367 1368 void 1369 cpu_boot_secondary_processors(void) 1370 { 1371 start_secondary_cpu = 1; 1372 __asm volatile ("sync"); 1373 } 1374 1375 #endif /*MULTIPROCESSOR*/ 1376