1 /* $NetBSD: cpu_subr.c,v 1.47 2008/05/25 16:00:52 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.47 2008/05/25 16:00:52 chs Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/cpufeat.h> 58 59 #include <dev/sysmon/sysmonvar.h> 60 61 static void cpu_enable_l2cr(register_t); 62 static void cpu_enable_l3cr(register_t); 63 static void cpu_config_l2cr(int); 64 static void cpu_config_l3cr(int); 65 static void cpu_probe_speed(struct cpu_info *); 66 static void cpu_idlespin(void); 67 #if NSYSMON_ENVSYS > 0 68 static void cpu_tau_setup(struct cpu_info *); 69 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 70 #endif 71 72 int cpu; 73 int ncpus; 74 75 struct fmttab { 76 register_t fmt_mask; 77 register_t fmt_value; 78 const char *fmt_string; 79 }; 80 81 static const struct fmttab cpu_7450_l2cr_formats[] = { 82 { L2CR_L2E, 0, " disabled" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 85 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 86 { L2CR_L2E, ~0, " 256KB L2 cache" }, 87 { L2CR_L2PE, 0, " no parity" }, 88 { L2CR_L2PE, ~0, " parity enabled" }, 89 { 0, 0, NULL } 90 }; 91 92 static const struct fmttab cpu_7448_l2cr_formats[] = { 93 { L2CR_L2E, 0, " disabled" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 97 { L2CR_L2E, ~0, " 1MB L2 cache" }, 98 { L2CR_L2PE, 0, " no parity" }, 99 { L2CR_L2PE, ~0, " parity enabled" }, 100 { 0, 0, NULL } 101 }; 102 103 static const struct fmttab cpu_7457_l2cr_formats[] = { 104 { L2CR_L2E, 0, " disabled" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 108 { L2CR_L2E, ~0, " 512KB L2 cache" }, 109 { L2CR_L2PE, 0, " no parity" }, 110 { L2CR_L2PE, ~0, " parity enabled" }, 111 { 0, 0, NULL } 112 }; 113 114 static const struct fmttab cpu_7450_l3cr_formats[] = { 115 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 116 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 117 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 118 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 119 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 120 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 121 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 122 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 123 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 124 { L3CR_L3SIZ, ~0, " L3 cache" }, 125 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 126 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 127 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 128 { L3CR_L3CLK, ~0, " at" }, 129 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 130 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 131 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 132 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 133 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 134 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 135 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 136 { L3CR_L3CLK, ~0, " ratio" }, 137 { 0, 0, NULL }, 138 }; 139 140 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 141 { L2CR_L2E, 0, " disabled" }, 142 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 143 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 144 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 145 { 0, ~0, " 512KB" }, 146 { L2CR_L2WT, L2CR_L2WT, " WT" }, 147 { L2CR_L2WT, 0, " WB" }, 148 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 149 { 0, ~0, " L2 cache" }, 150 { 0, 0, NULL } 151 }; 152 153 static const struct fmttab cpu_l2cr_formats[] = { 154 { L2CR_L2E, 0, " disabled" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 157 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 158 { L2CR_L2PE, L2CR_L2PE, " parity" }, 159 { L2CR_L2PE, 0, " no-parity" }, 160 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 161 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 162 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 163 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 164 { L2CR_L2WT, L2CR_L2WT, " WT" }, 165 { L2CR_L2WT, 0, " WB" }, 166 { L2CR_L2E, ~0, " L2 cache" }, 167 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 168 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 169 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 170 { L2CR_L2CLK, ~0, " at" }, 171 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 172 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 173 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 174 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 175 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 176 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 177 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 178 { L2CR_L2CLK, ~0, " ratio" }, 179 { 0, 0, NULL } 180 }; 181 182 static void cpu_fmttab_print(const struct fmttab *, register_t); 183 184 struct cputab { 185 const char name[8]; 186 uint16_t version; 187 uint16_t revfmt; 188 }; 189 #define REVFMT_MAJMIN 1 /* %u.%u */ 190 #define REVFMT_HEX 2 /* 0x%04x */ 191 #define REVFMT_DEC 3 /* %u */ 192 static const struct cputab models[] = { 193 { "601", MPC601, REVFMT_DEC }, 194 { "602", MPC602, REVFMT_DEC }, 195 { "603", MPC603, REVFMT_MAJMIN }, 196 { "603e", MPC603e, REVFMT_MAJMIN }, 197 { "603ev", MPC603ev, REVFMT_MAJMIN }, 198 { "G2", MPCG2, REVFMT_MAJMIN }, 199 { "604", MPC604, REVFMT_MAJMIN }, 200 { "604e", MPC604e, REVFMT_MAJMIN }, 201 { "604ev", MPC604ev, REVFMT_MAJMIN }, 202 { "620", MPC620, REVFMT_HEX }, 203 { "750", MPC750, REVFMT_MAJMIN }, 204 { "750FX", IBM750FX, REVFMT_MAJMIN }, 205 { "7400", MPC7400, REVFMT_MAJMIN }, 206 { "7410", MPC7410, REVFMT_MAJMIN }, 207 { "7450", MPC7450, REVFMT_MAJMIN }, 208 { "7455", MPC7455, REVFMT_MAJMIN }, 209 { "7457", MPC7457, REVFMT_MAJMIN }, 210 { "7447A", MPC7447A, REVFMT_MAJMIN }, 211 { "7448", MPC7448, REVFMT_MAJMIN }, 212 { "8240", MPC8240, REVFMT_MAJMIN }, 213 { "8245", MPC8245, REVFMT_MAJMIN }, 214 { "970", IBM970, REVFMT_MAJMIN }, 215 { "970FX", IBM970FX, REVFMT_MAJMIN }, 216 { "970MP", IBM970MP, REVFMT_MAJMIN }, 217 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 218 { "", 0, REVFMT_HEX } 219 }; 220 221 #ifdef MULTIPROCESSOR 222 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 223 volatile struct cpu_hatch_data *cpu_hatch_data; 224 volatile int cpu_hatch_stack; 225 extern int ticks_per_intr; 226 #include <powerpc/oea/bat.h> 227 #include <arch/powerpc/pic/picvar.h> 228 #include <arch/powerpc/pic/ipivar.h> 229 extern struct bat battable[]; 230 #else 231 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 232 #endif /*MULTIPROCESSOR*/ 233 234 int cpu_altivec; 235 int cpu_psluserset, cpu_pslusermod; 236 char cpu_model[80]; 237 238 /* This is to be called from locore.S, and nowhere else. */ 239 240 void 241 cpu_model_init(void) 242 { 243 u_int pvr, vers; 244 245 pvr = mfpvr(); 246 vers = pvr >> 16; 247 248 oeacpufeat = 0; 249 250 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 251 vers == IBMCELL || vers == IBMPOWER6P5) 252 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 253 254 else if (vers == MPC601) 255 oeacpufeat |= OEACPU_601; 256 257 else if (MPC745X_P(vers) && vers != MPC7450) 258 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 259 } 260 261 void 262 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 263 { 264 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 265 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 266 (data & fmt->fmt_mask) == fmt->fmt_value) 267 aprint_normal("%s", fmt->fmt_string); 268 } 269 } 270 271 void 272 cpu_idlespin(void) 273 { 274 register_t msr; 275 276 if (powersave <= 0) 277 return; 278 279 __asm volatile( 280 "sync;" 281 "mfmsr %0;" 282 "oris %0,%0,%1@h;" /* enter power saving mode */ 283 "mtmsr %0;" 284 "isync;" 285 : "=r"(msr) 286 : "J"(PSL_POW)); 287 } 288 289 void 290 cpu_probe_cache(void) 291 { 292 u_int assoc, pvr, vers; 293 294 pvr = mfpvr(); 295 vers = pvr >> 16; 296 297 298 /* Presently common across almost all implementations. */ 299 curcpu()->ci_ci.dcache_line_size = 32; 300 curcpu()->ci_ci.icache_line_size = 32; 301 302 303 switch (vers) { 304 #define K *1024 305 case IBM750FX: 306 case MPC601: 307 case MPC750: 308 case MPC7447A: 309 case MPC7448: 310 case MPC7450: 311 case MPC7455: 312 case MPC7457: 313 curcpu()->ci_ci.dcache_size = 32 K; 314 curcpu()->ci_ci.icache_size = 32 K; 315 assoc = 8; 316 break; 317 case MPC603: 318 curcpu()->ci_ci.dcache_size = 8 K; 319 curcpu()->ci_ci.icache_size = 8 K; 320 assoc = 2; 321 break; 322 case MPC603e: 323 case MPC603ev: 324 case MPC604: 325 case MPC8240: 326 case MPC8245: 327 case MPCG2: 328 curcpu()->ci_ci.dcache_size = 16 K; 329 curcpu()->ci_ci.icache_size = 16 K; 330 assoc = 4; 331 break; 332 case MPC604e: 333 case MPC604ev: 334 curcpu()->ci_ci.dcache_size = 32 K; 335 curcpu()->ci_ci.icache_size = 32 K; 336 assoc = 4; 337 break; 338 case IBMPOWER3II: 339 curcpu()->ci_ci.dcache_size = 64 K; 340 curcpu()->ci_ci.icache_size = 32 K; 341 curcpu()->ci_ci.dcache_line_size = 128; 342 curcpu()->ci_ci.icache_line_size = 128; 343 assoc = 128; /* not a typo */ 344 break; 345 case IBM970: 346 case IBM970FX: 347 case IBM970MP: 348 curcpu()->ci_ci.dcache_size = 32 K; 349 curcpu()->ci_ci.icache_size = 64 K; 350 curcpu()->ci_ci.dcache_line_size = 128; 351 curcpu()->ci_ci.icache_line_size = 128; 352 assoc = 2; 353 break; 354 355 default: 356 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 357 curcpu()->ci_ci.icache_size = PAGE_SIZE; 358 assoc = 1; 359 #undef K 360 } 361 362 /* 363 * Possibly recolor. 364 */ 365 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 366 } 367 368 struct cpu_info * 369 cpu_attach_common(struct device *self, int id) 370 { 371 struct cpu_info *ci; 372 u_int pvr, vers; 373 374 ci = &cpu_info[id]; 375 #ifndef MULTIPROCESSOR 376 /* 377 * If this isn't the primary CPU, print an error message 378 * and just bail out. 379 */ 380 if (id != 0) { 381 aprint_normal(": ID %d\n", id); 382 aprint_normal("%s: processor off-line; multiprocessor support " 383 "not present in kernel\n", self->dv_xname); 384 return (NULL); 385 } 386 #endif 387 388 ci->ci_cpuid = id; 389 ci->ci_intrdepth = -1; 390 ci->ci_dev = self; 391 ci->ci_idlespin = cpu_idlespin; 392 393 pvr = mfpvr(); 394 vers = (pvr >> 16) & 0xffff; 395 396 switch (id) { 397 case 0: 398 /* load my cpu_number to PIR */ 399 switch (vers) { 400 case MPC601: 401 case MPC604: 402 case MPC604e: 403 case MPC604ev: 404 case MPC7400: 405 case MPC7410: 406 case MPC7447A: 407 case MPC7448: 408 case MPC7450: 409 case MPC7455: 410 case MPC7457: 411 mtspr(SPR_PIR, id); 412 } 413 cpu_setup(self, ci); 414 break; 415 default: 416 if (id >= CPU_MAXNUM) { 417 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 418 panic("cpuattach"); 419 } 420 #ifndef MULTIPROCESSOR 421 aprint_normal(" not configured\n"); 422 return NULL; 423 #else 424 mi_cpu_attach(ci); 425 break; 426 #endif 427 } 428 return (ci); 429 } 430 431 void 432 cpu_setup(self, ci) 433 struct device *self; 434 struct cpu_info *ci; 435 { 436 u_int hid0, hid0_save, pvr, vers; 437 const char *bitmask; 438 char hidbuf[128]; 439 char model[80]; 440 441 pvr = mfpvr(); 442 vers = (pvr >> 16) & 0xffff; 443 444 cpu_identify(model, sizeof(model)); 445 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 446 cpu_number() == 0 ? " (primary)" : ""); 447 448 /* set the cpu number */ 449 ci->ci_cpuid = cpu_number(); 450 hid0_save = hid0 = mfspr(SPR_HID0); 451 452 cpu_probe_cache(); 453 454 /* 455 * Configure power-saving mode. 456 */ 457 switch (vers) { 458 case MPC604: 459 case MPC604e: 460 case MPC604ev: 461 /* 462 * Do not have HID0 support settings, but can support 463 * MSR[POW] off 464 */ 465 powersave = 1; 466 break; 467 468 case MPC603: 469 case MPC603e: 470 case MPC603ev: 471 case MPC750: 472 case IBM750FX: 473 case MPC7400: 474 case MPC7410: 475 case MPC8240: 476 case MPC8245: 477 case MPCG2: 478 /* Select DOZE mode. */ 479 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 480 hid0 |= HID0_DOZE | HID0_DPM; 481 powersave = 1; 482 break; 483 484 case MPC7447A: 485 case MPC7448: 486 case MPC7457: 487 case MPC7455: 488 case MPC7450: 489 /* Enable the 7450 branch caches */ 490 hid0 |= HID0_SGE | HID0_BTIC; 491 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 492 /* Enable more and larger BAT registers */ 493 if (oeacpufeat & OEACPU_XBSEN) 494 hid0 |= HID0_XBSEN; 495 if (oeacpufeat & OEACPU_HIGHBAT) 496 hid0 |= HID0_HIGH_BAT_EN; 497 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 498 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 499 hid0 &= ~HID0_BTIC; 500 /* Select NAP mode. */ 501 hid0 &= ~HID0_SLEEP; 502 hid0 |= HID0_NAP | HID0_DPM; 503 powersave = 1; 504 break; 505 506 case IBM970: 507 case IBM970FX: 508 case IBM970MP: 509 case IBMPOWER3II: 510 default: 511 /* No power-saving mode is available. */ ; 512 } 513 514 #ifdef NAPMODE 515 switch (vers) { 516 case IBM750FX: 517 case MPC750: 518 case MPC7400: 519 /* Select NAP mode. */ 520 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 521 hid0 |= HID0_NAP; 522 break; 523 } 524 #endif 525 526 switch (vers) { 527 case IBM750FX: 528 case MPC750: 529 hid0 &= ~HID0_DBP; /* XXX correct? */ 530 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 531 break; 532 533 case MPC7400: 534 case MPC7410: 535 hid0 &= ~HID0_SPD; 536 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 537 hid0 |= HID0_EIEC; 538 break; 539 } 540 541 if (hid0 != hid0_save) { 542 mtspr(SPR_HID0, hid0); 543 __asm volatile("sync;isync"); 544 } 545 546 547 switch (vers) { 548 case MPC601: 549 bitmask = HID0_601_BITMASK; 550 break; 551 case MPC7450: 552 case MPC7455: 553 case MPC7457: 554 bitmask = HID0_7450_BITMASK; 555 break; 556 case IBM970: 557 case IBM970FX: 558 case IBM970MP: 559 bitmask = 0; 560 break; 561 default: 562 bitmask = HID0_BITMASK; 563 break; 564 } 565 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 566 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 567 powersave); 568 569 ci->ci_khz = 0; 570 571 /* 572 * Display speed and cache configuration. 573 */ 574 switch (vers) { 575 case MPC604: 576 case MPC604e: 577 case MPC604ev: 578 case MPC750: 579 case IBM750FX: 580 case MPC7400: 581 case MPC7410: 582 case MPC7447A: 583 case MPC7448: 584 case MPC7450: 585 case MPC7455: 586 case MPC7457: 587 aprint_normal("%s: ", self->dv_xname); 588 cpu_probe_speed(ci); 589 aprint_normal("%u.%02u MHz", 590 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 591 switch (vers) { 592 case MPC7450: /* 7441 does not have L3! */ 593 case MPC7455: /* 7445 does not have L3! */ 594 case MPC7457: /* 7447 does not have L3! */ 595 cpu_config_l3cr(vers); 596 break; 597 case IBM750FX: 598 case MPC750: 599 case MPC7400: 600 case MPC7410: 601 case MPC7447A: 602 case MPC7448: 603 cpu_config_l2cr(pvr); 604 break; 605 default: 606 break; 607 } 608 aprint_normal("\n"); 609 break; 610 } 611 612 #if NSYSMON_ENVSYS > 0 613 /* 614 * Attach MPC750 temperature sensor to the envsys subsystem. 615 * XXX the 74xx series also has this sensor, but it is not 616 * XXX supported by Motorola and may return values that are off by 617 * XXX 35-55 degrees C. 618 */ 619 if (vers == MPC750 || vers == IBM750FX) 620 cpu_tau_setup(ci); 621 #endif 622 623 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 624 NULL, self->dv_xname, "clock"); 625 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 626 NULL, self->dv_xname, "soft clock"); 627 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 628 NULL, self->dv_xname, "soft net"); 629 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 630 NULL, self->dv_xname, "soft serial"); 631 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 632 NULL, self->dv_xname, "traps"); 633 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 634 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 635 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 636 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 637 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 638 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 639 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 640 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 641 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 642 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 643 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 644 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 645 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 646 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 647 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 648 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 649 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 650 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 651 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 652 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 653 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 654 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 655 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 656 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 657 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 658 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 659 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 660 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 661 #ifdef ALTIVEC 662 if (cpu_altivec) { 663 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 664 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 665 } 666 #endif 667 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 668 NULL, self->dv_xname, "IPIs"); 669 } 670 671 /* 672 * According to a document labeled "PVR Register Settings": 673 ** For integrated microprocessors the PVR register inside the device 674 ** will identify the version of the microprocessor core. You must also 675 ** read the Device ID, PCI register 02, to identify the part and the 676 ** Revision ID, PCI register 08, to identify the revision of the 677 ** integrated microprocessor. 678 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 679 */ 680 681 void 682 cpu_identify(char *str, size_t len) 683 { 684 u_int pvr, major, minor; 685 uint16_t vers, rev, revfmt; 686 const struct cputab *cp; 687 const char *name; 688 size_t n; 689 690 pvr = mfpvr(); 691 vers = pvr >> 16; 692 rev = pvr; 693 694 switch (vers) { 695 case MPC7410: 696 minor = (pvr >> 0) & 0xff; 697 major = minor <= 4 ? 1 : 2; 698 break; 699 case MPCG2: /*XXX see note above */ 700 major = (pvr >> 4) & 0xf; 701 minor = (pvr >> 0) & 0xf; 702 break; 703 default: 704 major = (pvr >> 8) & 0xf; 705 minor = (pvr >> 0) & 0xf; 706 } 707 708 for (cp = models; cp->name[0] != '\0'; cp++) { 709 if (cp->version == vers) 710 break; 711 } 712 713 if (str == NULL) { 714 str = cpu_model; 715 len = sizeof(cpu_model); 716 cpu = vers; 717 } 718 719 revfmt = cp->revfmt; 720 name = cp->name; 721 if (rev == MPC750 && pvr == 15) { 722 name = "755"; 723 revfmt = REVFMT_HEX; 724 } 725 726 if (cp->name[0] != '\0') { 727 n = snprintf(str, len, "%s (Revision ", cp->name); 728 } else { 729 n = snprintf(str, len, "Version %#x (Revision ", vers); 730 } 731 if (len > n) { 732 switch (revfmt) { 733 case REVFMT_MAJMIN: 734 snprintf(str + n, len - n, "%u.%u)", major, minor); 735 break; 736 case REVFMT_HEX: 737 snprintf(str + n, len - n, "0x%04x)", rev); 738 break; 739 case REVFMT_DEC: 740 snprintf(str + n, len - n, "%u)", rev); 741 break; 742 } 743 } 744 } 745 746 #ifdef L2CR_CONFIG 747 u_int l2cr_config = L2CR_CONFIG; 748 #else 749 u_int l2cr_config = 0; 750 #endif 751 752 #ifdef L3CR_CONFIG 753 u_int l3cr_config = L3CR_CONFIG; 754 #else 755 u_int l3cr_config = 0; 756 #endif 757 758 void 759 cpu_enable_l2cr(register_t l2cr) 760 { 761 register_t msr, x; 762 uint16_t vers; 763 764 vers = mfpvr() >> 16; 765 766 /* Disable interrupts and set the cache config bits. */ 767 msr = mfmsr(); 768 mtmsr(msr & ~PSL_EE); 769 #ifdef ALTIVEC 770 if (cpu_altivec) 771 __asm volatile("dssall"); 772 #endif 773 __asm volatile("sync"); 774 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 775 __asm volatile("sync"); 776 777 /* Wait for L2 clock to be stable (640 L2 clocks). */ 778 delay(100); 779 780 /* Invalidate all L2 contents. */ 781 if (MPC745X_P(vers)) { 782 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 783 do { 784 x = mfspr(SPR_L2CR); 785 } while (x & L2CR_L2I); 786 } else { 787 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 788 do { 789 x = mfspr(SPR_L2CR); 790 } while (x & L2CR_L2IP); 791 } 792 /* Enable L2 cache. */ 793 l2cr |= L2CR_L2E; 794 mtspr(SPR_L2CR, l2cr); 795 mtmsr(msr); 796 } 797 798 void 799 cpu_enable_l3cr(register_t l3cr) 800 { 801 register_t x; 802 803 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 804 805 /* 806 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 807 * L3CLKEN. (also mask off reserved bits in case they were included 808 * in L3CR_CONFIG) 809 */ 810 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 811 mtspr(SPR_L3CR, l3cr); 812 813 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 814 l3cr |= 0x04000000; 815 mtspr(SPR_L3CR, l3cr); 816 817 /* 3: Set L3CLKEN to 1*/ 818 l3cr |= L3CR_L3CLKEN; 819 mtspr(SPR_L3CR, l3cr); 820 821 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 822 __asm volatile("dssall;sync"); 823 /* L3 cache is already disabled, no need to clear L3E */ 824 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 825 do { 826 x = mfspr(SPR_L3CR); 827 } while (x & L3CR_L3I); 828 829 /* 6: Clear L3CLKEN to 0 */ 830 l3cr &= ~L3CR_L3CLKEN; 831 mtspr(SPR_L3CR, l3cr); 832 833 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 834 __asm volatile("sync"); 835 delay(100); 836 837 /* 8: Set L3E and L3CLKEN */ 838 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 839 mtspr(SPR_L3CR, l3cr); 840 841 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 842 __asm volatile("sync"); 843 delay(100); 844 } 845 846 void 847 cpu_config_l2cr(int pvr) 848 { 849 register_t l2cr; 850 u_int vers = (pvr >> 16) & 0xffff; 851 852 l2cr = mfspr(SPR_L2CR); 853 854 /* 855 * For MP systems, the firmware may only configure the L2 cache 856 * on the first CPU. In this case, assume that the other CPUs 857 * should use the same value for L2CR. 858 */ 859 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 860 l2cr_config = l2cr; 861 } 862 863 /* 864 * Configure L2 cache if not enabled. 865 */ 866 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 867 cpu_enable_l2cr(l2cr_config); 868 l2cr = mfspr(SPR_L2CR); 869 } 870 871 if ((l2cr & L2CR_L2E) == 0) { 872 aprint_normal(" L2 cache present but not enabled "); 873 return; 874 } 875 aprint_normal(","); 876 877 switch (vers) { 878 case IBM750FX: 879 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 880 break; 881 case MPC750: 882 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 883 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 884 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 885 else 886 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 887 break; 888 case MPC7447A: 889 case MPC7457: 890 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 891 return; 892 case MPC7448: 893 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 894 return; 895 case MPC7450: 896 case MPC7455: 897 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 898 break; 899 default: 900 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 901 break; 902 } 903 } 904 905 void 906 cpu_config_l3cr(int vers) 907 { 908 register_t l2cr; 909 register_t l3cr; 910 911 l2cr = mfspr(SPR_L2CR); 912 913 /* 914 * For MP systems, the firmware may only configure the L2 cache 915 * on the first CPU. In this case, assume that the other CPUs 916 * should use the same value for L2CR. 917 */ 918 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 919 l2cr_config = l2cr; 920 } 921 922 /* 923 * Configure L2 cache if not enabled. 924 */ 925 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 926 cpu_enable_l2cr(l2cr_config); 927 l2cr = mfspr(SPR_L2CR); 928 } 929 930 aprint_normal(","); 931 switch (vers) { 932 case MPC7447A: 933 case MPC7457: 934 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 935 return; 936 case MPC7448: 937 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 938 return; 939 default: 940 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 941 break; 942 } 943 944 l3cr = mfspr(SPR_L3CR); 945 946 /* 947 * For MP systems, the firmware may only configure the L3 cache 948 * on the first CPU. In this case, assume that the other CPUs 949 * should use the same value for L3CR. 950 */ 951 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 952 l3cr_config = l3cr; 953 } 954 955 /* 956 * Configure L3 cache if not enabled. 957 */ 958 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 959 cpu_enable_l3cr(l3cr_config); 960 l3cr = mfspr(SPR_L3CR); 961 } 962 963 if (l3cr & L3CR_L3E) { 964 aprint_normal(","); 965 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 966 } 967 } 968 969 void 970 cpu_probe_speed(struct cpu_info *ci) 971 { 972 uint64_t cps; 973 974 mtspr(SPR_MMCR0, MMCR0_FC); 975 mtspr(SPR_PMC1, 0); 976 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 977 delay(100000); 978 cps = (mfspr(SPR_PMC1) * 10) + 4999; 979 980 mtspr(SPR_MMCR0, MMCR0_FC); 981 982 ci->ci_khz = cps / 1000; 983 } 984 985 #if NSYSMON_ENVSYS > 0 986 void 987 cpu_tau_setup(struct cpu_info *ci) 988 { 989 struct sysmon_envsys *sme; 990 envsys_data_t sensor; 991 int error; 992 993 sme = sysmon_envsys_create(); 994 995 sensor.state = ENVSYS_SVALID; 996 sensor.units = ENVSYS_STEMP; 997 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 998 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 999 sysmon_envsys_destroy(sme); 1000 return; 1001 } 1002 1003 sme->sme_name = ci->ci_dev->dv_xname; 1004 sme->sme_cookie = ci; 1005 sme->sme_refresh = cpu_tau_refresh; 1006 1007 if ((error = sysmon_envsys_register(sme)) != 0) { 1008 aprint_error("%s: unable to register with sysmon (%d)\n", 1009 ci->ci_dev->dv_xname, error); 1010 sysmon_envsys_destroy(sme); 1011 } 1012 } 1013 1014 1015 /* Find the temperature of the CPU. */ 1016 void 1017 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1018 { 1019 int i, threshold, count; 1020 1021 threshold = 64; /* Half of the 7-bit sensor range */ 1022 mtspr(SPR_THRM1, 0); 1023 mtspr(SPR_THRM2, 0); 1024 /* XXX This counter is supposed to be "at least 20 microseonds, in 1025 * XXX units of clock cycles". Since we don't have convenient 1026 * XXX access to the CPU speed, set it to a conservative value, 1027 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 1028 * XXX the fastest G3 processor is 700MHz) . The cost is that 1029 * XXX measuring the temperature takes a bit longer. 1030 */ 1031 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 1032 1033 /* Successive-approximation code adapted from Motorola 1034 * application note AN1800/D, "Programming the Thermal Assist 1035 * Unit in the MPC750 Microprocessor". 1036 */ 1037 for (i = 4; i >= 0 ; i--) { 1038 mtspr(SPR_THRM1, 1039 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1040 count = 0; 1041 while ((count < 100) && 1042 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1043 count++; 1044 delay(1); 1045 } 1046 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1047 /* The interrupt bit was set, meaning the 1048 * temperature was above the threshold 1049 */ 1050 threshold += 2 << i; 1051 } else { 1052 /* Temperature was below the threshold */ 1053 threshold -= 2 << i; 1054 } 1055 } 1056 threshold += 2; 1057 1058 /* Convert the temperature in degrees C to microkelvin */ 1059 edata->value_cur = (threshold * 1000000) + 273150000; 1060 } 1061 #endif /* NSYSMON_ENVSYS > 0 */ 1062 1063 #ifdef MULTIPROCESSOR 1064 extern volatile u_int cpu_spinstart_ack; 1065 1066 int 1067 cpu_spinup(struct device *self, struct cpu_info *ci) 1068 { 1069 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1070 struct pglist mlist; 1071 int i, error, pvr, vers; 1072 char *cp, *hp; 1073 1074 pvr = mfpvr(); 1075 vers = pvr >> 16; 1076 KASSERT(ci != curcpu()); 1077 1078 /* 1079 * Allocate some contiguous pages for the intteup PCB and stack 1080 * from the lowest 256MB (because bat0 always maps it va == pa). 1081 * Must be 16 byte aligned. 1082 */ 1083 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1084 &mlist, 1, 1); 1085 if (error) { 1086 aprint_error(": unable to allocate idle stack\n"); 1087 return -1; 1088 } 1089 1090 KASSERT(ci != &cpu_info[0]); 1091 1092 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1093 memset(cp, 0, INTSTK); 1094 1095 ci->ci_intstk = cp; 1096 1097 /* Now allocate a hatch stack */ 1098 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1099 &mlist, 1, 1); 1100 if (error) { 1101 aprint_error(": unable to allocate hatch stack\n"); 1102 return -1; 1103 } 1104 1105 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1106 memset(hp, 0, 0x1000); 1107 1108 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1109 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1110 ci->ci_curpcb = &ci->ci_curlwp->l_addr->u_pcb; 1111 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1112 1113 cpu_hatch_data = h; 1114 h->running = 0; 1115 h->self = self; 1116 h->ci = ci; 1117 h->pir = ci->ci_cpuid; 1118 1119 cpu_hatch_stack = (uint32_t)hp; 1120 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1121 1122 /* copy special registers */ 1123 1124 h->hid0 = mfspr(SPR_HID0); 1125 1126 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1127 for (i = 0; i < 16; i++) { 1128 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1129 "r"(i << ADDR_SR_SHFT)); 1130 } 1131 if (oeacpufeat & OEACPU_64) 1132 h->asr = mfspr(SPR_ASR); 1133 else 1134 h->asr = 0; 1135 1136 /* copy the bat regs */ 1137 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1138 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1139 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1140 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1141 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1142 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1143 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1144 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1145 __asm volatile ("sync; isync"); 1146 1147 if (md_setup_trampoline(h, ci) == -1) 1148 return -1; 1149 md_presync_timebase(h); 1150 md_start_timebase(h); 1151 1152 /* wait for secondary printf */ 1153 1154 delay(200000); 1155 1156 if (h->running < 1) { 1157 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1158 ci->ci_cpuid, cpu_spinstart_ack); 1159 Debugger(); 1160 return -1; 1161 } 1162 1163 /* Register IPI Interrupt */ 1164 if (ipiops.ppc_establish_ipi) 1165 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1166 1167 return 0; 1168 } 1169 1170 static volatile int start_secondary_cpu; 1171 extern void tlbia(void); 1172 1173 register_t 1174 cpu_hatch(void) 1175 { 1176 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1177 struct cpu_info * const ci = h->ci; 1178 u_int msr; 1179 int i; 1180 1181 /* Initialize timebase. */ 1182 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1183 1184 /* 1185 * Set PIR (Processor Identification Register). i.e. whoami 1186 * Note that PIR is read-only on some CPU's. Try to work around 1187 * that as best as possible. Assume that if it is 0, it is meant 1188 * to be setup by us. 1189 */ 1190 1191 msr = mfspr(SPR_PIR); 1192 if (msr == 0) 1193 mtspr(SPR_PIR, h->pir); 1194 1195 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1196 cpu_spinstart_ack = 0; 1197 1198 /* Initialize MMU. */ 1199 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1200 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1201 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1202 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1203 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1204 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1205 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1206 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1207 1208 mtspr(SPR_HID0, h->hid0); 1209 1210 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1211 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1212 1213 __asm volatile ("sync"); 1214 for (i = 0; i < 16; i++) 1215 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1216 __asm volatile ("sync; isync"); 1217 1218 if (oeacpufeat & OEACPU_64) 1219 mtspr(SPR_ASR, h->asr); 1220 1221 cpu_spinstart_ack = 1; 1222 __asm ("ptesync"); 1223 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1224 __asm volatile ("sync; isync"); 1225 1226 cpu_spinstart_ack = 5; 1227 for (i = 0; i < 16; i++) 1228 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1229 "r"(i << ADDR_SR_SHFT)); 1230 1231 /* Enable I/D address translations. */ 1232 msr = mfmsr(); 1233 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1234 mtmsr(msr); 1235 __asm volatile ("sync; isync"); 1236 cpu_spinstart_ack = 2; 1237 1238 md_sync_timebase(h); 1239 1240 cpu_setup(h->self, ci); 1241 1242 h->running = 1; 1243 __asm volatile ("sync; isync"); 1244 1245 while (start_secondary_cpu == 0) 1246 ; 1247 1248 __asm volatile ("sync; isync"); 1249 1250 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1251 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1252 1253 md_setup_interrupts(); 1254 1255 ci->ci_ipending = 0; 1256 ci->ci_cpl = 0; 1257 1258 mtmsr(mfmsr() | PSL_EE); 1259 return ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp; 1260 } 1261 1262 void 1263 cpu_boot_secondary_processors() 1264 { 1265 start_secondary_cpu = 1; 1266 __asm volatile ("sync"); 1267 } 1268 1269 #endif /*MULTIPROCESSOR*/ 1270