1 /* $NetBSD: cpu_subr.c,v 1.61 2011/01/18 02:25:42 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.61 2011/01/18 02:25:42 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/malloc.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/spr.h> 56 #include <powerpc/oea/hid.h> 57 #include <powerpc/oea/hid_601.h> 58 #include <powerpc/oea/spr.h> 59 #include <powerpc/oea/cpufeat.h> 60 61 #include <dev/sysmon/sysmonvar.h> 62 63 static void cpu_enable_l2cr(register_t); 64 static void cpu_enable_l3cr(register_t); 65 static void cpu_config_l2cr(int); 66 static void cpu_config_l3cr(int); 67 static void cpu_probe_speed(struct cpu_info *); 68 static void cpu_idlespin(void); 69 static void cpu_set_dfs_xcall(void *, void *); 70 #if NSYSMON_ENVSYS > 0 71 static void cpu_tau_setup(struct cpu_info *); 72 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 73 #endif 74 75 int cpu; 76 int ncpus; 77 78 struct fmttab { 79 register_t fmt_mask; 80 register_t fmt_value; 81 const char *fmt_string; 82 }; 83 84 /* 85 * This should be one per CPU but since we only support it on 750 variants it 86 * doesn't realy matter since none of them supports SMP 87 */ 88 envsys_data_t sensor; 89 90 static const struct fmttab cpu_7450_l2cr_formats[] = { 91 { L2CR_L2E, 0, " disabled" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 95 { L2CR_L2E, ~0, " 256KB L2 cache" }, 96 { L2CR_L2PE, 0, " no parity" }, 97 { L2CR_L2PE, ~0, " parity enabled" }, 98 { 0, 0, NULL } 99 }; 100 101 static const struct fmttab cpu_7448_l2cr_formats[] = { 102 { L2CR_L2E, 0, " disabled" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 106 { L2CR_L2E, ~0, " 1MB L2 cache" }, 107 { L2CR_L2PE, 0, " no parity" }, 108 { L2CR_L2PE, ~0, " parity enabled" }, 109 { 0, 0, NULL } 110 }; 111 112 static const struct fmttab cpu_7457_l2cr_formats[] = { 113 { L2CR_L2E, 0, " disabled" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 117 { L2CR_L2E, ~0, " 512KB L2 cache" }, 118 { L2CR_L2PE, 0, " no parity" }, 119 { L2CR_L2PE, ~0, " parity enabled" }, 120 { 0, 0, NULL } 121 }; 122 123 static const struct fmttab cpu_7450_l3cr_formats[] = { 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 127 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 128 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 133 { L3CR_L3SIZ, ~0, " L3 cache" }, 134 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 135 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 136 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 137 { L3CR_L3CLK, ~0, " at" }, 138 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 139 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 140 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 141 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 142 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 143 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 144 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 145 { L3CR_L3CLK, ~0, " ratio" }, 146 { 0, 0, NULL }, 147 }; 148 149 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 150 { L2CR_L2E, 0, " disabled" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 154 { 0, ~0, " 512KB" }, 155 { L2CR_L2WT, L2CR_L2WT, " WT" }, 156 { L2CR_L2WT, 0, " WB" }, 157 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 158 { 0, ~0, " L2 cache" }, 159 { 0, 0, NULL } 160 }; 161 162 static const struct fmttab cpu_l2cr_formats[] = { 163 { L2CR_L2E, 0, " disabled" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 167 { L2CR_L2PE, L2CR_L2PE, " parity" }, 168 { L2CR_L2PE, 0, " no-parity" }, 169 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 170 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 171 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 172 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 173 { L2CR_L2WT, L2CR_L2WT, " WT" }, 174 { L2CR_L2WT, 0, " WB" }, 175 { L2CR_L2E, ~0, " L2 cache" }, 176 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 177 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 179 { L2CR_L2CLK, ~0, " at" }, 180 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 181 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 182 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 183 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 184 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 185 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 186 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 187 { L2CR_L2CLK, ~0, " ratio" }, 188 { 0, 0, NULL } 189 }; 190 191 static void cpu_fmttab_print(const struct fmttab *, register_t); 192 193 struct cputab { 194 const char name[8]; 195 uint16_t version; 196 uint16_t revfmt; 197 }; 198 #define REVFMT_MAJMIN 1 /* %u.%u */ 199 #define REVFMT_HEX 2 /* 0x%04x */ 200 #define REVFMT_DEC 3 /* %u */ 201 static const struct cputab models[] = { 202 { "601", MPC601, REVFMT_DEC }, 203 { "602", MPC602, REVFMT_DEC }, 204 { "603", MPC603, REVFMT_MAJMIN }, 205 { "603e", MPC603e, REVFMT_MAJMIN }, 206 { "603ev", MPC603ev, REVFMT_MAJMIN }, 207 { "G2", MPCG2, REVFMT_MAJMIN }, 208 { "604", MPC604, REVFMT_MAJMIN }, 209 { "604e", MPC604e, REVFMT_MAJMIN }, 210 { "604ev", MPC604ev, REVFMT_MAJMIN }, 211 { "620", MPC620, REVFMT_HEX }, 212 { "750", MPC750, REVFMT_MAJMIN }, 213 { "750FX", IBM750FX, REVFMT_MAJMIN }, 214 { "7400", MPC7400, REVFMT_MAJMIN }, 215 { "7410", MPC7410, REVFMT_MAJMIN }, 216 { "7450", MPC7450, REVFMT_MAJMIN }, 217 { "7455", MPC7455, REVFMT_MAJMIN }, 218 { "7457", MPC7457, REVFMT_MAJMIN }, 219 { "7447A", MPC7447A, REVFMT_MAJMIN }, 220 { "7448", MPC7448, REVFMT_MAJMIN }, 221 { "8240", MPC8240, REVFMT_MAJMIN }, 222 { "8245", MPC8245, REVFMT_MAJMIN }, 223 { "970", IBM970, REVFMT_MAJMIN }, 224 { "970FX", IBM970FX, REVFMT_MAJMIN }, 225 { "970MP", IBM970MP, REVFMT_MAJMIN }, 226 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 227 { "", 0, REVFMT_HEX } 228 }; 229 230 #ifdef MULTIPROCESSOR 231 struct cpu_info cpu_info[CPU_MAXNUM] = { 232 [0] = { 233 .ci_curlwp = &lwp0, 234 .ci_fpulwp = &lwp0, 235 .ci_veclwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 extern int ticks_per_intr; 241 #include <powerpc/oea/bat.h> 242 #include <arch/powerpc/pic/picvar.h> 243 #include <arch/powerpc/pic/ipivar.h> 244 extern struct bat battable[]; 245 #else 246 struct cpu_info cpu_info[1] = { 247 [0] = { 248 .ci_curlwp = &lwp0, 249 .ci_fpulwp = &lwp0, 250 .ci_veclwp = &lwp0, 251 }, 252 }; 253 #endif /*MULTIPROCESSOR*/ 254 255 int cpu_altivec; 256 int cpu_psluserset, cpu_pslusermod; 257 char cpu_model[80]; 258 259 /* This is to be called from locore.S, and nowhere else. */ 260 261 void 262 cpu_model_init(void) 263 { 264 u_int pvr, vers; 265 266 pvr = mfpvr(); 267 vers = pvr >> 16; 268 269 oeacpufeat = 0; 270 271 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 272 vers == IBMCELL || vers == IBMPOWER6P5) 273 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 274 275 else if (vers == MPC601) 276 oeacpufeat |= OEACPU_601; 277 278 else if (MPC745X_P(vers) && vers != MPC7450) 279 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 280 } 281 282 void 283 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 284 { 285 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 286 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 287 (data & fmt->fmt_mask) == fmt->fmt_value) 288 aprint_normal("%s", fmt->fmt_string); 289 } 290 } 291 292 void 293 cpu_idlespin(void) 294 { 295 register_t msr; 296 297 if (powersave <= 0) 298 return; 299 300 __asm volatile( 301 "sync;" 302 "mfmsr %0;" 303 "oris %0,%0,%1@h;" /* enter power saving mode */ 304 "mtmsr %0;" 305 "isync;" 306 : "=r"(msr) 307 : "J"(PSL_POW)); 308 } 309 310 void 311 cpu_probe_cache(void) 312 { 313 u_int assoc, pvr, vers; 314 315 pvr = mfpvr(); 316 vers = pvr >> 16; 317 318 319 /* Presently common across almost all implementations. */ 320 curcpu()->ci_ci.dcache_line_size = 32; 321 curcpu()->ci_ci.icache_line_size = 32; 322 323 324 switch (vers) { 325 #define K *1024 326 case IBM750FX: 327 case MPC601: 328 case MPC750: 329 case MPC7400: 330 case MPC7447A: 331 case MPC7448: 332 case MPC7450: 333 case MPC7455: 334 case MPC7457: 335 curcpu()->ci_ci.dcache_size = 32 K; 336 curcpu()->ci_ci.icache_size = 32 K; 337 assoc = 8; 338 break; 339 case MPC603: 340 curcpu()->ci_ci.dcache_size = 8 K; 341 curcpu()->ci_ci.icache_size = 8 K; 342 assoc = 2; 343 break; 344 case MPC603e: 345 case MPC603ev: 346 case MPC604: 347 case MPC8240: 348 case MPC8245: 349 case MPCG2: 350 curcpu()->ci_ci.dcache_size = 16 K; 351 curcpu()->ci_ci.icache_size = 16 K; 352 assoc = 4; 353 break; 354 case MPC604e: 355 case MPC604ev: 356 curcpu()->ci_ci.dcache_size = 32 K; 357 curcpu()->ci_ci.icache_size = 32 K; 358 assoc = 4; 359 break; 360 case IBMPOWER3II: 361 curcpu()->ci_ci.dcache_size = 64 K; 362 curcpu()->ci_ci.icache_size = 32 K; 363 curcpu()->ci_ci.dcache_line_size = 128; 364 curcpu()->ci_ci.icache_line_size = 128; 365 assoc = 128; /* not a typo */ 366 break; 367 case IBM970: 368 case IBM970FX: 369 case IBM970MP: 370 curcpu()->ci_ci.dcache_size = 32 K; 371 curcpu()->ci_ci.icache_size = 64 K; 372 curcpu()->ci_ci.dcache_line_size = 128; 373 curcpu()->ci_ci.icache_line_size = 128; 374 assoc = 2; 375 break; 376 377 default: 378 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 379 curcpu()->ci_ci.icache_size = PAGE_SIZE; 380 assoc = 1; 381 #undef K 382 } 383 384 /* 385 * Possibly recolor. 386 */ 387 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 388 } 389 390 struct cpu_info * 391 cpu_attach_common(device_t self, int id) 392 { 393 struct cpu_info *ci; 394 u_int pvr, vers; 395 396 ci = &cpu_info[id]; 397 #ifndef MULTIPROCESSOR 398 /* 399 * If this isn't the primary CPU, print an error message 400 * and just bail out. 401 */ 402 if (id != 0) { 403 aprint_normal(": ID %d\n", id); 404 aprint_normal("%s: processor off-line; multiprocessor support " 405 "not present in kernel\n", self->dv_xname); 406 return (NULL); 407 } 408 #endif 409 410 ci->ci_cpuid = id; 411 ci->ci_idepth = -1; 412 ci->ci_dev = self; 413 ci->ci_idlespin = cpu_idlespin; 414 415 pvr = mfpvr(); 416 vers = (pvr >> 16) & 0xffff; 417 418 switch (id) { 419 case 0: 420 /* load my cpu_number to PIR */ 421 switch (vers) { 422 case MPC601: 423 case MPC604: 424 case MPC604e: 425 case MPC604ev: 426 case MPC7400: 427 case MPC7410: 428 case MPC7447A: 429 case MPC7448: 430 case MPC7450: 431 case MPC7455: 432 case MPC7457: 433 mtspr(SPR_PIR, id); 434 } 435 cpu_setup(self, ci); 436 break; 437 default: 438 if (id >= CPU_MAXNUM) { 439 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 440 panic("cpuattach"); 441 } 442 #ifndef MULTIPROCESSOR 443 aprint_normal(" not configured\n"); 444 return NULL; 445 #else 446 mi_cpu_attach(ci); 447 break; 448 #endif 449 } 450 return (ci); 451 } 452 453 void 454 cpu_setup(device_t self, struct cpu_info *ci) 455 { 456 u_int hid0, hid0_save, pvr, vers; 457 const char *bitmask; 458 char hidbuf[128]; 459 char model[80]; 460 461 pvr = mfpvr(); 462 vers = (pvr >> 16) & 0xffff; 463 464 cpu_identify(model, sizeof(model)); 465 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 466 cpu_number() == 0 ? " (primary)" : ""); 467 468 /* set the cpu number */ 469 ci->ci_cpuid = cpu_number(); 470 hid0_save = hid0 = mfspr(SPR_HID0); 471 472 cpu_probe_cache(); 473 474 /* 475 * Configure power-saving mode. 476 */ 477 switch (vers) { 478 case MPC604: 479 case MPC604e: 480 case MPC604ev: 481 /* 482 * Do not have HID0 support settings, but can support 483 * MSR[POW] off 484 */ 485 powersave = 1; 486 break; 487 488 case MPC603: 489 case MPC603e: 490 case MPC603ev: 491 case MPC7400: 492 case MPC7410: 493 case MPC8240: 494 case MPC8245: 495 case MPCG2: 496 /* Select DOZE mode. */ 497 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 498 hid0 |= HID0_DOZE | HID0_DPM; 499 powersave = 1; 500 break; 501 502 case MPC750: 503 case IBM750FX: 504 /* Select NAP mode. */ 505 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 506 hid0 |= HID0_NAP | HID0_DPM; 507 powersave = 1; 508 break; 509 510 case MPC7447A: 511 case MPC7448: 512 case MPC7457: 513 case MPC7455: 514 case MPC7450: 515 /* Enable the 7450 branch caches */ 516 hid0 |= HID0_SGE | HID0_BTIC; 517 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 518 /* Enable more and larger BAT registers */ 519 if (oeacpufeat & OEACPU_XBSEN) 520 hid0 |= HID0_XBSEN; 521 if (oeacpufeat & OEACPU_HIGHBAT) 522 hid0 |= HID0_HIGH_BAT_EN; 523 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 524 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 525 hid0 &= ~HID0_BTIC; 526 /* Select NAP mode. */ 527 hid0 &= ~HID0_SLEEP; 528 hid0 |= HID0_NAP | HID0_DPM; 529 powersave = 1; 530 break; 531 532 case IBM970: 533 case IBM970FX: 534 case IBM970MP: 535 case IBMPOWER3II: 536 default: 537 /* No power-saving mode is available. */ ; 538 } 539 540 #ifdef NAPMODE 541 switch (vers) { 542 case IBM750FX: 543 case MPC750: 544 case MPC7400: 545 /* Select NAP mode. */ 546 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 547 hid0 |= HID0_NAP; 548 break; 549 } 550 #endif 551 552 switch (vers) { 553 case IBM750FX: 554 case MPC750: 555 hid0 &= ~HID0_DBP; /* XXX correct? */ 556 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 557 break; 558 559 case MPC7400: 560 case MPC7410: 561 hid0 &= ~HID0_SPD; 562 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 563 hid0 |= HID0_EIEC; 564 break; 565 } 566 567 if (hid0 != hid0_save) { 568 mtspr(SPR_HID0, hid0); 569 __asm volatile("sync;isync"); 570 } 571 572 573 switch (vers) { 574 case MPC601: 575 bitmask = HID0_601_BITMASK; 576 break; 577 case MPC7450: 578 case MPC7455: 579 case MPC7457: 580 bitmask = HID0_7450_BITMASK; 581 break; 582 case IBM970: 583 case IBM970FX: 584 case IBM970MP: 585 bitmask = 0; 586 break; 587 default: 588 bitmask = HID0_BITMASK; 589 break; 590 } 591 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 592 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 593 powersave); 594 595 ci->ci_khz = 0; 596 597 /* 598 * Display speed and cache configuration. 599 */ 600 switch (vers) { 601 case MPC604: 602 case MPC604e: 603 case MPC604ev: 604 case MPC750: 605 case IBM750FX: 606 case MPC7400: 607 case MPC7410: 608 case MPC7447A: 609 case MPC7448: 610 case MPC7450: 611 case MPC7455: 612 case MPC7457: 613 aprint_normal("%s: ", self->dv_xname); 614 cpu_probe_speed(ci); 615 aprint_normal("%u.%02u MHz", 616 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 617 switch (vers) { 618 case MPC7450: /* 7441 does not have L3! */ 619 case MPC7455: /* 7445 does not have L3! */ 620 case MPC7457: /* 7447 does not have L3! */ 621 cpu_config_l3cr(vers); 622 break; 623 case IBM750FX: 624 case MPC750: 625 case MPC7400: 626 case MPC7410: 627 case MPC7447A: 628 case MPC7448: 629 cpu_config_l2cr(pvr); 630 break; 631 default: 632 break; 633 } 634 aprint_normal("\n"); 635 break; 636 } 637 638 #if NSYSMON_ENVSYS > 0 639 /* 640 * Attach MPC750 temperature sensor to the envsys subsystem. 641 * XXX the 74xx series also has this sensor, but it is not 642 * XXX supported by Motorola and may return values that are off by 643 * XXX 35-55 degrees C. 644 */ 645 if (vers == MPC750 || vers == IBM750FX) 646 cpu_tau_setup(ci); 647 #endif 648 649 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 650 NULL, self->dv_xname, "clock"); 651 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 652 NULL, self->dv_xname, "soft clock"); 653 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 654 NULL, self->dv_xname, "soft net"); 655 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 656 NULL, self->dv_xname, "soft serial"); 657 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 658 NULL, self->dv_xname, "traps"); 659 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 660 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 661 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 662 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 663 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 664 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 665 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 666 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 667 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 668 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 669 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 670 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 671 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 672 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 673 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 674 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 675 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 676 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 677 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 678 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 679 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 680 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 681 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 682 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 683 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 684 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 685 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 686 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 687 #ifdef ALTIVEC 688 if (cpu_altivec) { 689 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 690 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 691 } 692 #endif 693 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 694 NULL, self->dv_xname, "IPIs"); 695 } 696 697 /* 698 * According to a document labeled "PVR Register Settings": 699 ** For integrated microprocessors the PVR register inside the device 700 ** will identify the version of the microprocessor core. You must also 701 ** read the Device ID, PCI register 02, to identify the part and the 702 ** Revision ID, PCI register 08, to identify the revision of the 703 ** integrated microprocessor. 704 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 705 */ 706 707 void 708 cpu_identify(char *str, size_t len) 709 { 710 u_int pvr, major, minor; 711 uint16_t vers, rev, revfmt; 712 const struct cputab *cp; 713 const char *name; 714 size_t n; 715 716 pvr = mfpvr(); 717 vers = pvr >> 16; 718 rev = pvr; 719 720 switch (vers) { 721 case MPC7410: 722 minor = (pvr >> 0) & 0xff; 723 major = minor <= 4 ? 1 : 2; 724 break; 725 case MPCG2: /*XXX see note above */ 726 major = (pvr >> 4) & 0xf; 727 minor = (pvr >> 0) & 0xf; 728 break; 729 default: 730 major = (pvr >> 8) & 0xf; 731 minor = (pvr >> 0) & 0xf; 732 } 733 734 for (cp = models; cp->name[0] != '\0'; cp++) { 735 if (cp->version == vers) 736 break; 737 } 738 739 if (str == NULL) { 740 str = cpu_model; 741 len = sizeof(cpu_model); 742 cpu = vers; 743 } 744 745 revfmt = cp->revfmt; 746 name = cp->name; 747 if (rev == MPC750 && pvr == 15) { 748 name = "755"; 749 revfmt = REVFMT_HEX; 750 } 751 752 if (cp->name[0] != '\0') { 753 n = snprintf(str, len, "%s (Revision ", cp->name); 754 } else { 755 n = snprintf(str, len, "Version %#x (Revision ", vers); 756 } 757 if (len > n) { 758 switch (revfmt) { 759 case REVFMT_MAJMIN: 760 snprintf(str + n, len - n, "%u.%u)", major, minor); 761 break; 762 case REVFMT_HEX: 763 snprintf(str + n, len - n, "0x%04x)", rev); 764 break; 765 case REVFMT_DEC: 766 snprintf(str + n, len - n, "%u)", rev); 767 break; 768 } 769 } 770 } 771 772 #ifdef L2CR_CONFIG 773 u_int l2cr_config = L2CR_CONFIG; 774 #else 775 u_int l2cr_config = 0; 776 #endif 777 778 #ifdef L3CR_CONFIG 779 u_int l3cr_config = L3CR_CONFIG; 780 #else 781 u_int l3cr_config = 0; 782 #endif 783 784 void 785 cpu_enable_l2cr(register_t l2cr) 786 { 787 register_t msr, x; 788 uint16_t vers; 789 790 vers = mfpvr() >> 16; 791 792 /* Disable interrupts and set the cache config bits. */ 793 msr = mfmsr(); 794 mtmsr(msr & ~PSL_EE); 795 #ifdef ALTIVEC 796 if (cpu_altivec) 797 __asm volatile("dssall"); 798 #endif 799 __asm volatile("sync"); 800 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 801 __asm volatile("sync"); 802 803 /* Wait for L2 clock to be stable (640 L2 clocks). */ 804 delay(100); 805 806 /* Invalidate all L2 contents. */ 807 if (MPC745X_P(vers)) { 808 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 809 do { 810 x = mfspr(SPR_L2CR); 811 } while (x & L2CR_L2I); 812 } else { 813 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 814 do { 815 x = mfspr(SPR_L2CR); 816 } while (x & L2CR_L2IP); 817 } 818 /* Enable L2 cache. */ 819 l2cr |= L2CR_L2E; 820 mtspr(SPR_L2CR, l2cr); 821 mtmsr(msr); 822 } 823 824 void 825 cpu_enable_l3cr(register_t l3cr) 826 { 827 register_t x; 828 829 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 830 831 /* 832 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 833 * L3CLKEN. (also mask off reserved bits in case they were included 834 * in L3CR_CONFIG) 835 */ 836 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 837 mtspr(SPR_L3CR, l3cr); 838 839 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 840 l3cr |= 0x04000000; 841 mtspr(SPR_L3CR, l3cr); 842 843 /* 3: Set L3CLKEN to 1*/ 844 l3cr |= L3CR_L3CLKEN; 845 mtspr(SPR_L3CR, l3cr); 846 847 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 848 __asm volatile("dssall;sync"); 849 /* L3 cache is already disabled, no need to clear L3E */ 850 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 851 do { 852 x = mfspr(SPR_L3CR); 853 } while (x & L3CR_L3I); 854 855 /* 6: Clear L3CLKEN to 0 */ 856 l3cr &= ~L3CR_L3CLKEN; 857 mtspr(SPR_L3CR, l3cr); 858 859 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 860 __asm volatile("sync"); 861 delay(100); 862 863 /* 8: Set L3E and L3CLKEN */ 864 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 865 mtspr(SPR_L3CR, l3cr); 866 867 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 868 __asm volatile("sync"); 869 delay(100); 870 } 871 872 void 873 cpu_config_l2cr(int pvr) 874 { 875 register_t l2cr; 876 u_int vers = (pvr >> 16) & 0xffff; 877 878 l2cr = mfspr(SPR_L2CR); 879 880 /* 881 * For MP systems, the firmware may only configure the L2 cache 882 * on the first CPU. In this case, assume that the other CPUs 883 * should use the same value for L2CR. 884 */ 885 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 886 l2cr_config = l2cr; 887 } 888 889 /* 890 * Configure L2 cache if not enabled. 891 */ 892 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 893 cpu_enable_l2cr(l2cr_config); 894 l2cr = mfspr(SPR_L2CR); 895 } 896 897 if ((l2cr & L2CR_L2E) == 0) { 898 aprint_normal(" L2 cache present but not enabled "); 899 return; 900 } 901 aprint_normal(","); 902 903 switch (vers) { 904 case IBM750FX: 905 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 906 break; 907 case MPC750: 908 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 909 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 910 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 911 else 912 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 913 break; 914 case MPC7447A: 915 case MPC7457: 916 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 917 return; 918 case MPC7448: 919 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 920 return; 921 case MPC7450: 922 case MPC7455: 923 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 924 break; 925 default: 926 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 927 break; 928 } 929 } 930 931 void 932 cpu_config_l3cr(int vers) 933 { 934 register_t l2cr; 935 register_t l3cr; 936 937 l2cr = mfspr(SPR_L2CR); 938 939 /* 940 * For MP systems, the firmware may only configure the L2 cache 941 * on the first CPU. In this case, assume that the other CPUs 942 * should use the same value for L2CR. 943 */ 944 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 945 l2cr_config = l2cr; 946 } 947 948 /* 949 * Configure L2 cache if not enabled. 950 */ 951 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 952 cpu_enable_l2cr(l2cr_config); 953 l2cr = mfspr(SPR_L2CR); 954 } 955 956 aprint_normal(","); 957 switch (vers) { 958 case MPC7447A: 959 case MPC7457: 960 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 961 return; 962 case MPC7448: 963 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 964 return; 965 default: 966 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 967 break; 968 } 969 970 l3cr = mfspr(SPR_L3CR); 971 972 /* 973 * For MP systems, the firmware may only configure the L3 cache 974 * on the first CPU. In this case, assume that the other CPUs 975 * should use the same value for L3CR. 976 */ 977 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 978 l3cr_config = l3cr; 979 } 980 981 /* 982 * Configure L3 cache if not enabled. 983 */ 984 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 985 cpu_enable_l3cr(l3cr_config); 986 l3cr = mfspr(SPR_L3CR); 987 } 988 989 if (l3cr & L3CR_L3E) { 990 aprint_normal(","); 991 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 992 } 993 } 994 995 void 996 cpu_probe_speed(struct cpu_info *ci) 997 { 998 uint64_t cps; 999 1000 mtspr(SPR_MMCR0, MMCR0_FC); 1001 mtspr(SPR_PMC1, 0); 1002 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1003 delay(100000); 1004 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1005 1006 mtspr(SPR_MMCR0, MMCR0_FC); 1007 1008 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1009 } 1010 1011 /* 1012 * Read the Dynamic Frequency Switching state and return a divisor for 1013 * the maximum frequency. 1014 */ 1015 int 1016 cpu_get_dfs(void) 1017 { 1018 u_int pvr, vers; 1019 1020 pvr = mfpvr(); 1021 vers = pvr >> 16; 1022 1023 switch (vers) { 1024 case MPC7448: 1025 if (mfspr(SPR_HID1) & HID1_DFS4) 1026 return 4; 1027 case MPC7447A: 1028 if (mfspr(SPR_HID1) & HID1_DFS2) 1029 return 2; 1030 } 1031 return 1; 1032 } 1033 1034 /* 1035 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1036 */ 1037 void 1038 cpu_set_dfs(int div) 1039 { 1040 uint64_t where; 1041 u_int dfs_mask, pvr, vers; 1042 1043 pvr = mfpvr(); 1044 vers = pvr >> 16; 1045 dfs_mask = 0; 1046 1047 switch (vers) { 1048 case MPC7448: 1049 dfs_mask |= HID1_DFS4; 1050 case MPC7447A: 1051 dfs_mask |= HID1_DFS2; 1052 break; 1053 default: 1054 printf("cpu_set_dfs: DFS not supported\n"); 1055 return; 1056 1057 } 1058 1059 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1060 xc_wait(where); 1061 } 1062 1063 static void 1064 cpu_set_dfs_xcall(void *arg1, void *arg2) 1065 { 1066 u_int dfs_mask, hid1, old_hid1; 1067 int *divisor, s; 1068 1069 divisor = arg1; 1070 dfs_mask = *(u_int *)arg2; 1071 1072 s = splhigh(); 1073 hid1 = old_hid1 = mfspr(SPR_HID1); 1074 1075 switch (*divisor) { 1076 case 1: 1077 hid1 &= ~dfs_mask; 1078 break; 1079 case 2: 1080 hid1 &= ~(dfs_mask & HID1_DFS4); 1081 hid1 |= dfs_mask & HID1_DFS2; 1082 break; 1083 case 4: 1084 hid1 &= ~(dfs_mask & HID1_DFS2); 1085 hid1 |= dfs_mask & HID1_DFS4; 1086 break; 1087 } 1088 1089 if (hid1 != old_hid1) { 1090 __asm volatile("sync"); 1091 mtspr(SPR_HID1, hid1); 1092 __asm volatile("sync;isync"); 1093 } 1094 1095 splx(s); 1096 } 1097 1098 #if NSYSMON_ENVSYS > 0 1099 void 1100 cpu_tau_setup(struct cpu_info *ci) 1101 { 1102 struct sysmon_envsys *sme; 1103 int error, therm_delay; 1104 1105 mtspr(SPR_THRM1, SPR_THRM_VALID); 1106 mtspr(SPR_THRM2, 0); 1107 1108 /* 1109 * we need to figure out how much 20+us in units of CPU clock cycles 1110 * are 1111 */ 1112 1113 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1114 1115 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1116 1117 sme = sysmon_envsys_create(); 1118 1119 sensor.units = ENVSYS_STEMP; 1120 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1121 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1122 sysmon_envsys_destroy(sme); 1123 return; 1124 } 1125 1126 sme->sme_name = ci->ci_dev->dv_xname; 1127 sme->sme_cookie = ci; 1128 sme->sme_refresh = cpu_tau_refresh; 1129 1130 if ((error = sysmon_envsys_register(sme)) != 0) { 1131 aprint_error("%s: unable to register with sysmon (%d)\n", 1132 ci->ci_dev->dv_xname, error); 1133 sysmon_envsys_destroy(sme); 1134 } 1135 } 1136 1137 1138 /* Find the temperature of the CPU. */ 1139 void 1140 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1141 { 1142 int i, threshold, count; 1143 1144 threshold = 64; /* Half of the 7-bit sensor range */ 1145 1146 /* Successive-approximation code adapted from Motorola 1147 * application note AN1800/D, "Programming the Thermal Assist 1148 * Unit in the MPC750 Microprocessor". 1149 */ 1150 for (i = 5; i >= 0 ; i--) { 1151 mtspr(SPR_THRM1, 1152 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1153 count = 0; 1154 while ((count < 100000) && 1155 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1156 count++; 1157 delay(1); 1158 } 1159 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1160 /* The interrupt bit was set, meaning the 1161 * temperature was above the threshold 1162 */ 1163 threshold += 1 << i; 1164 } else { 1165 /* Temperature was below the threshold */ 1166 threshold -= 1 << i; 1167 } 1168 1169 } 1170 threshold += 2; 1171 1172 /* Convert the temperature in degrees C to microkelvin */ 1173 edata->value_cur = (threshold * 1000000) + 273150000; 1174 edata->state = ENVSYS_SVALID; 1175 } 1176 #endif /* NSYSMON_ENVSYS > 0 */ 1177 1178 #ifdef MULTIPROCESSOR 1179 extern volatile u_int cpu_spinstart_ack; 1180 1181 int 1182 cpu_spinup(device_t self, struct cpu_info *ci) 1183 { 1184 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1185 struct pglist mlist; 1186 int i, error, pvr, vers; 1187 char *hp; 1188 1189 pvr = mfpvr(); 1190 vers = pvr >> 16; 1191 KASSERT(ci != curcpu()); 1192 1193 /* Now allocate a hatch stack */ 1194 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1195 &mlist, 1, 1); 1196 if (error) { 1197 aprint_error(": unable to allocate hatch stack\n"); 1198 return -1; 1199 } 1200 1201 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1202 memset(hp, 0, 0x1000); 1203 1204 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1205 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1206 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1207 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1208 1209 cpu_hatch_data = h; 1210 h->running = 0; 1211 h->self = self; 1212 h->ci = ci; 1213 h->pir = ci->ci_cpuid; 1214 1215 cpu_hatch_stack = (uint32_t)hp; 1216 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1217 1218 /* copy special registers */ 1219 1220 h->hid0 = mfspr(SPR_HID0); 1221 1222 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1223 for (i = 0; i < 16; i++) { 1224 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1225 "r"(i << ADDR_SR_SHFT)); 1226 } 1227 if (oeacpufeat & OEACPU_64) 1228 h->asr = mfspr(SPR_ASR); 1229 else 1230 h->asr = 0; 1231 1232 /* copy the bat regs */ 1233 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1234 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1235 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1236 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1237 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1238 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1239 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1240 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1241 __asm volatile ("sync; isync"); 1242 1243 if (md_setup_trampoline(h, ci) == -1) 1244 return -1; 1245 md_presync_timebase(h); 1246 md_start_timebase(h); 1247 1248 /* wait for secondary printf */ 1249 1250 delay(200000); 1251 1252 if (h->running < 1) { 1253 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1254 ci->ci_cpuid, cpu_spinstart_ack); 1255 Debugger(); 1256 return -1; 1257 } 1258 1259 /* Register IPI Interrupt */ 1260 if (ipiops.ppc_establish_ipi) 1261 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1262 1263 return 0; 1264 } 1265 1266 static volatile int start_secondary_cpu; 1267 extern void tlbia(void); 1268 1269 register_t 1270 cpu_hatch(void) 1271 { 1272 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1273 struct cpu_info * const ci = h->ci; 1274 struct pcb *pcb; 1275 u_int msr; 1276 int i; 1277 1278 /* Initialize timebase. */ 1279 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1280 1281 /* 1282 * Set PIR (Processor Identification Register). i.e. whoami 1283 * Note that PIR is read-only on some CPU versions, so we write to it 1284 * only if it has a different value than we need. 1285 */ 1286 1287 msr = mfspr(SPR_PIR); 1288 if (msr != h->pir) 1289 mtspr(SPR_PIR, h->pir); 1290 1291 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1292 cpu_spinstart_ack = 0; 1293 1294 /* Initialize MMU. */ 1295 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1296 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1297 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1298 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1299 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1300 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1301 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1302 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1303 1304 mtspr(SPR_HID0, h->hid0); 1305 1306 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1307 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1308 1309 __asm volatile ("sync"); 1310 for (i = 0; i < 16; i++) 1311 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1312 __asm volatile ("sync; isync"); 1313 1314 if (oeacpufeat & OEACPU_64) 1315 mtspr(SPR_ASR, h->asr); 1316 1317 cpu_spinstart_ack = 1; 1318 __asm ("ptesync"); 1319 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1320 __asm volatile ("sync; isync"); 1321 1322 cpu_spinstart_ack = 5; 1323 for (i = 0; i < 16; i++) 1324 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1325 "r"(i << ADDR_SR_SHFT)); 1326 1327 /* Enable I/D address translations. */ 1328 msr = mfmsr(); 1329 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1330 mtmsr(msr); 1331 __asm volatile ("sync; isync"); 1332 cpu_spinstart_ack = 2; 1333 1334 md_sync_timebase(h); 1335 1336 cpu_setup(h->self, ci); 1337 1338 h->running = 1; 1339 __asm volatile ("sync; isync"); 1340 1341 while (start_secondary_cpu == 0) 1342 ; 1343 1344 __asm volatile ("sync; isync"); 1345 1346 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1347 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1348 1349 md_setup_interrupts(); 1350 1351 ci->ci_ipending = 0; 1352 ci->ci_cpl = 0; 1353 1354 mtmsr(mfmsr() | PSL_EE); 1355 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1356 return pcb->pcb_sp; 1357 } 1358 1359 void 1360 cpu_boot_secondary_processors(void) 1361 { 1362 start_secondary_cpu = 1; 1363 __asm volatile ("sync"); 1364 } 1365 1366 #endif /*MULTIPROCESSOR*/ 1367