1 /* $NetBSD: cpu_subr.c,v 1.82 2014/03/24 19:29:59 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.82 2014/03/24 19:29:59 christos Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu = -1; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't realy matter since none of them supports SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 #define HATCH_STACK_SIZE 0x1000 241 extern int ticks_per_intr; 242 #include <powerpc/oea/bat.h> 243 #include <powerpc/pic/picvar.h> 244 #include <powerpc/pic/ipivar.h> 245 extern struct bat battable[]; 246 #else 247 struct cpu_info cpu_info[1] = { 248 [0] = { 249 .ci_curlwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 register_t cpu_psluserset; 256 register_t cpu_pslusermod; 257 register_t cpu_pslusermask = 0xffff; 258 259 /* This is to be called from locore.S, and nowhere else. */ 260 261 void 262 cpu_model_init(void) 263 { 264 u_int pvr, vers; 265 266 pvr = mfpvr(); 267 vers = pvr >> 16; 268 269 oeacpufeat = 0; 270 271 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 272 vers == IBMCELL || vers == IBMPOWER6P5) { 273 oeacpufeat |= OEACPU_64; 274 oeacpufeat |= OEACPU_64_BRIDGE; 275 oeacpufeat |= OEACPU_NOBAT; 276 277 } else if (vers == MPC601) { 278 oeacpufeat |= OEACPU_601; 279 280 } else if (MPC745X_P(vers)) { 281 register_t hid1 = mfspr(SPR_HID1); 282 283 if (vers != MPC7450) { 284 register_t hid0 = mfspr(SPR_HID0); 285 286 /* Enable more SPRG registers */ 287 oeacpufeat |= OEACPU_HIGHSPRG; 288 289 /* Enable more BAT registers */ 290 oeacpufeat |= OEACPU_HIGHBAT; 291 hid0 |= HID0_HIGH_BAT_EN; 292 293 /* Enable larger BAT registers */ 294 oeacpufeat |= OEACPU_XBSEN; 295 hid0 |= HID0_XBSEN; 296 297 mtspr(SPR_HID0, hid0); 298 __asm volatile("sync;isync"); 299 } 300 301 /* Enable address broadcasting for MP systems */ 302 hid1 |= HID1_SYNCBE | HID1_ABE; 303 304 mtspr(SPR_HID1, hid1); 305 __asm volatile("sync;isync"); 306 307 } else if (vers == IBM750FX || vers == IBM750GX) { 308 oeacpufeat |= OEACPU_HIGHBAT; 309 } 310 } 311 312 void 313 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 314 { 315 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 316 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 317 (data & fmt->fmt_mask) == fmt->fmt_value) 318 aprint_normal("%s", fmt->fmt_string); 319 } 320 } 321 322 void 323 cpu_idlespin(void) 324 { 325 register_t msr; 326 327 if (powersave <= 0) 328 return; 329 330 __asm volatile( 331 "sync;" 332 "mfmsr %0;" 333 "oris %0,%0,%1@h;" /* enter power saving mode */ 334 "mtmsr %0;" 335 "isync;" 336 : "=r"(msr) 337 : "J"(PSL_POW)); 338 } 339 340 void 341 cpu_probe_cache(void) 342 { 343 u_int assoc, pvr, vers; 344 345 pvr = mfpvr(); 346 vers = pvr >> 16; 347 348 349 /* Presently common across almost all implementations. */ 350 curcpu()->ci_ci.dcache_line_size = 32; 351 curcpu()->ci_ci.icache_line_size = 32; 352 353 354 switch (vers) { 355 #define K *1024 356 case IBM750FX: 357 case IBM750GX: 358 case MPC601: 359 case MPC750: 360 case MPC7400: 361 case MPC7447A: 362 case MPC7448: 363 case MPC7450: 364 case MPC7455: 365 case MPC7457: 366 curcpu()->ci_ci.dcache_size = 32 K; 367 curcpu()->ci_ci.icache_size = 32 K; 368 assoc = 8; 369 break; 370 case MPC603: 371 curcpu()->ci_ci.dcache_size = 8 K; 372 curcpu()->ci_ci.icache_size = 8 K; 373 assoc = 2; 374 break; 375 case MPC603e: 376 case MPC603ev: 377 case MPC604: 378 case MPC8240: 379 case MPC8245: 380 case MPCG2: 381 curcpu()->ci_ci.dcache_size = 16 K; 382 curcpu()->ci_ci.icache_size = 16 K; 383 assoc = 4; 384 break; 385 case MPC604e: 386 case MPC604ev: 387 curcpu()->ci_ci.dcache_size = 32 K; 388 curcpu()->ci_ci.icache_size = 32 K; 389 assoc = 4; 390 break; 391 case IBMPOWER3II: 392 curcpu()->ci_ci.dcache_size = 64 K; 393 curcpu()->ci_ci.icache_size = 32 K; 394 curcpu()->ci_ci.dcache_line_size = 128; 395 curcpu()->ci_ci.icache_line_size = 128; 396 assoc = 128; /* not a typo */ 397 break; 398 case IBM970: 399 case IBM970FX: 400 case IBM970MP: 401 curcpu()->ci_ci.dcache_size = 32 K; 402 curcpu()->ci_ci.icache_size = 64 K; 403 curcpu()->ci_ci.dcache_line_size = 128; 404 curcpu()->ci_ci.icache_line_size = 128; 405 assoc = 2; 406 break; 407 408 default: 409 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 410 curcpu()->ci_ci.icache_size = PAGE_SIZE; 411 assoc = 1; 412 #undef K 413 } 414 415 /* 416 * Possibly recolor. 417 */ 418 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 419 } 420 421 struct cpu_info * 422 cpu_attach_common(device_t self, int id) 423 { 424 struct cpu_info *ci; 425 u_int pvr, vers; 426 427 ci = &cpu_info[id]; 428 #ifndef MULTIPROCESSOR 429 /* 430 * If this isn't the primary CPU, print an error message 431 * and just bail out. 432 */ 433 if (id != 0) { 434 aprint_naive("\n"); 435 aprint_normal(": ID %d\n", id); 436 aprint_normal_dev(self, 437 "processor off-line; " 438 "multiprocessor support not present in kernel\n"); 439 return (NULL); 440 } 441 #endif 442 443 ci->ci_cpuid = id; 444 ci->ci_idepth = -1; 445 ci->ci_dev = self; 446 ci->ci_idlespin = cpu_idlespin; 447 448 pvr = mfpvr(); 449 vers = (pvr >> 16) & 0xffff; 450 451 switch (id) { 452 case 0: 453 /* load my cpu_number to PIR */ 454 switch (vers) { 455 case MPC601: 456 case MPC604: 457 case MPC604e: 458 case MPC604ev: 459 case MPC7400: 460 case MPC7410: 461 case MPC7447A: 462 case MPC7448: 463 case MPC7450: 464 case MPC7455: 465 case MPC7457: 466 mtspr(SPR_PIR, id); 467 } 468 cpu_setup(self, ci); 469 break; 470 default: 471 aprint_naive("\n"); 472 if (id >= CPU_MAXNUM) { 473 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 474 panic("cpuattach"); 475 } 476 #ifndef MULTIPROCESSOR 477 aprint_normal(" not configured\n"); 478 return NULL; 479 #else 480 mi_cpu_attach(ci); 481 break; 482 #endif 483 } 484 return (ci); 485 } 486 487 void 488 cpu_setup(device_t self, struct cpu_info *ci) 489 { 490 u_int hid0, hid0_save, pvr, vers; 491 const char * const xname = device_xname(self); 492 const char *bitmask; 493 char hidbuf[128]; 494 char model[80]; 495 496 pvr = mfpvr(); 497 vers = (pvr >> 16) & 0xffff; 498 499 cpu_identify(model, sizeof(model)); 500 aprint_naive("\n"); 501 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 502 cpu_number() == 0 ? " (primary)" : ""); 503 504 /* set the cpu number */ 505 ci->ci_cpuid = cpu_number(); 506 hid0_save = hid0 = mfspr(SPR_HID0); 507 508 cpu_probe_cache(); 509 510 /* 511 * Configure power-saving mode. 512 */ 513 switch (vers) { 514 case MPC604: 515 case MPC604e: 516 case MPC604ev: 517 /* 518 * Do not have HID0 support settings, but can support 519 * MSR[POW] off 520 */ 521 powersave = 1; 522 break; 523 524 case MPC603: 525 case MPC603e: 526 case MPC603ev: 527 case MPC7400: 528 case MPC7410: 529 case MPC8240: 530 case MPC8245: 531 case MPCG2: 532 /* Select DOZE mode. */ 533 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 534 hid0 |= HID0_DOZE | HID0_DPM; 535 powersave = 1; 536 break; 537 538 case MPC750: 539 case IBM750FX: 540 case IBM750GX: 541 /* Select NAP mode. */ 542 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 543 hid0 |= HID0_NAP | HID0_DPM; 544 powersave = 1; 545 break; 546 547 case MPC7447A: 548 case MPC7448: 549 case MPC7457: 550 case MPC7455: 551 case MPC7450: 552 /* Enable the 7450 branch caches */ 553 hid0 |= HID0_SGE | HID0_BTIC; 554 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 555 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 556 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 557 hid0 &= ~HID0_BTIC; 558 /* Select NAP mode. */ 559 hid0 &= ~HID0_SLEEP; 560 hid0 |= HID0_NAP | HID0_DPM; 561 powersave = 1; 562 break; 563 564 case IBM970: 565 case IBM970FX: 566 case IBM970MP: 567 case IBMPOWER3II: 568 default: 569 /* No power-saving mode is available. */ ; 570 } 571 572 #ifdef NAPMODE 573 switch (vers) { 574 case IBM750FX: 575 case IBM750GX: 576 case MPC750: 577 case MPC7400: 578 /* Select NAP mode. */ 579 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 580 hid0 |= HID0_NAP; 581 break; 582 } 583 #endif 584 585 switch (vers) { 586 case IBM750FX: 587 case IBM750GX: 588 case MPC750: 589 hid0 &= ~HID0_DBP; /* XXX correct? */ 590 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 591 break; 592 593 case MPC7400: 594 case MPC7410: 595 hid0 &= ~HID0_SPD; 596 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 597 hid0 |= HID0_EIEC; 598 break; 599 } 600 601 #ifdef MULTIPROCESSOR 602 switch (vers) { 603 case MPC603e: 604 hid0 |= HID0_ABE; 605 } 606 #endif 607 608 if (hid0 != hid0_save) { 609 mtspr(SPR_HID0, hid0); 610 __asm volatile("sync;isync"); 611 } 612 613 614 switch (vers) { 615 case MPC601: 616 bitmask = HID0_601_BITMASK; 617 break; 618 case MPC7450: 619 case MPC7455: 620 case MPC7457: 621 bitmask = HID0_7450_BITMASK; 622 break; 623 case IBM970: 624 case IBM970FX: 625 case IBM970MP: 626 bitmask = 0; 627 break; 628 default: 629 bitmask = HID0_BITMASK; 630 break; 631 } 632 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 633 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 634 635 ci->ci_khz = 0; 636 637 /* 638 * Display speed and cache configuration. 639 */ 640 switch (vers) { 641 case MPC604: 642 case MPC604e: 643 case MPC604ev: 644 case MPC750: 645 case IBM750FX: 646 case IBM750GX: 647 case MPC7400: 648 case MPC7410: 649 case MPC7447A: 650 case MPC7448: 651 case MPC7450: 652 case MPC7455: 653 case MPC7457: 654 aprint_normal_dev(self, ""); 655 cpu_probe_speed(ci); 656 aprint_normal("%u.%02u MHz", 657 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 658 switch (vers) { 659 case MPC7450: /* 7441 does not have L3! */ 660 case MPC7455: /* 7445 does not have L3! */ 661 case MPC7457: /* 7447 does not have L3! */ 662 cpu_config_l3cr(vers); 663 break; 664 case IBM750FX: 665 case IBM750GX: 666 case MPC750: 667 case MPC7400: 668 case MPC7410: 669 case MPC7447A: 670 case MPC7448: 671 cpu_config_l2cr(pvr); 672 break; 673 default: 674 break; 675 } 676 aprint_normal("\n"); 677 break; 678 } 679 680 #if NSYSMON_ENVSYS > 0 681 /* 682 * Attach MPC750 temperature sensor to the envsys subsystem. 683 * XXX the 74xx series also has this sensor, but it is not 684 * XXX supported by Motorola and may return values that are off by 685 * XXX 35-55 degrees C. 686 */ 687 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 688 cpu_tau_setup(ci); 689 #endif 690 691 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 692 NULL, xname, "clock"); 693 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 694 NULL, xname, "traps"); 695 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 696 &ci->ci_ev_traps, xname, "kernel DSI traps"); 697 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 698 &ci->ci_ev_traps, xname, "user DSI traps"); 699 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 700 &ci->ci_ev_udsi, xname, "user DSI failures"); 701 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 702 &ci->ci_ev_traps, xname, "kernel ISI traps"); 703 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 704 &ci->ci_ev_traps, xname, "user ISI traps"); 705 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 706 &ci->ci_ev_isi, xname, "user ISI failures"); 707 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 708 &ci->ci_ev_traps, xname, "system call traps"); 709 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 710 &ci->ci_ev_traps, xname, "PGM traps"); 711 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 712 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 713 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 714 &ci->ci_ev_fpu, xname, "FPU context switches"); 715 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 716 &ci->ci_ev_traps, xname, "user alignment traps"); 717 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 718 &ci->ci_ev_ali, xname, "user alignment traps"); 719 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 720 &ci->ci_ev_umchk, xname, "user MCHK failures"); 721 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 722 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 723 #ifdef ALTIVEC 724 if (cpu_altivec) { 725 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 726 &ci->ci_ev_vec, xname, "AltiVec context switches"); 727 } 728 #endif 729 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 730 NULL, xname, "IPIs"); 731 } 732 733 /* 734 * According to a document labeled "PVR Register Settings": 735 ** For integrated microprocessors the PVR register inside the device 736 ** will identify the version of the microprocessor core. You must also 737 ** read the Device ID, PCI register 02, to identify the part and the 738 ** Revision ID, PCI register 08, to identify the revision of the 739 ** integrated microprocessor. 740 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 741 */ 742 743 void 744 cpu_identify(char *str, size_t len) 745 { 746 u_int pvr, major, minor; 747 uint16_t vers, rev, revfmt; 748 const struct cputab *cp; 749 size_t n; 750 751 pvr = mfpvr(); 752 vers = pvr >> 16; 753 rev = pvr; 754 755 switch (vers) { 756 case MPC7410: 757 minor = (pvr >> 0) & 0xff; 758 major = minor <= 4 ? 1 : 2; 759 break; 760 case MPCG2: /*XXX see note above */ 761 major = (pvr >> 4) & 0xf; 762 minor = (pvr >> 0) & 0xf; 763 break; 764 default: 765 major = (pvr >> 8) & 0xf; 766 minor = (pvr >> 0) & 0xf; 767 } 768 769 for (cp = models; cp->name[0] != '\0'; cp++) { 770 if (cp->version == vers) 771 break; 772 } 773 774 if (cpu == -1) 775 cpu = vers; 776 777 revfmt = cp->revfmt; 778 if (rev == MPC750 && pvr == 15) { 779 revfmt = REVFMT_HEX; 780 } 781 782 if (cp->name[0] != '\0') { 783 n = snprintf(str, len, "%s (Revision ", cp->name); 784 } else { 785 n = snprintf(str, len, "Version %#x (Revision ", vers); 786 } 787 if (len > n) { 788 switch (revfmt) { 789 case REVFMT_MAJMIN: 790 snprintf(str + n, len - n, "%u.%u)", major, minor); 791 break; 792 case REVFMT_HEX: 793 snprintf(str + n, len - n, "0x%04x)", rev); 794 break; 795 case REVFMT_DEC: 796 snprintf(str + n, len - n, "%u)", rev); 797 break; 798 } 799 } 800 } 801 802 #ifdef L2CR_CONFIG 803 u_int l2cr_config = L2CR_CONFIG; 804 #else 805 u_int l2cr_config = 0; 806 #endif 807 808 #ifdef L3CR_CONFIG 809 u_int l3cr_config = L3CR_CONFIG; 810 #else 811 u_int l3cr_config = 0; 812 #endif 813 814 void 815 cpu_enable_l2cr(register_t l2cr) 816 { 817 register_t msr, x; 818 uint16_t vers; 819 820 vers = mfpvr() >> 16; 821 822 /* Disable interrupts and set the cache config bits. */ 823 msr = mfmsr(); 824 mtmsr(msr & ~PSL_EE); 825 #ifdef ALTIVEC 826 if (cpu_altivec) 827 __asm volatile("dssall"); 828 #endif 829 __asm volatile("sync"); 830 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 831 __asm volatile("sync"); 832 833 /* Wait for L2 clock to be stable (640 L2 clocks). */ 834 delay(100); 835 836 /* Invalidate all L2 contents. */ 837 if (MPC745X_P(vers)) { 838 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 839 do { 840 x = mfspr(SPR_L2CR); 841 } while (x & L2CR_L2I); 842 } else { 843 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 844 do { 845 x = mfspr(SPR_L2CR); 846 } while (x & L2CR_L2IP); 847 } 848 /* Enable L2 cache. */ 849 l2cr |= L2CR_L2E; 850 mtspr(SPR_L2CR, l2cr); 851 mtmsr(msr); 852 } 853 854 void 855 cpu_enable_l3cr(register_t l3cr) 856 { 857 register_t x; 858 859 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 860 861 /* 862 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 863 * L3CLKEN. (also mask off reserved bits in case they were included 864 * in L3CR_CONFIG) 865 */ 866 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 867 mtspr(SPR_L3CR, l3cr); 868 869 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 870 l3cr |= 0x04000000; 871 mtspr(SPR_L3CR, l3cr); 872 873 /* 3: Set L3CLKEN to 1*/ 874 l3cr |= L3CR_L3CLKEN; 875 mtspr(SPR_L3CR, l3cr); 876 877 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 878 __asm volatile("dssall;sync"); 879 /* L3 cache is already disabled, no need to clear L3E */ 880 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 881 do { 882 x = mfspr(SPR_L3CR); 883 } while (x & L3CR_L3I); 884 885 /* 6: Clear L3CLKEN to 0 */ 886 l3cr &= ~L3CR_L3CLKEN; 887 mtspr(SPR_L3CR, l3cr); 888 889 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 890 __asm volatile("sync"); 891 delay(100); 892 893 /* 8: Set L3E and L3CLKEN */ 894 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 895 mtspr(SPR_L3CR, l3cr); 896 897 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 898 __asm volatile("sync"); 899 delay(100); 900 } 901 902 void 903 cpu_config_l2cr(int pvr) 904 { 905 register_t l2cr; 906 u_int vers = (pvr >> 16) & 0xffff; 907 908 l2cr = mfspr(SPR_L2CR); 909 910 /* 911 * For MP systems, the firmware may only configure the L2 cache 912 * on the first CPU. In this case, assume that the other CPUs 913 * should use the same value for L2CR. 914 */ 915 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 916 l2cr_config = l2cr; 917 } 918 919 /* 920 * Configure L2 cache if not enabled. 921 */ 922 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 923 cpu_enable_l2cr(l2cr_config); 924 l2cr = mfspr(SPR_L2CR); 925 } 926 927 if ((l2cr & L2CR_L2E) == 0) { 928 aprint_normal(" L2 cache present but not enabled "); 929 return; 930 } 931 aprint_normal(","); 932 933 switch (vers) { 934 case IBM750FX: 935 case IBM750GX: 936 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 937 break; 938 case MPC750: 939 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 940 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 941 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 942 else 943 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 944 break; 945 case MPC7447A: 946 case MPC7457: 947 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 948 return; 949 case MPC7448: 950 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 951 return; 952 case MPC7450: 953 case MPC7455: 954 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 955 break; 956 default: 957 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 958 break; 959 } 960 } 961 962 void 963 cpu_config_l3cr(int vers) 964 { 965 register_t l2cr; 966 register_t l3cr; 967 968 l2cr = mfspr(SPR_L2CR); 969 970 /* 971 * For MP systems, the firmware may only configure the L2 cache 972 * on the first CPU. In this case, assume that the other CPUs 973 * should use the same value for L2CR. 974 */ 975 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 976 l2cr_config = l2cr; 977 } 978 979 /* 980 * Configure L2 cache if not enabled. 981 */ 982 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 983 cpu_enable_l2cr(l2cr_config); 984 l2cr = mfspr(SPR_L2CR); 985 } 986 987 aprint_normal(","); 988 switch (vers) { 989 case MPC7447A: 990 case MPC7457: 991 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 992 return; 993 case MPC7448: 994 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 995 return; 996 default: 997 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 998 break; 999 } 1000 1001 l3cr = mfspr(SPR_L3CR); 1002 1003 /* 1004 * For MP systems, the firmware may only configure the L3 cache 1005 * on the first CPU. In this case, assume that the other CPUs 1006 * should use the same value for L3CR. 1007 */ 1008 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1009 l3cr_config = l3cr; 1010 } 1011 1012 /* 1013 * Configure L3 cache if not enabled. 1014 */ 1015 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1016 cpu_enable_l3cr(l3cr_config); 1017 l3cr = mfspr(SPR_L3CR); 1018 } 1019 1020 if (l3cr & L3CR_L3E) { 1021 aprint_normal(","); 1022 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1023 } 1024 } 1025 1026 void 1027 cpu_probe_speed(struct cpu_info *ci) 1028 { 1029 uint64_t cps; 1030 1031 mtspr(SPR_MMCR0, MMCR0_FC); 1032 mtspr(SPR_PMC1, 0); 1033 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1034 delay(100000); 1035 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1036 1037 mtspr(SPR_MMCR0, MMCR0_FC); 1038 1039 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1040 } 1041 1042 /* 1043 * Read the Dynamic Frequency Switching state and return a divisor for 1044 * the maximum frequency. 1045 */ 1046 int 1047 cpu_get_dfs(void) 1048 { 1049 u_int pvr, vers; 1050 1051 pvr = mfpvr(); 1052 vers = pvr >> 16; 1053 1054 switch (vers) { 1055 case MPC7448: 1056 if (mfspr(SPR_HID1) & HID1_DFS4) 1057 return 4; 1058 case MPC7447A: 1059 if (mfspr(SPR_HID1) & HID1_DFS2) 1060 return 2; 1061 } 1062 return 1; 1063 } 1064 1065 /* 1066 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1067 */ 1068 void 1069 cpu_set_dfs(int div) 1070 { 1071 uint64_t where; 1072 u_int dfs_mask, pvr, vers; 1073 1074 pvr = mfpvr(); 1075 vers = pvr >> 16; 1076 dfs_mask = 0; 1077 1078 switch (vers) { 1079 case MPC7448: 1080 dfs_mask |= HID1_DFS4; 1081 case MPC7447A: 1082 dfs_mask |= HID1_DFS2; 1083 break; 1084 default: 1085 printf("cpu_set_dfs: DFS not supported\n"); 1086 return; 1087 1088 } 1089 1090 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1091 xc_wait(where); 1092 } 1093 1094 static void 1095 cpu_set_dfs_xcall(void *arg1, void *arg2) 1096 { 1097 u_int dfs_mask, hid1, old_hid1; 1098 int *divisor, s; 1099 1100 divisor = arg1; 1101 dfs_mask = *(u_int *)arg2; 1102 1103 s = splhigh(); 1104 hid1 = old_hid1 = mfspr(SPR_HID1); 1105 1106 switch (*divisor) { 1107 case 1: 1108 hid1 &= ~dfs_mask; 1109 break; 1110 case 2: 1111 hid1 &= ~(dfs_mask & HID1_DFS4); 1112 hid1 |= dfs_mask & HID1_DFS2; 1113 break; 1114 case 4: 1115 hid1 &= ~(dfs_mask & HID1_DFS2); 1116 hid1 |= dfs_mask & HID1_DFS4; 1117 break; 1118 } 1119 1120 if (hid1 != old_hid1) { 1121 __asm volatile("sync"); 1122 mtspr(SPR_HID1, hid1); 1123 __asm volatile("sync;isync"); 1124 } 1125 1126 splx(s); 1127 } 1128 1129 #if NSYSMON_ENVSYS > 0 1130 void 1131 cpu_tau_setup(struct cpu_info *ci) 1132 { 1133 struct sysmon_envsys *sme; 1134 int error, therm_delay; 1135 1136 mtspr(SPR_THRM1, SPR_THRM_VALID); 1137 mtspr(SPR_THRM2, 0); 1138 1139 /* 1140 * we need to figure out how much 20+us in units of CPU clock cycles 1141 * are 1142 */ 1143 1144 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1145 1146 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1147 1148 sme = sysmon_envsys_create(); 1149 1150 sensor.units = ENVSYS_STEMP; 1151 sensor.state = ENVSYS_SINVALID; 1152 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1153 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1154 sysmon_envsys_destroy(sme); 1155 return; 1156 } 1157 1158 sme->sme_name = device_xname(ci->ci_dev); 1159 sme->sme_cookie = ci; 1160 sme->sme_refresh = cpu_tau_refresh; 1161 1162 if ((error = sysmon_envsys_register(sme)) != 0) { 1163 aprint_error_dev(ci->ci_dev, 1164 " unable to register with sysmon (%d)\n", error); 1165 sysmon_envsys_destroy(sme); 1166 } 1167 } 1168 1169 1170 /* Find the temperature of the CPU. */ 1171 void 1172 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1173 { 1174 int i, threshold, count; 1175 1176 threshold = 64; /* Half of the 7-bit sensor range */ 1177 1178 /* Successive-approximation code adapted from Motorola 1179 * application note AN1800/D, "Programming the Thermal Assist 1180 * Unit in the MPC750 Microprocessor". 1181 */ 1182 for (i = 5; i >= 0 ; i--) { 1183 mtspr(SPR_THRM1, 1184 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1185 count = 0; 1186 while ((count < 100000) && 1187 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1188 count++; 1189 delay(1); 1190 } 1191 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1192 /* The interrupt bit was set, meaning the 1193 * temperature was above the threshold 1194 */ 1195 threshold += 1 << i; 1196 } else { 1197 /* Temperature was below the threshold */ 1198 threshold -= 1 << i; 1199 } 1200 } 1201 threshold += 2; 1202 1203 /* Convert the temperature in degrees C to microkelvin */ 1204 edata->value_cur = (threshold * 1000000) + 273150000; 1205 edata->state = ENVSYS_SVALID; 1206 } 1207 #endif /* NSYSMON_ENVSYS > 0 */ 1208 1209 #ifdef MULTIPROCESSOR 1210 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1211 1212 int 1213 cpu_spinup(device_t self, struct cpu_info *ci) 1214 { 1215 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1216 struct pglist mlist; 1217 int i, error; 1218 char *hp; 1219 1220 KASSERT(ci != curcpu()); 1221 1222 /* Now allocate a hatch stack */ 1223 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1224 &mlist, 1, 1); 1225 if (error) { 1226 aprint_error(": unable to allocate hatch stack\n"); 1227 return -1; 1228 } 1229 1230 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1231 memset(hp, 0, HATCH_STACK_SIZE); 1232 1233 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1234 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1235 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1236 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1237 1238 cpu_hatch_data = h; 1239 h->hatch_running = 0; 1240 h->hatch_self = self; 1241 h->hatch_ci = ci; 1242 h->hatch_pir = ci->ci_cpuid; 1243 1244 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1245 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1246 1247 /* copy special registers */ 1248 1249 h->hatch_hid0 = mfspr(SPR_HID0); 1250 1251 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1252 for (i = 0; i < 16; i++) { 1253 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1254 "r"(i << ADDR_SR_SHFT)); 1255 } 1256 if (oeacpufeat & OEACPU_64) 1257 h->hatch_asr = mfspr(SPR_ASR); 1258 else 1259 h->hatch_asr = 0; 1260 1261 /* copy the bat regs */ 1262 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1263 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1264 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1265 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1266 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1267 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1268 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1269 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1270 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1271 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1272 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1273 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1274 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1275 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1276 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1277 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1278 __asm volatile ("sync; isync"); 1279 1280 if (md_setup_trampoline(h, ci) == -1) 1281 return -1; 1282 md_presync_timebase(h); 1283 md_start_timebase(h); 1284 1285 /* wait for secondary printf */ 1286 1287 delay(200000); 1288 1289 #ifdef CACHE_PROTO_MEI 1290 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1291 __asm volatile ("sync; isync"); 1292 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1293 __asm volatile ("sync; isync"); 1294 #endif 1295 if (h->hatch_running < 1) { 1296 #ifdef CACHE_PROTO_MEI 1297 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1298 __asm volatile ("sync; isync"); 1299 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1300 __asm volatile ("sync; isync"); 1301 #endif 1302 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1303 ci->ci_cpuid, cpu_spinstart_ack); 1304 Debugger(); 1305 return -1; 1306 } 1307 1308 /* Register IPI Interrupt */ 1309 if (ipiops.ppc_establish_ipi) 1310 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1311 1312 return 0; 1313 } 1314 1315 static volatile int start_secondary_cpu; 1316 1317 register_t 1318 cpu_hatch(void) 1319 { 1320 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1321 struct cpu_info * const ci = h->hatch_ci; 1322 struct pcb *pcb; 1323 u_int msr; 1324 int i; 1325 1326 /* Initialize timebase. */ 1327 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1328 1329 /* 1330 * Set PIR (Processor Identification Register). i.e. whoami 1331 * Note that PIR is read-only on some CPU versions, so we write to it 1332 * only if it has a different value than we need. 1333 */ 1334 1335 msr = mfspr(SPR_PIR); 1336 if (msr != h->hatch_pir) 1337 mtspr(SPR_PIR, h->hatch_pir); 1338 1339 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1340 curlwp = ci->ci_curlwp; 1341 cpu_spinstart_ack = 0; 1342 1343 /* Initialize MMU. */ 1344 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1345 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1346 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1347 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1348 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1349 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1350 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1351 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1352 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1353 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1354 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1355 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1356 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1357 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1358 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1359 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1360 1361 mtspr(SPR_HID0, h->hatch_hid0); 1362 1363 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1364 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1365 1366 __asm volatile ("sync"); 1367 for (i = 0; i < 16; i++) 1368 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1369 __asm volatile ("sync; isync"); 1370 1371 if (oeacpufeat & OEACPU_64) 1372 mtspr(SPR_ASR, h->hatch_asr); 1373 1374 cpu_spinstart_ack = 1; 1375 __asm ("ptesync"); 1376 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1377 __asm volatile ("sync; isync"); 1378 1379 cpu_spinstart_ack = 5; 1380 for (i = 0; i < 16; i++) 1381 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1382 "r"(i << ADDR_SR_SHFT)); 1383 1384 /* Enable I/D address translations. */ 1385 msr = mfmsr(); 1386 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1387 mtmsr(msr); 1388 __asm volatile ("sync; isync"); 1389 cpu_spinstart_ack = 2; 1390 1391 md_sync_timebase(h); 1392 1393 cpu_setup(h->hatch_self, ci); 1394 1395 h->hatch_running = 1; 1396 __asm volatile ("sync; isync"); 1397 1398 while (start_secondary_cpu == 0) 1399 ; 1400 1401 __asm volatile ("sync; isync"); 1402 1403 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1404 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1405 1406 md_setup_interrupts(); 1407 1408 ci->ci_ipending = 0; 1409 ci->ci_cpl = 0; 1410 1411 mtmsr(mfmsr() | PSL_EE); 1412 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1413 return pcb->pcb_sp; 1414 } 1415 1416 void 1417 cpu_boot_secondary_processors(void) 1418 { 1419 start_secondary_cpu = 1; 1420 __asm volatile ("sync"); 1421 } 1422 1423 #endif /*MULTIPROCESSOR*/ 1424