1 /* $NetBSD: cpu_subr.c,v 1.73 2012/02/01 09:54:03 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.73 2012/02/01 09:54:03 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/xcall.h> 50 51 #include <uvm/uvm.h> 52 53 #include <powerpc/pcb.h> 54 #include <powerpc/psl.h> 55 #include <powerpc/spr.h> 56 #include <powerpc/oea/hid.h> 57 #include <powerpc/oea/hid_601.h> 58 #include <powerpc/oea/spr.h> 59 #include <powerpc/oea/cpufeat.h> 60 61 #include <dev/sysmon/sysmonvar.h> 62 63 static void cpu_enable_l2cr(register_t); 64 static void cpu_enable_l3cr(register_t); 65 static void cpu_config_l2cr(int); 66 static void cpu_config_l3cr(int); 67 static void cpu_probe_speed(struct cpu_info *); 68 static void cpu_idlespin(void); 69 static void cpu_set_dfs_xcall(void *, void *); 70 #if NSYSMON_ENVSYS > 0 71 static void cpu_tau_setup(struct cpu_info *); 72 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 73 #endif 74 75 int cpu; 76 int ncpus; 77 78 struct fmttab { 79 register_t fmt_mask; 80 register_t fmt_value; 81 const char *fmt_string; 82 }; 83 84 /* 85 * This should be one per CPU but since we only support it on 750 variants it 86 * doesn't realy matter since none of them supports SMP 87 */ 88 envsys_data_t sensor; 89 90 static const struct fmttab cpu_7450_l2cr_formats[] = { 91 { L2CR_L2E, 0, " disabled" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 95 { L2CR_L2E, ~0, " 256KB L2 cache" }, 96 { L2CR_L2PE, 0, " no parity" }, 97 { L2CR_L2PE, ~0, " parity enabled" }, 98 { 0, 0, NULL } 99 }; 100 101 static const struct fmttab cpu_7448_l2cr_formats[] = { 102 { L2CR_L2E, 0, " disabled" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 106 { L2CR_L2E, ~0, " 1MB L2 cache" }, 107 { L2CR_L2PE, 0, " no parity" }, 108 { L2CR_L2PE, ~0, " parity enabled" }, 109 { 0, 0, NULL } 110 }; 111 112 static const struct fmttab cpu_7457_l2cr_formats[] = { 113 { L2CR_L2E, 0, " disabled" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 117 { L2CR_L2E, ~0, " 512KB L2 cache" }, 118 { L2CR_L2PE, 0, " no parity" }, 119 { L2CR_L2PE, ~0, " parity enabled" }, 120 { 0, 0, NULL } 121 }; 122 123 static const struct fmttab cpu_7450_l3cr_formats[] = { 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 127 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 128 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 133 { L3CR_L3SIZ, ~0, " L3 cache" }, 134 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 135 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 136 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 137 { L3CR_L3CLK, ~0, " at" }, 138 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 139 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 140 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 141 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 142 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 143 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 144 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 145 { L3CR_L3CLK, ~0, " ratio" }, 146 { 0, 0, NULL }, 147 }; 148 149 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 150 { L2CR_L2E, 0, " disabled" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 154 { 0, ~0, " 512KB" }, 155 { L2CR_L2WT, L2CR_L2WT, " WT" }, 156 { L2CR_L2WT, 0, " WB" }, 157 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 158 { 0, ~0, " L2 cache" }, 159 { 0, 0, NULL } 160 }; 161 162 static const struct fmttab cpu_l2cr_formats[] = { 163 { L2CR_L2E, 0, " disabled" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 167 { L2CR_L2PE, L2CR_L2PE, " parity" }, 168 { L2CR_L2PE, 0, " no-parity" }, 169 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 170 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 171 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 172 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 173 { L2CR_L2WT, L2CR_L2WT, " WT" }, 174 { L2CR_L2WT, 0, " WB" }, 175 { L2CR_L2E, ~0, " L2 cache" }, 176 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 177 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 179 { L2CR_L2CLK, ~0, " at" }, 180 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 181 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 182 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 183 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 184 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 185 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 186 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 187 { L2CR_L2CLK, ~0, " ratio" }, 188 { 0, 0, NULL } 189 }; 190 191 static void cpu_fmttab_print(const struct fmttab *, register_t); 192 193 struct cputab { 194 const char name[8]; 195 uint16_t version; 196 uint16_t revfmt; 197 }; 198 #define REVFMT_MAJMIN 1 /* %u.%u */ 199 #define REVFMT_HEX 2 /* 0x%04x */ 200 #define REVFMT_DEC 3 /* %u */ 201 static const struct cputab models[] = { 202 { "601", MPC601, REVFMT_DEC }, 203 { "602", MPC602, REVFMT_DEC }, 204 { "603", MPC603, REVFMT_MAJMIN }, 205 { "603e", MPC603e, REVFMT_MAJMIN }, 206 { "603ev", MPC603ev, REVFMT_MAJMIN }, 207 { "G2", MPCG2, REVFMT_MAJMIN }, 208 { "604", MPC604, REVFMT_MAJMIN }, 209 { "604e", MPC604e, REVFMT_MAJMIN }, 210 { "604ev", MPC604ev, REVFMT_MAJMIN }, 211 { "620", MPC620, REVFMT_HEX }, 212 { "750", MPC750, REVFMT_MAJMIN }, 213 { "750FX", IBM750FX, REVFMT_MAJMIN }, 214 { "750GX", IBM750GX, REVFMT_MAJMIN }, 215 { "7400", MPC7400, REVFMT_MAJMIN }, 216 { "7410", MPC7410, REVFMT_MAJMIN }, 217 { "7450", MPC7450, REVFMT_MAJMIN }, 218 { "7455", MPC7455, REVFMT_MAJMIN }, 219 { "7457", MPC7457, REVFMT_MAJMIN }, 220 { "7447A", MPC7447A, REVFMT_MAJMIN }, 221 { "7448", MPC7448, REVFMT_MAJMIN }, 222 { "8240", MPC8240, REVFMT_MAJMIN }, 223 { "8245", MPC8245, REVFMT_MAJMIN }, 224 { "970", IBM970, REVFMT_MAJMIN }, 225 { "970FX", IBM970FX, REVFMT_MAJMIN }, 226 { "970MP", IBM970MP, REVFMT_MAJMIN }, 227 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 228 { "", 0, REVFMT_HEX } 229 }; 230 231 #ifdef MULTIPROCESSOR 232 struct cpu_info cpu_info[CPU_MAXNUM] = { 233 [0] = { 234 .ci_curlwp = &lwp0, 235 }, 236 }; 237 volatile struct cpu_hatch_data *cpu_hatch_data; 238 volatile int cpu_hatch_stack; 239 extern int ticks_per_intr; 240 #include <powerpc/oea/bat.h> 241 #include <powerpc/pic/picvar.h> 242 #include <powerpc/pic/ipivar.h> 243 extern struct bat battable[]; 244 #else 245 struct cpu_info cpu_info[1] = { 246 [0] = { 247 .ci_curlwp = &lwp0, 248 }, 249 }; 250 #endif /*MULTIPROCESSOR*/ 251 252 int cpu_altivec; 253 register_t cpu_psluserset; 254 register_t cpu_pslusermod; 255 register_t cpu_pslusermask = 0xffff; 256 char cpu_model[80]; 257 258 /* This is to be called from locore.S, and nowhere else. */ 259 260 void 261 cpu_model_init(void) 262 { 263 u_int pvr, vers; 264 265 pvr = mfpvr(); 266 vers = pvr >> 16; 267 268 oeacpufeat = 0; 269 270 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 271 vers == IBMCELL || vers == IBMPOWER6P5) { 272 oeacpufeat |= OEACPU_64; 273 oeacpufeat |= OEACPU_64_BRIDGE; 274 oeacpufeat |= OEACPU_NOBAT; 275 276 } else if (vers == MPC601) { 277 oeacpufeat |= OEACPU_601; 278 279 } else if (MPC745X_P(vers) && vers != MPC7450) { 280 oeacpufeat |= OEACPU_HIGHSPRG; 281 oeacpufeat |= OEACPU_XBSEN; 282 oeacpufeat |= OEACPU_HIGHBAT; 283 /* Enable more and larger BAT registers */ 284 register_t hid0 = mfspr(SPR_HID0); 285 hid0 |= HID0_XBSEN; 286 hid0 |= HID0_HIGH_BAT_EN; 287 mtspr(SPR_HID0, hid0); 288 289 } else if (vers == IBM750FX || vers == IBM750GX) { 290 oeacpufeat |= OEACPU_HIGHBAT; 291 } 292 } 293 294 void 295 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 296 { 297 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 298 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 299 (data & fmt->fmt_mask) == fmt->fmt_value) 300 aprint_normal("%s", fmt->fmt_string); 301 } 302 } 303 304 void 305 cpu_idlespin(void) 306 { 307 register_t msr; 308 309 if (powersave <= 0) 310 return; 311 312 __asm volatile( 313 "sync;" 314 "mfmsr %0;" 315 "oris %0,%0,%1@h;" /* enter power saving mode */ 316 "mtmsr %0;" 317 "isync;" 318 : "=r"(msr) 319 : "J"(PSL_POW)); 320 } 321 322 void 323 cpu_probe_cache(void) 324 { 325 u_int assoc, pvr, vers; 326 327 pvr = mfpvr(); 328 vers = pvr >> 16; 329 330 331 /* Presently common across almost all implementations. */ 332 curcpu()->ci_ci.dcache_line_size = 32; 333 curcpu()->ci_ci.icache_line_size = 32; 334 335 336 switch (vers) { 337 #define K *1024 338 case IBM750FX: 339 case IBM750GX: 340 case MPC601: 341 case MPC750: 342 case MPC7400: 343 case MPC7447A: 344 case MPC7448: 345 case MPC7450: 346 case MPC7455: 347 case MPC7457: 348 curcpu()->ci_ci.dcache_size = 32 K; 349 curcpu()->ci_ci.icache_size = 32 K; 350 assoc = 8; 351 break; 352 case MPC603: 353 curcpu()->ci_ci.dcache_size = 8 K; 354 curcpu()->ci_ci.icache_size = 8 K; 355 assoc = 2; 356 break; 357 case MPC603e: 358 case MPC603ev: 359 case MPC604: 360 case MPC8240: 361 case MPC8245: 362 case MPCG2: 363 curcpu()->ci_ci.dcache_size = 16 K; 364 curcpu()->ci_ci.icache_size = 16 K; 365 assoc = 4; 366 break; 367 case MPC604e: 368 case MPC604ev: 369 curcpu()->ci_ci.dcache_size = 32 K; 370 curcpu()->ci_ci.icache_size = 32 K; 371 assoc = 4; 372 break; 373 case IBMPOWER3II: 374 curcpu()->ci_ci.dcache_size = 64 K; 375 curcpu()->ci_ci.icache_size = 32 K; 376 curcpu()->ci_ci.dcache_line_size = 128; 377 curcpu()->ci_ci.icache_line_size = 128; 378 assoc = 128; /* not a typo */ 379 break; 380 case IBM970: 381 case IBM970FX: 382 case IBM970MP: 383 curcpu()->ci_ci.dcache_size = 32 K; 384 curcpu()->ci_ci.icache_size = 64 K; 385 curcpu()->ci_ci.dcache_line_size = 128; 386 curcpu()->ci_ci.icache_line_size = 128; 387 assoc = 2; 388 break; 389 390 default: 391 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 392 curcpu()->ci_ci.icache_size = PAGE_SIZE; 393 assoc = 1; 394 #undef K 395 } 396 397 /* 398 * Possibly recolor. 399 */ 400 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 401 } 402 403 struct cpu_info * 404 cpu_attach_common(device_t self, int id) 405 { 406 struct cpu_info *ci; 407 u_int pvr, vers; 408 409 ci = &cpu_info[id]; 410 #ifndef MULTIPROCESSOR 411 /* 412 * If this isn't the primary CPU, print an error message 413 * and just bail out. 414 */ 415 if (id != 0) { 416 aprint_naive("\n"); 417 aprint_normal(": ID %d\n", id); 418 aprint_normal_dev(self, 419 "processor off-line; " 420 "multiprocessor support not present in kernel\n"); 421 return (NULL); 422 } 423 #endif 424 425 ci->ci_cpuid = id; 426 ci->ci_idepth = -1; 427 ci->ci_dev = self; 428 ci->ci_idlespin = cpu_idlespin; 429 430 pvr = mfpvr(); 431 vers = (pvr >> 16) & 0xffff; 432 433 switch (id) { 434 case 0: 435 /* load my cpu_number to PIR */ 436 switch (vers) { 437 case MPC601: 438 case MPC604: 439 case MPC604e: 440 case MPC604ev: 441 case MPC7400: 442 case MPC7410: 443 case MPC7447A: 444 case MPC7448: 445 case MPC7450: 446 case MPC7455: 447 case MPC7457: 448 mtspr(SPR_PIR, id); 449 } 450 cpu_setup(self, ci); 451 break; 452 default: 453 aprint_naive("\n"); 454 if (id >= CPU_MAXNUM) { 455 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 456 panic("cpuattach"); 457 } 458 #ifndef MULTIPROCESSOR 459 aprint_normal(" not configured\n"); 460 return NULL; 461 #else 462 mi_cpu_attach(ci); 463 break; 464 #endif 465 } 466 return (ci); 467 } 468 469 void 470 cpu_setup(device_t self, struct cpu_info *ci) 471 { 472 u_int hid0, hid0_save, pvr, vers; 473 const char * const xname = device_xname(self); 474 const char *bitmask; 475 char hidbuf[128]; 476 char model[80]; 477 478 pvr = mfpvr(); 479 vers = (pvr >> 16) & 0xffff; 480 481 cpu_identify(model, sizeof(model)); 482 aprint_naive("\n"); 483 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 484 cpu_number() == 0 ? " (primary)" : ""); 485 486 /* set the cpu number */ 487 ci->ci_cpuid = cpu_number(); 488 hid0_save = hid0 = mfspr(SPR_HID0); 489 490 cpu_probe_cache(); 491 492 /* 493 * Configure power-saving mode. 494 */ 495 switch (vers) { 496 case MPC604: 497 case MPC604e: 498 case MPC604ev: 499 /* 500 * Do not have HID0 support settings, but can support 501 * MSR[POW] off 502 */ 503 powersave = 1; 504 break; 505 506 case MPC603: 507 case MPC603e: 508 case MPC603ev: 509 case MPC7400: 510 case MPC7410: 511 case MPC8240: 512 case MPC8245: 513 case MPCG2: 514 /* Select DOZE mode. */ 515 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 516 hid0 |= HID0_DOZE | HID0_DPM; 517 powersave = 1; 518 break; 519 520 case MPC750: 521 case IBM750FX: 522 case IBM750GX: 523 /* Select NAP mode. */ 524 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 525 hid0 |= HID0_NAP | HID0_DPM; 526 powersave = 1; 527 break; 528 529 case MPC7447A: 530 case MPC7448: 531 case MPC7457: 532 case MPC7455: 533 case MPC7450: 534 /* Enable the 7450 branch caches */ 535 hid0 |= HID0_SGE | HID0_BTIC; 536 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 537 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 538 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 539 hid0 &= ~HID0_BTIC; 540 /* Select NAP mode. */ 541 hid0 &= ~HID0_SLEEP; 542 hid0 |= HID0_NAP | HID0_DPM; 543 powersave = 1; 544 break; 545 546 case IBM970: 547 case IBM970FX: 548 case IBM970MP: 549 case IBMPOWER3II: 550 default: 551 /* No power-saving mode is available. */ ; 552 } 553 554 #ifdef NAPMODE 555 switch (vers) { 556 case IBM750FX: 557 case IBM750GX: 558 case MPC750: 559 case MPC7400: 560 /* Select NAP mode. */ 561 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 562 hid0 |= HID0_NAP; 563 break; 564 } 565 #endif 566 567 switch (vers) { 568 case IBM750FX: 569 case IBM750GX: 570 case MPC750: 571 hid0 &= ~HID0_DBP; /* XXX correct? */ 572 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 573 break; 574 575 case MPC7400: 576 case MPC7410: 577 hid0 &= ~HID0_SPD; 578 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 579 hid0 |= HID0_EIEC; 580 break; 581 } 582 583 if (hid0 != hid0_save) { 584 mtspr(SPR_HID0, hid0); 585 __asm volatile("sync;isync"); 586 } 587 588 589 switch (vers) { 590 case MPC601: 591 bitmask = HID0_601_BITMASK; 592 break; 593 case MPC7450: 594 case MPC7455: 595 case MPC7457: 596 bitmask = HID0_7450_BITMASK; 597 break; 598 case IBM970: 599 case IBM970FX: 600 case IBM970MP: 601 bitmask = 0; 602 break; 603 default: 604 bitmask = HID0_BITMASK; 605 break; 606 } 607 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 608 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 609 610 ci->ci_khz = 0; 611 612 /* 613 * Display speed and cache configuration. 614 */ 615 switch (vers) { 616 case MPC604: 617 case MPC604e: 618 case MPC604ev: 619 case MPC750: 620 case IBM750FX: 621 case IBM750GX: 622 case MPC7400: 623 case MPC7410: 624 case MPC7447A: 625 case MPC7448: 626 case MPC7450: 627 case MPC7455: 628 case MPC7457: 629 aprint_normal_dev(self, ""); 630 cpu_probe_speed(ci); 631 aprint_normal("%u.%02u MHz", 632 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 633 switch (vers) { 634 case MPC7450: /* 7441 does not have L3! */ 635 case MPC7455: /* 7445 does not have L3! */ 636 case MPC7457: /* 7447 does not have L3! */ 637 cpu_config_l3cr(vers); 638 break; 639 case IBM750FX: 640 case IBM750GX: 641 case MPC750: 642 case MPC7400: 643 case MPC7410: 644 case MPC7447A: 645 case MPC7448: 646 cpu_config_l2cr(pvr); 647 break; 648 default: 649 break; 650 } 651 aprint_normal("\n"); 652 break; 653 } 654 655 #if NSYSMON_ENVSYS > 0 656 /* 657 * Attach MPC750 temperature sensor to the envsys subsystem. 658 * XXX the 74xx series also has this sensor, but it is not 659 * XXX supported by Motorola and may return values that are off by 660 * XXX 35-55 degrees C. 661 */ 662 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 663 cpu_tau_setup(ci); 664 #endif 665 666 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 667 NULL, xname, "clock"); 668 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 669 NULL, xname, "traps"); 670 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 671 &ci->ci_ev_traps, xname, "kernel DSI traps"); 672 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 673 &ci->ci_ev_traps, xname, "user DSI traps"); 674 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 675 &ci->ci_ev_udsi, xname, "user DSI failures"); 676 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 677 &ci->ci_ev_traps, xname, "kernel ISI traps"); 678 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 679 &ci->ci_ev_traps, xname, "user ISI traps"); 680 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 681 &ci->ci_ev_isi, xname, "user ISI failures"); 682 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 683 &ci->ci_ev_traps, xname, "system call traps"); 684 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 685 &ci->ci_ev_traps, xname, "PGM traps"); 686 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 687 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 688 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 689 &ci->ci_ev_fpu, xname, "FPU context switches"); 690 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 691 &ci->ci_ev_traps, xname, "user alignment traps"); 692 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 693 &ci->ci_ev_ali, xname, "user alignment traps"); 694 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 695 &ci->ci_ev_umchk, xname, "user MCHK failures"); 696 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 697 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 698 #ifdef ALTIVEC 699 if (cpu_altivec) { 700 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 701 &ci->ci_ev_vec, xname, "AltiVec context switches"); 702 } 703 #endif 704 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 705 NULL, xname, "IPIs"); 706 } 707 708 /* 709 * According to a document labeled "PVR Register Settings": 710 ** For integrated microprocessors the PVR register inside the device 711 ** will identify the version of the microprocessor core. You must also 712 ** read the Device ID, PCI register 02, to identify the part and the 713 ** Revision ID, PCI register 08, to identify the revision of the 714 ** integrated microprocessor. 715 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 716 */ 717 718 void 719 cpu_identify(char *str, size_t len) 720 { 721 u_int pvr, major, minor; 722 uint16_t vers, rev, revfmt; 723 const struct cputab *cp; 724 const char *name; 725 size_t n; 726 727 pvr = mfpvr(); 728 vers = pvr >> 16; 729 rev = pvr; 730 731 switch (vers) { 732 case MPC7410: 733 minor = (pvr >> 0) & 0xff; 734 major = minor <= 4 ? 1 : 2; 735 break; 736 case MPCG2: /*XXX see note above */ 737 major = (pvr >> 4) & 0xf; 738 minor = (pvr >> 0) & 0xf; 739 break; 740 default: 741 major = (pvr >> 8) & 0xf; 742 minor = (pvr >> 0) & 0xf; 743 } 744 745 for (cp = models; cp->name[0] != '\0'; cp++) { 746 if (cp->version == vers) 747 break; 748 } 749 750 if (str == NULL) { 751 str = cpu_model; 752 len = sizeof(cpu_model); 753 cpu = vers; 754 } 755 756 revfmt = cp->revfmt; 757 name = cp->name; 758 if (rev == MPC750 && pvr == 15) { 759 name = "755"; 760 revfmt = REVFMT_HEX; 761 } 762 763 if (cp->name[0] != '\0') { 764 n = snprintf(str, len, "%s (Revision ", cp->name); 765 } else { 766 n = snprintf(str, len, "Version %#x (Revision ", vers); 767 } 768 if (len > n) { 769 switch (revfmt) { 770 case REVFMT_MAJMIN: 771 snprintf(str + n, len - n, "%u.%u)", major, minor); 772 break; 773 case REVFMT_HEX: 774 snprintf(str + n, len - n, "0x%04x)", rev); 775 break; 776 case REVFMT_DEC: 777 snprintf(str + n, len - n, "%u)", rev); 778 break; 779 } 780 } 781 } 782 783 #ifdef L2CR_CONFIG 784 u_int l2cr_config = L2CR_CONFIG; 785 #else 786 u_int l2cr_config = 0; 787 #endif 788 789 #ifdef L3CR_CONFIG 790 u_int l3cr_config = L3CR_CONFIG; 791 #else 792 u_int l3cr_config = 0; 793 #endif 794 795 void 796 cpu_enable_l2cr(register_t l2cr) 797 { 798 register_t msr, x; 799 uint16_t vers; 800 801 vers = mfpvr() >> 16; 802 803 /* Disable interrupts and set the cache config bits. */ 804 msr = mfmsr(); 805 mtmsr(msr & ~PSL_EE); 806 #ifdef ALTIVEC 807 if (cpu_altivec) 808 __asm volatile("dssall"); 809 #endif 810 __asm volatile("sync"); 811 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 812 __asm volatile("sync"); 813 814 /* Wait for L2 clock to be stable (640 L2 clocks). */ 815 delay(100); 816 817 /* Invalidate all L2 contents. */ 818 if (MPC745X_P(vers)) { 819 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 820 do { 821 x = mfspr(SPR_L2CR); 822 } while (x & L2CR_L2I); 823 } else { 824 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 825 do { 826 x = mfspr(SPR_L2CR); 827 } while (x & L2CR_L2IP); 828 } 829 /* Enable L2 cache. */ 830 l2cr |= L2CR_L2E; 831 mtspr(SPR_L2CR, l2cr); 832 mtmsr(msr); 833 } 834 835 void 836 cpu_enable_l3cr(register_t l3cr) 837 { 838 register_t x; 839 840 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 841 842 /* 843 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 844 * L3CLKEN. (also mask off reserved bits in case they were included 845 * in L3CR_CONFIG) 846 */ 847 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 848 mtspr(SPR_L3CR, l3cr); 849 850 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 851 l3cr |= 0x04000000; 852 mtspr(SPR_L3CR, l3cr); 853 854 /* 3: Set L3CLKEN to 1*/ 855 l3cr |= L3CR_L3CLKEN; 856 mtspr(SPR_L3CR, l3cr); 857 858 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 859 __asm volatile("dssall;sync"); 860 /* L3 cache is already disabled, no need to clear L3E */ 861 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 862 do { 863 x = mfspr(SPR_L3CR); 864 } while (x & L3CR_L3I); 865 866 /* 6: Clear L3CLKEN to 0 */ 867 l3cr &= ~L3CR_L3CLKEN; 868 mtspr(SPR_L3CR, l3cr); 869 870 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 871 __asm volatile("sync"); 872 delay(100); 873 874 /* 8: Set L3E and L3CLKEN */ 875 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 876 mtspr(SPR_L3CR, l3cr); 877 878 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 879 __asm volatile("sync"); 880 delay(100); 881 } 882 883 void 884 cpu_config_l2cr(int pvr) 885 { 886 register_t l2cr; 887 u_int vers = (pvr >> 16) & 0xffff; 888 889 l2cr = mfspr(SPR_L2CR); 890 891 /* 892 * For MP systems, the firmware may only configure the L2 cache 893 * on the first CPU. In this case, assume that the other CPUs 894 * should use the same value for L2CR. 895 */ 896 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 897 l2cr_config = l2cr; 898 } 899 900 /* 901 * Configure L2 cache if not enabled. 902 */ 903 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 904 cpu_enable_l2cr(l2cr_config); 905 l2cr = mfspr(SPR_L2CR); 906 } 907 908 if ((l2cr & L2CR_L2E) == 0) { 909 aprint_normal(" L2 cache present but not enabled "); 910 return; 911 } 912 aprint_normal(","); 913 914 switch (vers) { 915 case IBM750FX: 916 case IBM750GX: 917 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 918 break; 919 case MPC750: 920 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 921 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 922 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 923 else 924 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 925 break; 926 case MPC7447A: 927 case MPC7457: 928 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 929 return; 930 case MPC7448: 931 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 932 return; 933 case MPC7450: 934 case MPC7455: 935 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 936 break; 937 default: 938 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 939 break; 940 } 941 } 942 943 void 944 cpu_config_l3cr(int vers) 945 { 946 register_t l2cr; 947 register_t l3cr; 948 949 l2cr = mfspr(SPR_L2CR); 950 951 /* 952 * For MP systems, the firmware may only configure the L2 cache 953 * on the first CPU. In this case, assume that the other CPUs 954 * should use the same value for L2CR. 955 */ 956 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 957 l2cr_config = l2cr; 958 } 959 960 /* 961 * Configure L2 cache if not enabled. 962 */ 963 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 964 cpu_enable_l2cr(l2cr_config); 965 l2cr = mfspr(SPR_L2CR); 966 } 967 968 aprint_normal(","); 969 switch (vers) { 970 case MPC7447A: 971 case MPC7457: 972 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 973 return; 974 case MPC7448: 975 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 976 return; 977 default: 978 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 979 break; 980 } 981 982 l3cr = mfspr(SPR_L3CR); 983 984 /* 985 * For MP systems, the firmware may only configure the L3 cache 986 * on the first CPU. In this case, assume that the other CPUs 987 * should use the same value for L3CR. 988 */ 989 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 990 l3cr_config = l3cr; 991 } 992 993 /* 994 * Configure L3 cache if not enabled. 995 */ 996 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 997 cpu_enable_l3cr(l3cr_config); 998 l3cr = mfspr(SPR_L3CR); 999 } 1000 1001 if (l3cr & L3CR_L3E) { 1002 aprint_normal(","); 1003 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1004 } 1005 } 1006 1007 void 1008 cpu_probe_speed(struct cpu_info *ci) 1009 { 1010 uint64_t cps; 1011 1012 mtspr(SPR_MMCR0, MMCR0_FC); 1013 mtspr(SPR_PMC1, 0); 1014 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1015 delay(100000); 1016 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1017 1018 mtspr(SPR_MMCR0, MMCR0_FC); 1019 1020 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1021 } 1022 1023 /* 1024 * Read the Dynamic Frequency Switching state and return a divisor for 1025 * the maximum frequency. 1026 */ 1027 int 1028 cpu_get_dfs(void) 1029 { 1030 u_int pvr, vers; 1031 1032 pvr = mfpvr(); 1033 vers = pvr >> 16; 1034 1035 switch (vers) { 1036 case MPC7448: 1037 if (mfspr(SPR_HID1) & HID1_DFS4) 1038 return 4; 1039 case MPC7447A: 1040 if (mfspr(SPR_HID1) & HID1_DFS2) 1041 return 2; 1042 } 1043 return 1; 1044 } 1045 1046 /* 1047 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1048 */ 1049 void 1050 cpu_set_dfs(int div) 1051 { 1052 uint64_t where; 1053 u_int dfs_mask, pvr, vers; 1054 1055 pvr = mfpvr(); 1056 vers = pvr >> 16; 1057 dfs_mask = 0; 1058 1059 switch (vers) { 1060 case MPC7448: 1061 dfs_mask |= HID1_DFS4; 1062 case MPC7447A: 1063 dfs_mask |= HID1_DFS2; 1064 break; 1065 default: 1066 printf("cpu_set_dfs: DFS not supported\n"); 1067 return; 1068 1069 } 1070 1071 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1072 xc_wait(where); 1073 } 1074 1075 static void 1076 cpu_set_dfs_xcall(void *arg1, void *arg2) 1077 { 1078 u_int dfs_mask, hid1, old_hid1; 1079 int *divisor, s; 1080 1081 divisor = arg1; 1082 dfs_mask = *(u_int *)arg2; 1083 1084 s = splhigh(); 1085 hid1 = old_hid1 = mfspr(SPR_HID1); 1086 1087 switch (*divisor) { 1088 case 1: 1089 hid1 &= ~dfs_mask; 1090 break; 1091 case 2: 1092 hid1 &= ~(dfs_mask & HID1_DFS4); 1093 hid1 |= dfs_mask & HID1_DFS2; 1094 break; 1095 case 4: 1096 hid1 &= ~(dfs_mask & HID1_DFS2); 1097 hid1 |= dfs_mask & HID1_DFS4; 1098 break; 1099 } 1100 1101 if (hid1 != old_hid1) { 1102 __asm volatile("sync"); 1103 mtspr(SPR_HID1, hid1); 1104 __asm volatile("sync;isync"); 1105 } 1106 1107 splx(s); 1108 } 1109 1110 #if NSYSMON_ENVSYS > 0 1111 void 1112 cpu_tau_setup(struct cpu_info *ci) 1113 { 1114 struct sysmon_envsys *sme; 1115 int error, therm_delay; 1116 1117 mtspr(SPR_THRM1, SPR_THRM_VALID); 1118 mtspr(SPR_THRM2, 0); 1119 1120 /* 1121 * we need to figure out how much 20+us in units of CPU clock cycles 1122 * are 1123 */ 1124 1125 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1126 1127 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1128 1129 sme = sysmon_envsys_create(); 1130 1131 sensor.units = ENVSYS_STEMP; 1132 sensor.state = ENVSYS_SINVALID; 1133 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1134 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1135 sysmon_envsys_destroy(sme); 1136 return; 1137 } 1138 1139 sme->sme_name = device_xname(ci->ci_dev); 1140 sme->sme_cookie = ci; 1141 sme->sme_refresh = cpu_tau_refresh; 1142 1143 if ((error = sysmon_envsys_register(sme)) != 0) { 1144 aprint_error_dev(ci->ci_dev, 1145 " unable to register with sysmon (%d)\n", error); 1146 sysmon_envsys_destroy(sme); 1147 } 1148 } 1149 1150 1151 /* Find the temperature of the CPU. */ 1152 void 1153 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1154 { 1155 int i, threshold, count; 1156 1157 threshold = 64; /* Half of the 7-bit sensor range */ 1158 1159 /* Successive-approximation code adapted from Motorola 1160 * application note AN1800/D, "Programming the Thermal Assist 1161 * Unit in the MPC750 Microprocessor". 1162 */ 1163 for (i = 5; i >= 0 ; i--) { 1164 mtspr(SPR_THRM1, 1165 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1166 count = 0; 1167 while ((count < 100000) && 1168 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1169 count++; 1170 delay(1); 1171 } 1172 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1173 /* The interrupt bit was set, meaning the 1174 * temperature was above the threshold 1175 */ 1176 threshold += 1 << i; 1177 } else { 1178 /* Temperature was below the threshold */ 1179 threshold -= 1 << i; 1180 } 1181 1182 } 1183 threshold += 2; 1184 1185 /* Convert the temperature in degrees C to microkelvin */ 1186 edata->value_cur = (threshold * 1000000) + 273150000; 1187 edata->state = ENVSYS_SVALID; 1188 } 1189 #endif /* NSYSMON_ENVSYS > 0 */ 1190 1191 #ifdef MULTIPROCESSOR 1192 extern volatile u_int cpu_spinstart_ack; 1193 1194 int 1195 cpu_spinup(device_t self, struct cpu_info *ci) 1196 { 1197 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1198 struct pglist mlist; 1199 int i, error, pvr, vers; 1200 char *hp; 1201 1202 pvr = mfpvr(); 1203 vers = pvr >> 16; 1204 KASSERT(ci != curcpu()); 1205 1206 /* Now allocate a hatch stack */ 1207 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1208 &mlist, 1, 1); 1209 if (error) { 1210 aprint_error(": unable to allocate hatch stack\n"); 1211 return -1; 1212 } 1213 1214 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1215 memset(hp, 0, 0x1000); 1216 1217 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1218 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1219 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1220 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1221 1222 cpu_hatch_data = h; 1223 h->hatch_running = 0; 1224 h->hatch_self = self; 1225 h->hatch_ci = ci; 1226 h->hatch_pir = ci->ci_cpuid; 1227 1228 cpu_hatch_stack = (uint32_t)hp; 1229 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1230 1231 /* copy special registers */ 1232 1233 h->hatch_hid0 = mfspr(SPR_HID0); 1234 1235 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1236 for (i = 0; i < 16; i++) { 1237 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1238 "r"(i << ADDR_SR_SHFT)); 1239 } 1240 if (oeacpufeat & OEACPU_64) 1241 h->hatch_asr = mfspr(SPR_ASR); 1242 else 1243 h->hatch_asr = 0; 1244 1245 /* copy the bat regs */ 1246 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_batu[0])); 1247 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_batl[0])); 1248 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_batu[1])); 1249 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_batl[1])); 1250 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_batu[2])); 1251 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_batl[2])); 1252 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_batu[3])); 1253 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_batl[3])); 1254 __asm volatile ("sync; isync"); 1255 1256 if (md_setup_trampoline(h, ci) == -1) 1257 return -1; 1258 md_presync_timebase(h); 1259 md_start_timebase(h); 1260 1261 /* wait for secondary printf */ 1262 1263 delay(200000); 1264 1265 if (h->hatch_running < 1) { 1266 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1267 ci->ci_cpuid, cpu_spinstart_ack); 1268 Debugger(); 1269 return -1; 1270 } 1271 1272 /* Register IPI Interrupt */ 1273 if (ipiops.ppc_establish_ipi) 1274 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1275 1276 return 0; 1277 } 1278 1279 static volatile int start_secondary_cpu; 1280 extern void tlbia(void); 1281 1282 register_t 1283 cpu_hatch(void) 1284 { 1285 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1286 struct cpu_info * const ci = h->hatch_ci; 1287 struct pcb *pcb; 1288 u_int msr; 1289 int i; 1290 1291 /* Initialize timebase. */ 1292 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1293 1294 /* 1295 * Set PIR (Processor Identification Register). i.e. whoami 1296 * Note that PIR is read-only on some CPU versions, so we write to it 1297 * only if it has a different value than we need. 1298 */ 1299 1300 msr = mfspr(SPR_PIR); 1301 if (msr != h->hatch_pir) 1302 mtspr(SPR_PIR, h->hatch_pir); 1303 1304 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1305 curlwp = ci->ci_curlwp; 1306 cpu_spinstart_ack = 0; 1307 1308 /* Initialize MMU. */ 1309 __asm ("mtibatu 0,%0" :: "r"(h->hatch_batu[0])); 1310 __asm ("mtibatl 0,%0" :: "r"(h->hatch_batl[0])); 1311 __asm ("mtibatu 1,%0" :: "r"(h->hatch_batu[1])); 1312 __asm ("mtibatl 1,%0" :: "r"(h->hatch_batl[1])); 1313 __asm ("mtibatu 2,%0" :: "r"(h->hatch_batu[2])); 1314 __asm ("mtibatl 2,%0" :: "r"(h->hatch_batl[2])); 1315 __asm ("mtibatu 3,%0" :: "r"(h->hatch_batu[3])); 1316 __asm ("mtibatl 3,%0" :: "r"(h->hatch_batl[3])); 1317 1318 mtspr(SPR_HID0, h->hatch_hid0); 1319 1320 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1321 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1322 1323 __asm volatile ("sync"); 1324 for (i = 0; i < 16; i++) 1325 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1326 __asm volatile ("sync; isync"); 1327 1328 if (oeacpufeat & OEACPU_64) 1329 mtspr(SPR_ASR, h->hatch_asr); 1330 1331 cpu_spinstart_ack = 1; 1332 __asm ("ptesync"); 1333 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1334 __asm volatile ("sync; isync"); 1335 1336 cpu_spinstart_ack = 5; 1337 for (i = 0; i < 16; i++) 1338 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1339 "r"(i << ADDR_SR_SHFT)); 1340 1341 /* Enable I/D address translations. */ 1342 msr = mfmsr(); 1343 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1344 mtmsr(msr); 1345 __asm volatile ("sync; isync"); 1346 cpu_spinstart_ack = 2; 1347 1348 md_sync_timebase(h); 1349 1350 cpu_setup(h->hatch_self, ci); 1351 1352 h->hatch_running = 1; 1353 __asm volatile ("sync; isync"); 1354 1355 while (start_secondary_cpu == 0) 1356 ; 1357 1358 __asm volatile ("sync; isync"); 1359 1360 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1361 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1362 1363 md_setup_interrupts(); 1364 1365 ci->ci_ipending = 0; 1366 ci->ci_cpl = 0; 1367 1368 mtmsr(mfmsr() | PSL_EE); 1369 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1370 return pcb->pcb_sp; 1371 } 1372 1373 void 1374 cpu_boot_secondary_processors(void) 1375 { 1376 start_secondary_cpu = 1; 1377 __asm volatile ("sync"); 1378 } 1379 1380 #endif /*MULTIPROCESSOR*/ 1381