1 /* $NetBSD: cpu_subr.c,v 1.26 2005/12/24 20:07:28 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.26 2005/12/24 20:07:28 perry Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_probe_speed(struct cpu_info *); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0 } 87 }; 88 89 static const struct fmttab cpu_7448_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 1MB L2 cache" }, 95 { 0 } 96 }; 97 98 static const struct fmttab cpu_7457_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 512KB L2 cache" }, 104 { 0 } 105 }; 106 107 static const struct fmttab cpu_7450_l3cr_formats[] = { 108 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 109 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 110 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 111 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 112 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 113 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 114 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 115 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 116 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 117 { L3CR_L3SIZ, ~0, " L3 cache" }, 118 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 119 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 120 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 121 { L3CR_L3CLK, ~0, " at" }, 122 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 123 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 124 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 125 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 126 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 127 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 128 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 129 { L3CR_L3CLK, ~0, " ratio" }, 130 { 0, 0 }, 131 }; 132 133 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 134 { L2CR_L2E, 0, " disabled" }, 135 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 136 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 137 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 138 { 0, ~0, " 512KB" }, 139 { L2CR_L2WT, L2CR_L2WT, " WT" }, 140 { L2CR_L2WT, 0, " WB" }, 141 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 142 { 0, ~0, " L2 cache" }, 143 { 0 } 144 }; 145 146 static const struct fmttab cpu_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { L2CR_L2PE, L2CR_L2PE, " parity" }, 152 { L2CR_L2PE, 0, " no-parity" }, 153 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 154 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 155 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 156 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 157 { L2CR_L2WT, L2CR_L2WT, " WT" }, 158 { L2CR_L2WT, 0, " WB" }, 159 { L2CR_L2E, ~0, " L2 cache" }, 160 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 161 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 162 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 163 { L2CR_L2CLK, ~0, " at" }, 164 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 165 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 166 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 167 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 168 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 169 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 170 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 171 { L2CR_L2CLK, ~0, " ratio" }, 172 { 0 } 173 }; 174 175 static void cpu_fmttab_print(const struct fmttab *, register_t); 176 177 struct cputab { 178 const char name[8]; 179 uint16_t version; 180 uint16_t revfmt; 181 }; 182 #define REVFMT_MAJMIN 1 /* %u.%u */ 183 #define REVFMT_HEX 2 /* 0x%04x */ 184 #define REVFMT_DEC 3 /* %u */ 185 static const struct cputab models[] = { 186 { "601", MPC601, REVFMT_DEC }, 187 { "602", MPC602, REVFMT_DEC }, 188 { "603", MPC603, REVFMT_MAJMIN }, 189 { "603e", MPC603e, REVFMT_MAJMIN }, 190 { "603ev", MPC603ev, REVFMT_MAJMIN }, 191 { "604", MPC604, REVFMT_MAJMIN }, 192 { "604e", MPC604e, REVFMT_MAJMIN }, 193 { "604ev", MPC604ev, REVFMT_MAJMIN }, 194 { "620", MPC620, REVFMT_HEX }, 195 { "750", MPC750, REVFMT_MAJMIN }, 196 { "750FX", IBM750FX, REVFMT_MAJMIN }, 197 { "7400", MPC7400, REVFMT_MAJMIN }, 198 { "7410", MPC7410, REVFMT_MAJMIN }, 199 { "7450", MPC7450, REVFMT_MAJMIN }, 200 { "7455", MPC7455, REVFMT_MAJMIN }, 201 { "7457", MPC7457, REVFMT_MAJMIN }, 202 { "7447A", MPC7447A, REVFMT_MAJMIN }, 203 { "7448", MPC7448, REVFMT_MAJMIN }, 204 { "8240", MPC8240, REVFMT_MAJMIN }, 205 { "", 0, REVFMT_HEX } 206 }; 207 208 209 #ifdef MULTIPROCESSOR 210 struct cpu_info cpu_info[CPU_MAXNUM]; 211 #else 212 struct cpu_info cpu_info[1]; 213 #endif 214 215 int cpu_altivec; 216 int cpu_psluserset, cpu_pslusermod; 217 char cpu_model[80]; 218 219 void 220 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 221 { 222 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 223 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 224 (data & fmt->fmt_mask) == fmt->fmt_value) 225 aprint_normal("%s", fmt->fmt_string); 226 } 227 } 228 229 void 230 cpu_idlespin(void) 231 { 232 register_t msr; 233 234 if (powersave <= 0) 235 return; 236 237 __asm volatile( 238 "sync;" 239 "mfmsr %0;" 240 "oris %0,%0,%1@h;" /* enter power saving mode */ 241 "mtmsr %0;" 242 "isync;" 243 : "=r"(msr) 244 : "J"(PSL_POW)); 245 } 246 247 void 248 cpu_probe_cache(void) 249 { 250 u_int assoc, pvr, vers; 251 252 pvr = mfpvr(); 253 vers = pvr >> 16; 254 255 switch (vers) { 256 #define K *1024 257 case IBM750FX: 258 case MPC601: 259 case MPC750: 260 case MPC7447A: 261 case MPC7448: 262 case MPC7450: 263 case MPC7455: 264 case MPC7457: 265 curcpu()->ci_ci.dcache_size = 32 K; 266 curcpu()->ci_ci.icache_size = 32 K; 267 assoc = 8; 268 break; 269 case MPC603: 270 curcpu()->ci_ci.dcache_size = 8 K; 271 curcpu()->ci_ci.icache_size = 8 K; 272 assoc = 2; 273 break; 274 case MPC603e: 275 case MPC603ev: 276 case MPC604: 277 case MPC8240: 278 case MPC8245: 279 curcpu()->ci_ci.dcache_size = 16 K; 280 curcpu()->ci_ci.icache_size = 16 K; 281 assoc = 4; 282 break; 283 case MPC604e: 284 case MPC604ev: 285 curcpu()->ci_ci.dcache_size = 32 K; 286 curcpu()->ci_ci.icache_size = 32 K; 287 assoc = 4; 288 break; 289 default: 290 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 291 curcpu()->ci_ci.icache_size = PAGE_SIZE; 292 assoc = 1; 293 #undef K 294 } 295 296 /* Presently common across all implementations. */ 297 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 298 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 299 300 /* 301 * Possibly recolor. 302 */ 303 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 304 } 305 306 struct cpu_info * 307 cpu_attach_common(struct device *self, int id) 308 { 309 struct cpu_info *ci; 310 u_int pvr, vers; 311 312 ncpus++; 313 ci = &cpu_info[id]; 314 #ifndef MULTIPROCESSOR 315 /* 316 * If this isn't the primary CPU, print an error message 317 * and just bail out. 318 */ 319 if (id != 0) { 320 aprint_normal(": ID %d\n", id); 321 aprint_normal("%s: processor off-line; multiprocessor support " 322 "not present in kernel\n", self->dv_xname); 323 return (NULL); 324 } 325 #endif 326 327 ci->ci_cpuid = id; 328 ci->ci_intrdepth = -1; 329 ci->ci_dev = self; 330 ci->ci_idlespin = cpu_idlespin; 331 332 pvr = mfpvr(); 333 vers = (pvr >> 16) & 0xffff; 334 335 switch (id) { 336 case 0: 337 /* load my cpu_number to PIR */ 338 switch (vers) { 339 case MPC601: 340 case MPC604: 341 case MPC604e: 342 case MPC604ev: 343 case MPC7400: 344 case MPC7410: 345 case MPC7447A: 346 case MPC7448: 347 case MPC7450: 348 case MPC7455: 349 case MPC7457: 350 mtspr(SPR_PIR, id); 351 } 352 cpu_setup(self, ci); 353 break; 354 default: 355 if (id >= CPU_MAXNUM) { 356 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 357 panic("cpuattach"); 358 } 359 #ifndef MULTIPROCESSOR 360 aprint_normal(" not configured\n"); 361 return NULL; 362 #endif 363 } 364 return (ci); 365 } 366 367 void 368 cpu_setup(self, ci) 369 struct device *self; 370 struct cpu_info *ci; 371 { 372 u_int hid0, pvr, vers; 373 const char *bitmask; 374 char hidbuf[128]; 375 char model[80]; 376 377 pvr = mfpvr(); 378 vers = (pvr >> 16) & 0xffff; 379 380 cpu_identify(model, sizeof(model)); 381 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 382 cpu_number() == 0 ? " (primary)" : ""); 383 384 hid0 = mfspr(SPR_HID0); 385 cpu_probe_cache(); 386 387 /* 388 * Configure power-saving mode. 389 */ 390 switch (vers) { 391 case MPC604: 392 case MPC604e: 393 case MPC604ev: 394 /* 395 * Do not have HID0 support settings, but can support 396 * MSR[POW] off 397 */ 398 powersave = 1; 399 break; 400 401 case MPC603: 402 case MPC603e: 403 case MPC603ev: 404 case MPC750: 405 case IBM750FX: 406 case MPC7400: 407 case MPC7410: 408 case MPC8240: 409 case MPC8245: 410 /* Select DOZE mode. */ 411 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 412 hid0 |= HID0_DOZE | HID0_DPM; 413 powersave = 1; 414 break; 415 416 case MPC7447A: 417 case MPC7448: 418 case MPC7457: 419 case MPC7455: 420 case MPC7450: 421 /* Enable the 7450 branch caches */ 422 hid0 |= HID0_SGE | HID0_BTIC; 423 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 424 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 425 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 426 hid0 &= ~HID0_BTIC; 427 /* Select NAP mode. */ 428 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 429 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 430 powersave = 1; 431 break; 432 433 default: 434 /* No power-saving mode is available. */ ; 435 } 436 437 #ifdef NAPMODE 438 switch (vers) { 439 case IBM750FX: 440 case MPC750: 441 case MPC7400: 442 /* Select NAP mode. */ 443 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 444 hid0 |= HID0_NAP; 445 break; 446 } 447 #endif 448 449 switch (vers) { 450 case IBM750FX: 451 case MPC750: 452 hid0 &= ~HID0_DBP; /* XXX correct? */ 453 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 454 break; 455 456 case MPC7400: 457 case MPC7410: 458 hid0 &= ~HID0_SPD; 459 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 460 hid0 |= HID0_EIEC; 461 break; 462 } 463 464 mtspr(SPR_HID0, hid0); 465 __asm volatile("sync;isync"); 466 467 switch (vers) { 468 case MPC601: 469 bitmask = HID0_601_BITMASK; 470 break; 471 case MPC7450: 472 case MPC7455: 473 case MPC7457: 474 bitmask = HID0_7450_BITMASK; 475 break; 476 default: 477 bitmask = HID0_BITMASK; 478 break; 479 } 480 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 481 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 482 483 ci->ci_khz = 0; 484 485 /* 486 * Display speed and cache configuration. 487 */ 488 switch (vers) { 489 case MPC604: 490 case MPC604e: 491 case MPC604ev: 492 case MPC750: 493 case IBM750FX: 494 case MPC7400: 495 case MPC7410: 496 case MPC7447A: 497 case MPC7448: 498 case MPC7450: 499 case MPC7455: 500 case MPC7457: 501 aprint_normal("%s: ", self->dv_xname); 502 cpu_probe_speed(ci); 503 aprint_normal("%u.%02u MHz", 504 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 505 506 if (vers == IBM750FX || vers == MPC750 || 507 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 508 if (MPC745X_P(vers)) { 509 cpu_config_l3cr(vers); 510 } else { 511 cpu_config_l2cr(pvr); 512 } 513 } 514 aprint_normal("\n"); 515 break; 516 } 517 518 #if NSYSMON_ENVSYS > 0 519 /* 520 * Attach MPC750 temperature sensor to the envsys subsystem. 521 * XXX the 74xx series also has this sensor, but it is not 522 * XXX supported by Motorola and may return values that are off by 523 * XXX 35-55 degrees C. 524 */ 525 if (vers == MPC750 || vers == IBM750FX) 526 cpu_tau_setup(ci); 527 #endif 528 529 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 530 NULL, self->dv_xname, "clock"); 531 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 532 NULL, self->dv_xname, "soft clock"); 533 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 534 NULL, self->dv_xname, "soft net"); 535 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 536 NULL, self->dv_xname, "soft serial"); 537 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 538 NULL, self->dv_xname, "traps"); 539 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 540 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 541 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 542 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 543 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 544 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 545 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 546 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 547 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 548 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 549 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 550 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 551 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 552 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 553 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 554 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 555 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 556 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 557 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 558 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 559 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 560 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 561 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 562 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 563 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 564 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 565 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 566 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 567 #ifdef ALTIVEC 568 if (cpu_altivec) { 569 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 570 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 571 } 572 #endif 573 } 574 575 void 576 cpu_identify(char *str, size_t len) 577 { 578 u_int pvr, major, minor; 579 uint16_t vers, rev, revfmt; 580 const struct cputab *cp; 581 const char *name; 582 size_t n; 583 584 pvr = mfpvr(); 585 vers = pvr >> 16; 586 rev = pvr; 587 switch (vers) { 588 case MPC7410: 589 minor = (pvr >> 0) & 0xff; 590 major = minor <= 4 ? 1 : 2; 591 break; 592 default: 593 major = (pvr >> 8) & 0xf; 594 minor = (pvr >> 0) & 0xf; 595 } 596 597 for (cp = models; cp->name[0] != '\0'; cp++) { 598 if (cp->version == vers) 599 break; 600 } 601 602 if (str == NULL) { 603 str = cpu_model; 604 len = sizeof(cpu_model); 605 cpu = vers; 606 } 607 608 revfmt = cp->revfmt; 609 name = cp->name; 610 if (rev == MPC750 && pvr == 15) { 611 name = "755"; 612 revfmt = REVFMT_HEX; 613 } 614 615 if (cp->name[0] != '\0') { 616 n = snprintf(str, len, "%s (Revision ", cp->name); 617 } else { 618 n = snprintf(str, len, "Version %#x (Revision ", vers); 619 } 620 if (len > n) { 621 switch (revfmt) { 622 case REVFMT_MAJMIN: 623 snprintf(str + n, len - n, "%u.%u)", major, minor); 624 break; 625 case REVFMT_HEX: 626 snprintf(str + n, len - n, "0x%04x)", rev); 627 break; 628 case REVFMT_DEC: 629 snprintf(str + n, len - n, "%u)", rev); 630 break; 631 } 632 } 633 } 634 635 #ifdef L2CR_CONFIG 636 u_int l2cr_config = L2CR_CONFIG; 637 #else 638 u_int l2cr_config = 0; 639 #endif 640 641 #ifdef L3CR_CONFIG 642 u_int l3cr_config = L3CR_CONFIG; 643 #else 644 u_int l3cr_config = 0; 645 #endif 646 647 void 648 cpu_enable_l2cr(register_t l2cr) 649 { 650 register_t msr, x; 651 652 /* Disable interrupts and set the cache config bits. */ 653 msr = mfmsr(); 654 mtmsr(msr & ~PSL_EE); 655 #ifdef ALTIVEC 656 if (cpu_altivec) 657 __asm volatile("dssall"); 658 #endif 659 __asm volatile("sync"); 660 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 661 __asm volatile("sync"); 662 663 /* Wait for L2 clock to be stable (640 L2 clocks). */ 664 delay(100); 665 666 /* Invalidate all L2 contents. */ 667 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 668 do { 669 x = mfspr(SPR_L2CR); 670 } while (x & L2CR_L2IP); 671 672 /* Enable L2 cache. */ 673 l2cr |= L2CR_L2E; 674 mtspr(SPR_L2CR, l2cr); 675 mtmsr(msr); 676 } 677 678 void 679 cpu_enable_l3cr(register_t l3cr) 680 { 681 register_t x; 682 683 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 684 685 /* 686 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 687 * L3CLKEN. (also mask off reserved bits in case they were included 688 * in L3CR_CONFIG) 689 */ 690 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 691 mtspr(SPR_L3CR, l3cr); 692 693 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 694 l3cr |= 0x04000000; 695 mtspr(SPR_L3CR, l3cr); 696 697 /* 3: Set L3CLKEN to 1*/ 698 l3cr |= L3CR_L3CLKEN; 699 mtspr(SPR_L3CR, l3cr); 700 701 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 702 __asm volatile("dssall;sync"); 703 /* L3 cache is already disabled, no need to clear L3E */ 704 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 705 do { 706 x = mfspr(SPR_L3CR); 707 } while (x & L3CR_L3I); 708 709 /* 6: Clear L3CLKEN to 0 */ 710 l3cr &= ~L3CR_L3CLKEN; 711 mtspr(SPR_L3CR, l3cr); 712 713 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 714 __asm volatile("sync"); 715 delay(100); 716 717 /* 8: Set L3E and L3CLKEN */ 718 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 719 mtspr(SPR_L3CR, l3cr); 720 721 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 722 __asm volatile("sync"); 723 delay(100); 724 } 725 726 void 727 cpu_config_l2cr(int pvr) 728 { 729 register_t l2cr; 730 731 l2cr = mfspr(SPR_L2CR); 732 733 /* 734 * For MP systems, the firmware may only configure the L2 cache 735 * on the first CPU. In this case, assume that the other CPUs 736 * should use the same value for L2CR. 737 */ 738 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 739 l2cr_config = l2cr; 740 } 741 742 /* 743 * Configure L2 cache if not enabled. 744 */ 745 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 746 cpu_enable_l2cr(l2cr_config); 747 l2cr = mfspr(SPR_L2CR); 748 } 749 750 if ((l2cr & L2CR_L2E) == 0) { 751 aprint_normal(" L2 cache present but not enabled "); 752 return; 753 } 754 755 aprint_normal(","); 756 if ((pvr >> 16) == IBM750FX || 757 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 758 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 759 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 760 } else { 761 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 762 } 763 } 764 765 void 766 cpu_config_l3cr(int vers) 767 { 768 register_t l2cr; 769 register_t l3cr; 770 771 l2cr = mfspr(SPR_L2CR); 772 773 /* 774 * For MP systems, the firmware may only configure the L2 cache 775 * on the first CPU. In this case, assume that the other CPUs 776 * should use the same value for L2CR. 777 */ 778 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 779 l2cr_config = l2cr; 780 } 781 782 /* 783 * Configure L2 cache if not enabled. 784 */ 785 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 786 cpu_enable_l2cr(l2cr_config); 787 l2cr = mfspr(SPR_L2CR); 788 } 789 790 aprint_normal(","); 791 switch (vers) { 792 case MPC7447A: 793 case MPC7457: 794 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 795 return; 796 case MPC7448: 797 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 798 return; 799 default: 800 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 801 break; 802 } 803 804 l3cr = mfspr(SPR_L3CR); 805 806 /* 807 * For MP systems, the firmware may only configure the L3 cache 808 * on the first CPU. In this case, assume that the other CPUs 809 * should use the same value for L3CR. 810 */ 811 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 812 l3cr_config = l3cr; 813 } 814 815 /* 816 * Configure L3 cache if not enabled. 817 */ 818 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 819 cpu_enable_l3cr(l3cr_config); 820 l3cr = mfspr(SPR_L3CR); 821 } 822 823 if (l3cr & L3CR_L3E) { 824 aprint_normal(","); 825 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 826 } 827 } 828 829 void 830 cpu_probe_speed(struct cpu_info *ci) 831 { 832 uint64_t cps; 833 834 mtspr(SPR_MMCR0, MMCR0_FC); 835 mtspr(SPR_PMC1, 0); 836 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 837 delay(100000); 838 cps = (mfspr(SPR_PMC1) * 10) + 4999; 839 840 mtspr(SPR_MMCR0, MMCR0_FC); 841 842 ci->ci_khz = cps / 1000; 843 } 844 845 #if NSYSMON_ENVSYS > 0 846 const struct envsys_range cpu_tau_ranges[] = { 847 { 0, 0, ENVSYS_STEMP} 848 }; 849 850 struct envsys_basic_info cpu_tau_info[] = { 851 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 852 }; 853 854 void 855 cpu_tau_setup(struct cpu_info *ci) 856 { 857 struct { 858 struct sysmon_envsys sme; 859 struct envsys_tre_data tau_info; 860 } *datap; 861 int error; 862 863 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 864 865 ci->ci_sysmon_cookie = &datap->sme; 866 datap->sme.sme_nsensors = 1; 867 datap->sme.sme_envsys_version = 1000; 868 datap->sme.sme_ranges = cpu_tau_ranges; 869 datap->sme.sme_sensor_info = cpu_tau_info; 870 datap->sme.sme_sensor_data = &datap->tau_info; 871 872 datap->sme.sme_sensor_data->sensor = 0; 873 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 874 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 875 datap->sme.sme_cookie = ci; 876 datap->sme.sme_gtredata = cpu_tau_gtredata; 877 datap->sme.sme_streinfo = cpu_tau_streinfo; 878 datap->sme.sme_flags = 0; 879 880 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 881 aprint_error("%s: unable to register with sysmon (%d)\n", 882 ci->ci_dev->dv_xname, error); 883 } 884 885 886 /* Find the temperature of the CPU. */ 887 int 888 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 889 { 890 int i, threshold, count; 891 892 if (tred->sensor != 0) { 893 tred->validflags = 0; 894 return 0; 895 } 896 897 threshold = 64; /* Half of the 7-bit sensor range */ 898 mtspr(SPR_THRM1, 0); 899 mtspr(SPR_THRM2, 0); 900 /* XXX This counter is supposed to be "at least 20 microseonds, in 901 * XXX units of clock cycles". Since we don't have convenient 902 * XXX access to the CPU speed, set it to a conservative value, 903 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 904 * XXX the fastest G3 processor is 700MHz) . The cost is that 905 * XXX measuring the temperature takes a bit longer. 906 */ 907 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 908 909 /* Successive-approximation code adapted from Motorola 910 * application note AN1800/D, "Programming the Thermal Assist 911 * Unit in the MPC750 Microprocessor". 912 */ 913 for (i = 4; i >= 0 ; i--) { 914 mtspr(SPR_THRM1, 915 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 916 count = 0; 917 while ((count < 100) && 918 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 919 count++; 920 delay(1); 921 } 922 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 923 /* The interrupt bit was set, meaning the 924 * temperature was above the threshold 925 */ 926 threshold += 2 << i; 927 } else { 928 /* Temperature was below the threshold */ 929 threshold -= 2 << i; 930 } 931 } 932 threshold += 2; 933 934 /* Convert the temperature in degrees C to microkelvin */ 935 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 936 937 *tred = *sme->sme_sensor_data; 938 939 return 0; 940 } 941 942 int 943 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 944 { 945 946 /* There is nothing to set here. */ 947 return (EINVAL); 948 } 949 #endif /* NSYSMON_ENVSYS > 0 */ 950