1 /* $NetBSD: cpu_subr.c,v 1.76 2012/10/20 14:42:15 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.76 2012/10/20 14:42:15 kiyohara Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't realy matter since none of them supports SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 #define HATCH_STACK_SIZE 0x1000 241 extern int ticks_per_intr; 242 #include <powerpc/oea/bat.h> 243 #include <powerpc/pic/picvar.h> 244 #include <powerpc/pic/ipivar.h> 245 extern struct bat battable[]; 246 #else 247 struct cpu_info cpu_info[1] = { 248 [0] = { 249 .ci_curlwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 register_t cpu_psluserset; 256 register_t cpu_pslusermod; 257 register_t cpu_pslusermask = 0xffff; 258 char cpu_model[80]; 259 260 /* This is to be called from locore.S, and nowhere else. */ 261 262 void 263 cpu_model_init(void) 264 { 265 u_int pvr, vers; 266 267 pvr = mfpvr(); 268 vers = pvr >> 16; 269 270 oeacpufeat = 0; 271 272 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 273 vers == IBMCELL || vers == IBMPOWER6P5) { 274 oeacpufeat |= OEACPU_64; 275 oeacpufeat |= OEACPU_64_BRIDGE; 276 oeacpufeat |= OEACPU_NOBAT; 277 278 } else if (vers == MPC601) { 279 oeacpufeat |= OEACPU_601; 280 281 } else if (MPC745X_P(vers) && vers != MPC7450) { 282 oeacpufeat |= OEACPU_HIGHSPRG; 283 oeacpufeat |= OEACPU_XBSEN; 284 oeacpufeat |= OEACPU_HIGHBAT; 285 /* Enable more and larger BAT registers */ 286 register_t hid0 = mfspr(SPR_HID0); 287 hid0 |= HID0_XBSEN; 288 hid0 |= HID0_HIGH_BAT_EN; 289 mtspr(SPR_HID0, hid0); 290 291 } else if (vers == IBM750FX || vers == IBM750GX) { 292 oeacpufeat |= OEACPU_HIGHBAT; 293 } 294 } 295 296 void 297 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 298 { 299 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 300 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 301 (data & fmt->fmt_mask) == fmt->fmt_value) 302 aprint_normal("%s", fmt->fmt_string); 303 } 304 } 305 306 void 307 cpu_idlespin(void) 308 { 309 register_t msr; 310 311 if (powersave <= 0) 312 return; 313 314 __asm volatile( 315 "sync;" 316 "mfmsr %0;" 317 "oris %0,%0,%1@h;" /* enter power saving mode */ 318 "mtmsr %0;" 319 "isync;" 320 : "=r"(msr) 321 : "J"(PSL_POW)); 322 } 323 324 void 325 cpu_probe_cache(void) 326 { 327 u_int assoc, pvr, vers; 328 329 pvr = mfpvr(); 330 vers = pvr >> 16; 331 332 333 /* Presently common across almost all implementations. */ 334 curcpu()->ci_ci.dcache_line_size = 32; 335 curcpu()->ci_ci.icache_line_size = 32; 336 337 338 switch (vers) { 339 #define K *1024 340 case IBM750FX: 341 case IBM750GX: 342 case MPC601: 343 case MPC750: 344 case MPC7400: 345 case MPC7447A: 346 case MPC7448: 347 case MPC7450: 348 case MPC7455: 349 case MPC7457: 350 curcpu()->ci_ci.dcache_size = 32 K; 351 curcpu()->ci_ci.icache_size = 32 K; 352 assoc = 8; 353 break; 354 case MPC603: 355 curcpu()->ci_ci.dcache_size = 8 K; 356 curcpu()->ci_ci.icache_size = 8 K; 357 assoc = 2; 358 break; 359 case MPC603e: 360 case MPC603ev: 361 case MPC604: 362 case MPC8240: 363 case MPC8245: 364 case MPCG2: 365 curcpu()->ci_ci.dcache_size = 16 K; 366 curcpu()->ci_ci.icache_size = 16 K; 367 assoc = 4; 368 break; 369 case MPC604e: 370 case MPC604ev: 371 curcpu()->ci_ci.dcache_size = 32 K; 372 curcpu()->ci_ci.icache_size = 32 K; 373 assoc = 4; 374 break; 375 case IBMPOWER3II: 376 curcpu()->ci_ci.dcache_size = 64 K; 377 curcpu()->ci_ci.icache_size = 32 K; 378 curcpu()->ci_ci.dcache_line_size = 128; 379 curcpu()->ci_ci.icache_line_size = 128; 380 assoc = 128; /* not a typo */ 381 break; 382 case IBM970: 383 case IBM970FX: 384 case IBM970MP: 385 curcpu()->ci_ci.dcache_size = 32 K; 386 curcpu()->ci_ci.icache_size = 64 K; 387 curcpu()->ci_ci.dcache_line_size = 128; 388 curcpu()->ci_ci.icache_line_size = 128; 389 assoc = 2; 390 break; 391 392 default: 393 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 394 curcpu()->ci_ci.icache_size = PAGE_SIZE; 395 assoc = 1; 396 #undef K 397 } 398 399 /* 400 * Possibly recolor. 401 */ 402 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 403 } 404 405 struct cpu_info * 406 cpu_attach_common(device_t self, int id) 407 { 408 struct cpu_info *ci; 409 u_int pvr, vers; 410 411 ci = &cpu_info[id]; 412 #ifndef MULTIPROCESSOR 413 /* 414 * If this isn't the primary CPU, print an error message 415 * and just bail out. 416 */ 417 if (id != 0) { 418 aprint_naive("\n"); 419 aprint_normal(": ID %d\n", id); 420 aprint_normal_dev(self, 421 "processor off-line; " 422 "multiprocessor support not present in kernel\n"); 423 return (NULL); 424 } 425 #endif 426 427 ci->ci_cpuid = id; 428 ci->ci_idepth = -1; 429 ci->ci_dev = self; 430 ci->ci_idlespin = cpu_idlespin; 431 432 pvr = mfpvr(); 433 vers = (pvr >> 16) & 0xffff; 434 435 switch (id) { 436 case 0: 437 /* load my cpu_number to PIR */ 438 switch (vers) { 439 case MPC601: 440 case MPC604: 441 case MPC604e: 442 case MPC604ev: 443 case MPC7400: 444 case MPC7410: 445 case MPC7447A: 446 case MPC7448: 447 case MPC7450: 448 case MPC7455: 449 case MPC7457: 450 mtspr(SPR_PIR, id); 451 } 452 cpu_setup(self, ci); 453 break; 454 default: 455 aprint_naive("\n"); 456 if (id >= CPU_MAXNUM) { 457 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 458 panic("cpuattach"); 459 } 460 #ifndef MULTIPROCESSOR 461 aprint_normal(" not configured\n"); 462 return NULL; 463 #else 464 mi_cpu_attach(ci); 465 break; 466 #endif 467 } 468 return (ci); 469 } 470 471 void 472 cpu_setup(device_t self, struct cpu_info *ci) 473 { 474 u_int hid0, hid0_save, pvr, vers; 475 const char * const xname = device_xname(self); 476 const char *bitmask; 477 char hidbuf[128]; 478 char model[80]; 479 480 pvr = mfpvr(); 481 vers = (pvr >> 16) & 0xffff; 482 483 cpu_identify(model, sizeof(model)); 484 aprint_naive("\n"); 485 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 486 cpu_number() == 0 ? " (primary)" : ""); 487 488 /* set the cpu number */ 489 ci->ci_cpuid = cpu_number(); 490 hid0_save = hid0 = mfspr(SPR_HID0); 491 492 cpu_probe_cache(); 493 494 /* 495 * Configure power-saving mode. 496 */ 497 switch (vers) { 498 case MPC604: 499 case MPC604e: 500 case MPC604ev: 501 /* 502 * Do not have HID0 support settings, but can support 503 * MSR[POW] off 504 */ 505 powersave = 1; 506 break; 507 508 case MPC603: 509 case MPC603e: 510 case MPC603ev: 511 case MPC7400: 512 case MPC7410: 513 case MPC8240: 514 case MPC8245: 515 case MPCG2: 516 /* Select DOZE mode. */ 517 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 518 hid0 |= HID0_DOZE | HID0_DPM; 519 powersave = 1; 520 break; 521 522 case MPC750: 523 case IBM750FX: 524 case IBM750GX: 525 /* Select NAP mode. */ 526 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 527 hid0 |= HID0_NAP | HID0_DPM; 528 powersave = 1; 529 break; 530 531 case MPC7447A: 532 case MPC7448: 533 case MPC7457: 534 case MPC7455: 535 case MPC7450: 536 /* Enable the 7450 branch caches */ 537 hid0 |= HID0_SGE | HID0_BTIC; 538 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 539 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 540 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 541 hid0 &= ~HID0_BTIC; 542 /* Select NAP mode. */ 543 hid0 &= ~HID0_SLEEP; 544 hid0 |= HID0_NAP | HID0_DPM; 545 powersave = 1; 546 break; 547 548 case IBM970: 549 case IBM970FX: 550 case IBM970MP: 551 case IBMPOWER3II: 552 default: 553 /* No power-saving mode is available. */ ; 554 } 555 556 #ifdef NAPMODE 557 switch (vers) { 558 case IBM750FX: 559 case IBM750GX: 560 case MPC750: 561 case MPC7400: 562 /* Select NAP mode. */ 563 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 564 hid0 |= HID0_NAP; 565 break; 566 } 567 #endif 568 569 switch (vers) { 570 case IBM750FX: 571 case IBM750GX: 572 case MPC750: 573 hid0 &= ~HID0_DBP; /* XXX correct? */ 574 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 575 break; 576 577 case MPC7400: 578 case MPC7410: 579 hid0 &= ~HID0_SPD; 580 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 581 hid0 |= HID0_EIEC; 582 break; 583 } 584 585 #ifdef MULTIPROCESSOR 586 switch (vers) { 587 case MPC603e: 588 hid0 |= HID0_ABE; 589 } 590 #endif 591 592 if (hid0 != hid0_save) { 593 mtspr(SPR_HID0, hid0); 594 __asm volatile("sync;isync"); 595 } 596 597 598 switch (vers) { 599 case MPC601: 600 bitmask = HID0_601_BITMASK; 601 break; 602 case MPC7450: 603 case MPC7455: 604 case MPC7457: 605 bitmask = HID0_7450_BITMASK; 606 break; 607 case IBM970: 608 case IBM970FX: 609 case IBM970MP: 610 bitmask = 0; 611 break; 612 default: 613 bitmask = HID0_BITMASK; 614 break; 615 } 616 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 617 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 618 619 ci->ci_khz = 0; 620 621 /* 622 * Display speed and cache configuration. 623 */ 624 switch (vers) { 625 case MPC604: 626 case MPC604e: 627 case MPC604ev: 628 case MPC750: 629 case IBM750FX: 630 case IBM750GX: 631 case MPC7400: 632 case MPC7410: 633 case MPC7447A: 634 case MPC7448: 635 case MPC7450: 636 case MPC7455: 637 case MPC7457: 638 aprint_normal_dev(self, ""); 639 cpu_probe_speed(ci); 640 aprint_normal("%u.%02u MHz", 641 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 642 switch (vers) { 643 case MPC7450: /* 7441 does not have L3! */ 644 case MPC7455: /* 7445 does not have L3! */ 645 case MPC7457: /* 7447 does not have L3! */ 646 cpu_config_l3cr(vers); 647 break; 648 case IBM750FX: 649 case IBM750GX: 650 case MPC750: 651 case MPC7400: 652 case MPC7410: 653 case MPC7447A: 654 case MPC7448: 655 cpu_config_l2cr(pvr); 656 break; 657 default: 658 break; 659 } 660 aprint_normal("\n"); 661 break; 662 } 663 664 #if NSYSMON_ENVSYS > 0 665 /* 666 * Attach MPC750 temperature sensor to the envsys subsystem. 667 * XXX the 74xx series also has this sensor, but it is not 668 * XXX supported by Motorola and may return values that are off by 669 * XXX 35-55 degrees C. 670 */ 671 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 672 cpu_tau_setup(ci); 673 #endif 674 675 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 676 NULL, xname, "clock"); 677 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 678 NULL, xname, "traps"); 679 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 680 &ci->ci_ev_traps, xname, "kernel DSI traps"); 681 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 682 &ci->ci_ev_traps, xname, "user DSI traps"); 683 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 684 &ci->ci_ev_udsi, xname, "user DSI failures"); 685 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 686 &ci->ci_ev_traps, xname, "kernel ISI traps"); 687 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 688 &ci->ci_ev_traps, xname, "user ISI traps"); 689 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 690 &ci->ci_ev_isi, xname, "user ISI failures"); 691 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 692 &ci->ci_ev_traps, xname, "system call traps"); 693 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 694 &ci->ci_ev_traps, xname, "PGM traps"); 695 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 696 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 697 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 698 &ci->ci_ev_fpu, xname, "FPU context switches"); 699 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 700 &ci->ci_ev_traps, xname, "user alignment traps"); 701 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 702 &ci->ci_ev_ali, xname, "user alignment traps"); 703 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 704 &ci->ci_ev_umchk, xname, "user MCHK failures"); 705 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 706 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 707 #ifdef ALTIVEC 708 if (cpu_altivec) { 709 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 710 &ci->ci_ev_vec, xname, "AltiVec context switches"); 711 } 712 #endif 713 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 714 NULL, xname, "IPIs"); 715 } 716 717 /* 718 * According to a document labeled "PVR Register Settings": 719 ** For integrated microprocessors the PVR register inside the device 720 ** will identify the version of the microprocessor core. You must also 721 ** read the Device ID, PCI register 02, to identify the part and the 722 ** Revision ID, PCI register 08, to identify the revision of the 723 ** integrated microprocessor. 724 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 725 */ 726 727 void 728 cpu_identify(char *str, size_t len) 729 { 730 u_int pvr, major, minor; 731 uint16_t vers, rev, revfmt; 732 const struct cputab *cp; 733 const char *name; 734 size_t n; 735 736 pvr = mfpvr(); 737 vers = pvr >> 16; 738 rev = pvr; 739 740 switch (vers) { 741 case MPC7410: 742 minor = (pvr >> 0) & 0xff; 743 major = minor <= 4 ? 1 : 2; 744 break; 745 case MPCG2: /*XXX see note above */ 746 major = (pvr >> 4) & 0xf; 747 minor = (pvr >> 0) & 0xf; 748 break; 749 default: 750 major = (pvr >> 8) & 0xf; 751 minor = (pvr >> 0) & 0xf; 752 } 753 754 for (cp = models; cp->name[0] != '\0'; cp++) { 755 if (cp->version == vers) 756 break; 757 } 758 759 if (str == NULL) { 760 str = cpu_model; 761 len = sizeof(cpu_model); 762 cpu = vers; 763 } 764 765 revfmt = cp->revfmt; 766 name = cp->name; 767 if (rev == MPC750 && pvr == 15) { 768 name = "755"; 769 revfmt = REVFMT_HEX; 770 } 771 772 if (cp->name[0] != '\0') { 773 n = snprintf(str, len, "%s (Revision ", cp->name); 774 } else { 775 n = snprintf(str, len, "Version %#x (Revision ", vers); 776 } 777 if (len > n) { 778 switch (revfmt) { 779 case REVFMT_MAJMIN: 780 snprintf(str + n, len - n, "%u.%u)", major, minor); 781 break; 782 case REVFMT_HEX: 783 snprintf(str + n, len - n, "0x%04x)", rev); 784 break; 785 case REVFMT_DEC: 786 snprintf(str + n, len - n, "%u)", rev); 787 break; 788 } 789 } 790 } 791 792 #ifdef L2CR_CONFIG 793 u_int l2cr_config = L2CR_CONFIG; 794 #else 795 u_int l2cr_config = 0; 796 #endif 797 798 #ifdef L3CR_CONFIG 799 u_int l3cr_config = L3CR_CONFIG; 800 #else 801 u_int l3cr_config = 0; 802 #endif 803 804 void 805 cpu_enable_l2cr(register_t l2cr) 806 { 807 register_t msr, x; 808 uint16_t vers; 809 810 vers = mfpvr() >> 16; 811 812 /* Disable interrupts and set the cache config bits. */ 813 msr = mfmsr(); 814 mtmsr(msr & ~PSL_EE); 815 #ifdef ALTIVEC 816 if (cpu_altivec) 817 __asm volatile("dssall"); 818 #endif 819 __asm volatile("sync"); 820 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 821 __asm volatile("sync"); 822 823 /* Wait for L2 clock to be stable (640 L2 clocks). */ 824 delay(100); 825 826 /* Invalidate all L2 contents. */ 827 if (MPC745X_P(vers)) { 828 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 829 do { 830 x = mfspr(SPR_L2CR); 831 } while (x & L2CR_L2I); 832 } else { 833 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 834 do { 835 x = mfspr(SPR_L2CR); 836 } while (x & L2CR_L2IP); 837 } 838 /* Enable L2 cache. */ 839 l2cr |= L2CR_L2E; 840 mtspr(SPR_L2CR, l2cr); 841 mtmsr(msr); 842 } 843 844 void 845 cpu_enable_l3cr(register_t l3cr) 846 { 847 register_t x; 848 849 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 850 851 /* 852 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 853 * L3CLKEN. (also mask off reserved bits in case they were included 854 * in L3CR_CONFIG) 855 */ 856 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 857 mtspr(SPR_L3CR, l3cr); 858 859 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 860 l3cr |= 0x04000000; 861 mtspr(SPR_L3CR, l3cr); 862 863 /* 3: Set L3CLKEN to 1*/ 864 l3cr |= L3CR_L3CLKEN; 865 mtspr(SPR_L3CR, l3cr); 866 867 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 868 __asm volatile("dssall;sync"); 869 /* L3 cache is already disabled, no need to clear L3E */ 870 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 871 do { 872 x = mfspr(SPR_L3CR); 873 } while (x & L3CR_L3I); 874 875 /* 6: Clear L3CLKEN to 0 */ 876 l3cr &= ~L3CR_L3CLKEN; 877 mtspr(SPR_L3CR, l3cr); 878 879 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 880 __asm volatile("sync"); 881 delay(100); 882 883 /* 8: Set L3E and L3CLKEN */ 884 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 885 mtspr(SPR_L3CR, l3cr); 886 887 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 888 __asm volatile("sync"); 889 delay(100); 890 } 891 892 void 893 cpu_config_l2cr(int pvr) 894 { 895 register_t l2cr; 896 u_int vers = (pvr >> 16) & 0xffff; 897 898 l2cr = mfspr(SPR_L2CR); 899 900 /* 901 * For MP systems, the firmware may only configure the L2 cache 902 * on the first CPU. In this case, assume that the other CPUs 903 * should use the same value for L2CR. 904 */ 905 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 906 l2cr_config = l2cr; 907 } 908 909 /* 910 * Configure L2 cache if not enabled. 911 */ 912 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 913 cpu_enable_l2cr(l2cr_config); 914 l2cr = mfspr(SPR_L2CR); 915 } 916 917 if ((l2cr & L2CR_L2E) == 0) { 918 aprint_normal(" L2 cache present but not enabled "); 919 return; 920 } 921 aprint_normal(","); 922 923 switch (vers) { 924 case IBM750FX: 925 case IBM750GX: 926 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 927 break; 928 case MPC750: 929 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 930 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 931 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 932 else 933 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 934 break; 935 case MPC7447A: 936 case MPC7457: 937 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 938 return; 939 case MPC7448: 940 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 941 return; 942 case MPC7450: 943 case MPC7455: 944 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 945 break; 946 default: 947 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 948 break; 949 } 950 } 951 952 void 953 cpu_config_l3cr(int vers) 954 { 955 register_t l2cr; 956 register_t l3cr; 957 958 l2cr = mfspr(SPR_L2CR); 959 960 /* 961 * For MP systems, the firmware may only configure the L2 cache 962 * on the first CPU. In this case, assume that the other CPUs 963 * should use the same value for L2CR. 964 */ 965 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 966 l2cr_config = l2cr; 967 } 968 969 /* 970 * Configure L2 cache if not enabled. 971 */ 972 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 973 cpu_enable_l2cr(l2cr_config); 974 l2cr = mfspr(SPR_L2CR); 975 } 976 977 aprint_normal(","); 978 switch (vers) { 979 case MPC7447A: 980 case MPC7457: 981 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 982 return; 983 case MPC7448: 984 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 985 return; 986 default: 987 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 988 break; 989 } 990 991 l3cr = mfspr(SPR_L3CR); 992 993 /* 994 * For MP systems, the firmware may only configure the L3 cache 995 * on the first CPU. In this case, assume that the other CPUs 996 * should use the same value for L3CR. 997 */ 998 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 999 l3cr_config = l3cr; 1000 } 1001 1002 /* 1003 * Configure L3 cache if not enabled. 1004 */ 1005 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1006 cpu_enable_l3cr(l3cr_config); 1007 l3cr = mfspr(SPR_L3CR); 1008 } 1009 1010 if (l3cr & L3CR_L3E) { 1011 aprint_normal(","); 1012 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1013 } 1014 } 1015 1016 void 1017 cpu_probe_speed(struct cpu_info *ci) 1018 { 1019 uint64_t cps; 1020 1021 mtspr(SPR_MMCR0, MMCR0_FC); 1022 mtspr(SPR_PMC1, 0); 1023 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1024 delay(100000); 1025 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1026 1027 mtspr(SPR_MMCR0, MMCR0_FC); 1028 1029 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1030 } 1031 1032 /* 1033 * Read the Dynamic Frequency Switching state and return a divisor for 1034 * the maximum frequency. 1035 */ 1036 int 1037 cpu_get_dfs(void) 1038 { 1039 u_int pvr, vers; 1040 1041 pvr = mfpvr(); 1042 vers = pvr >> 16; 1043 1044 switch (vers) { 1045 case MPC7448: 1046 if (mfspr(SPR_HID1) & HID1_DFS4) 1047 return 4; 1048 case MPC7447A: 1049 if (mfspr(SPR_HID1) & HID1_DFS2) 1050 return 2; 1051 } 1052 return 1; 1053 } 1054 1055 /* 1056 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1057 */ 1058 void 1059 cpu_set_dfs(int div) 1060 { 1061 uint64_t where; 1062 u_int dfs_mask, pvr, vers; 1063 1064 pvr = mfpvr(); 1065 vers = pvr >> 16; 1066 dfs_mask = 0; 1067 1068 switch (vers) { 1069 case MPC7448: 1070 dfs_mask |= HID1_DFS4; 1071 case MPC7447A: 1072 dfs_mask |= HID1_DFS2; 1073 break; 1074 default: 1075 printf("cpu_set_dfs: DFS not supported\n"); 1076 return; 1077 1078 } 1079 1080 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1081 xc_wait(where); 1082 } 1083 1084 static void 1085 cpu_set_dfs_xcall(void *arg1, void *arg2) 1086 { 1087 u_int dfs_mask, hid1, old_hid1; 1088 int *divisor, s; 1089 1090 divisor = arg1; 1091 dfs_mask = *(u_int *)arg2; 1092 1093 s = splhigh(); 1094 hid1 = old_hid1 = mfspr(SPR_HID1); 1095 1096 switch (*divisor) { 1097 case 1: 1098 hid1 &= ~dfs_mask; 1099 break; 1100 case 2: 1101 hid1 &= ~(dfs_mask & HID1_DFS4); 1102 hid1 |= dfs_mask & HID1_DFS2; 1103 break; 1104 case 4: 1105 hid1 &= ~(dfs_mask & HID1_DFS2); 1106 hid1 |= dfs_mask & HID1_DFS4; 1107 break; 1108 } 1109 1110 if (hid1 != old_hid1) { 1111 __asm volatile("sync"); 1112 mtspr(SPR_HID1, hid1); 1113 __asm volatile("sync;isync"); 1114 } 1115 1116 splx(s); 1117 } 1118 1119 #if NSYSMON_ENVSYS > 0 1120 void 1121 cpu_tau_setup(struct cpu_info *ci) 1122 { 1123 struct sysmon_envsys *sme; 1124 int error, therm_delay; 1125 1126 mtspr(SPR_THRM1, SPR_THRM_VALID); 1127 mtspr(SPR_THRM2, 0); 1128 1129 /* 1130 * we need to figure out how much 20+us in units of CPU clock cycles 1131 * are 1132 */ 1133 1134 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1135 1136 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1137 1138 sme = sysmon_envsys_create(); 1139 1140 sensor.units = ENVSYS_STEMP; 1141 sensor.state = ENVSYS_SINVALID; 1142 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1143 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1144 sysmon_envsys_destroy(sme); 1145 return; 1146 } 1147 1148 sme->sme_name = device_xname(ci->ci_dev); 1149 sme->sme_cookie = ci; 1150 sme->sme_refresh = cpu_tau_refresh; 1151 1152 if ((error = sysmon_envsys_register(sme)) != 0) { 1153 aprint_error_dev(ci->ci_dev, 1154 " unable to register with sysmon (%d)\n", error); 1155 sysmon_envsys_destroy(sme); 1156 } 1157 } 1158 1159 1160 /* Find the temperature of the CPU. */ 1161 void 1162 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1163 { 1164 int i, threshold, count; 1165 1166 threshold = 64; /* Half of the 7-bit sensor range */ 1167 1168 /* Successive-approximation code adapted from Motorola 1169 * application note AN1800/D, "Programming the Thermal Assist 1170 * Unit in the MPC750 Microprocessor". 1171 */ 1172 for (i = 5; i >= 0 ; i--) { 1173 mtspr(SPR_THRM1, 1174 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1175 count = 0; 1176 while ((count < 100000) && 1177 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1178 count++; 1179 delay(1); 1180 } 1181 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1182 /* The interrupt bit was set, meaning the 1183 * temperature was above the threshold 1184 */ 1185 threshold += 1 << i; 1186 } else { 1187 /* Temperature was below the threshold */ 1188 threshold -= 1 << i; 1189 } 1190 } 1191 threshold += 2; 1192 1193 /* Convert the temperature in degrees C to microkelvin */ 1194 edata->value_cur = (threshold * 1000000) + 273150000; 1195 edata->state = ENVSYS_SVALID; 1196 } 1197 #endif /* NSYSMON_ENVSYS > 0 */ 1198 1199 #ifdef MULTIPROCESSOR 1200 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1201 1202 int 1203 cpu_spinup(device_t self, struct cpu_info *ci) 1204 { 1205 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1206 struct pglist mlist; 1207 int i, error, pvr, vers; 1208 char *hp; 1209 1210 pvr = mfpvr(); 1211 vers = pvr >> 16; 1212 KASSERT(ci != curcpu()); 1213 1214 /* Now allocate a hatch stack */ 1215 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1216 &mlist, 1, 1); 1217 if (error) { 1218 aprint_error(": unable to allocate hatch stack\n"); 1219 return -1; 1220 } 1221 1222 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1223 memset(hp, 0, HATCH_STACK_SIZE); 1224 1225 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1226 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1227 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1228 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1229 1230 cpu_hatch_data = h; 1231 h->hatch_running = 0; 1232 h->hatch_self = self; 1233 h->hatch_ci = ci; 1234 h->hatch_pir = ci->ci_cpuid; 1235 1236 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1237 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1238 1239 /* copy special registers */ 1240 1241 h->hatch_hid0 = mfspr(SPR_HID0); 1242 1243 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1244 for (i = 0; i < 16; i++) { 1245 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1246 "r"(i << ADDR_SR_SHFT)); 1247 } 1248 if (oeacpufeat & OEACPU_64) 1249 h->hatch_asr = mfspr(SPR_ASR); 1250 else 1251 h->hatch_asr = 0; 1252 1253 /* copy the bat regs */ 1254 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1255 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1256 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1257 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1258 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1259 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1260 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1261 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1262 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1263 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1264 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1265 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1266 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1267 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1268 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1269 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1270 __asm volatile ("sync; isync"); 1271 1272 if (md_setup_trampoline(h, ci) == -1) 1273 return -1; 1274 md_presync_timebase(h); 1275 md_start_timebase(h); 1276 1277 /* wait for secondary printf */ 1278 1279 delay(200000); 1280 1281 #ifdef CACHE_PROTO_MEI 1282 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1283 __asm volatile ("sync; isync"); 1284 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1285 __asm volatile ("sync; isync"); 1286 #endif 1287 if (h->hatch_running < 1) { 1288 #ifdef CACHE_PROTO_MEI 1289 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1290 __asm volatile ("sync; isync"); 1291 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1292 __asm volatile ("sync; isync"); 1293 #endif 1294 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1295 ci->ci_cpuid, cpu_spinstart_ack); 1296 Debugger(); 1297 return -1; 1298 } 1299 1300 /* Register IPI Interrupt */ 1301 if (ipiops.ppc_establish_ipi) 1302 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1303 1304 return 0; 1305 } 1306 1307 static volatile int start_secondary_cpu; 1308 1309 register_t 1310 cpu_hatch(void) 1311 { 1312 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1313 struct cpu_info * const ci = h->hatch_ci; 1314 struct pcb *pcb; 1315 u_int msr; 1316 int i; 1317 1318 /* Initialize timebase. */ 1319 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1320 1321 /* 1322 * Set PIR (Processor Identification Register). i.e. whoami 1323 * Note that PIR is read-only on some CPU versions, so we write to it 1324 * only if it has a different value than we need. 1325 */ 1326 1327 msr = mfspr(SPR_PIR); 1328 if (msr != h->hatch_pir) 1329 mtspr(SPR_PIR, h->hatch_pir); 1330 1331 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1332 curlwp = ci->ci_curlwp; 1333 cpu_spinstart_ack = 0; 1334 1335 /* Initialize MMU. */ 1336 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1337 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1338 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1339 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1340 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1341 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1342 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1343 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1344 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1345 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1346 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1347 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1348 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1349 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1350 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1351 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1352 1353 mtspr(SPR_HID0, h->hatch_hid0); 1354 1355 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1356 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1357 1358 __asm volatile ("sync"); 1359 for (i = 0; i < 16; i++) 1360 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1361 __asm volatile ("sync; isync"); 1362 1363 if (oeacpufeat & OEACPU_64) 1364 mtspr(SPR_ASR, h->hatch_asr); 1365 1366 cpu_spinstart_ack = 1; 1367 __asm ("ptesync"); 1368 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1369 __asm volatile ("sync; isync"); 1370 1371 cpu_spinstart_ack = 5; 1372 for (i = 0; i < 16; i++) 1373 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1374 "r"(i << ADDR_SR_SHFT)); 1375 1376 /* Enable I/D address translations. */ 1377 msr = mfmsr(); 1378 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1379 mtmsr(msr); 1380 __asm volatile ("sync; isync"); 1381 cpu_spinstart_ack = 2; 1382 1383 md_sync_timebase(h); 1384 1385 cpu_setup(h->hatch_self, ci); 1386 1387 h->hatch_running = 1; 1388 __asm volatile ("sync; isync"); 1389 1390 while (start_secondary_cpu == 0) 1391 ; 1392 1393 __asm volatile ("sync; isync"); 1394 1395 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1396 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1397 1398 md_setup_interrupts(); 1399 1400 ci->ci_ipending = 0; 1401 ci->ci_cpl = 0; 1402 1403 mtmsr(mfmsr() | PSL_EE); 1404 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1405 return pcb->pcb_sp; 1406 } 1407 1408 void 1409 cpu_boot_secondary_processors(void) 1410 { 1411 start_secondary_cpu = 1; 1412 __asm volatile ("sync"); 1413 } 1414 1415 #endif /*MULTIPROCESSOR*/ 1416