1 /* $NetBSD: cpu_subr.c,v 1.46 2008/04/08 02:33:03 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.46 2008/04/08 02:33:03 garbled Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/cpufeat.h> 58 59 #include <dev/sysmon/sysmonvar.h> 60 61 static void cpu_enable_l2cr(register_t); 62 static void cpu_enable_l3cr(register_t); 63 static void cpu_config_l2cr(int); 64 static void cpu_config_l3cr(int); 65 static void cpu_probe_speed(struct cpu_info *); 66 static void cpu_idlespin(void); 67 #if NSYSMON_ENVSYS > 0 68 static void cpu_tau_setup(struct cpu_info *); 69 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 70 #endif 71 72 int cpu; 73 int ncpus; 74 75 struct fmttab { 76 register_t fmt_mask; 77 register_t fmt_value; 78 const char *fmt_string; 79 }; 80 81 static const struct fmttab cpu_7450_l2cr_formats[] = { 82 { L2CR_L2E, 0, " disabled" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 85 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 86 { L2CR_L2E, ~0, " 256KB L2 cache" }, 87 { L2CR_L2PE, 0, " no parity" }, 88 { L2CR_L2PE, ~0, " parity enabled" }, 89 { 0, 0, NULL } 90 }; 91 92 static const struct fmttab cpu_7448_l2cr_formats[] = { 93 { L2CR_L2E, 0, " disabled" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 97 { L2CR_L2E, ~0, " 1MB L2 cache" }, 98 { L2CR_L2PE, 0, " no parity" }, 99 { L2CR_L2PE, ~0, " parity enabled" }, 100 { 0, 0, NULL } 101 }; 102 103 static const struct fmttab cpu_7457_l2cr_formats[] = { 104 { L2CR_L2E, 0, " disabled" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 108 { L2CR_L2E, ~0, " 512KB L2 cache" }, 109 { L2CR_L2PE, 0, " no parity" }, 110 { L2CR_L2PE, ~0, " parity enabled" }, 111 { 0, 0, NULL } 112 }; 113 114 static const struct fmttab cpu_7450_l3cr_formats[] = { 115 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 116 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 117 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 118 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 119 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 120 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 121 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 122 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 123 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 124 { L3CR_L3SIZ, ~0, " L3 cache" }, 125 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 126 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 127 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 128 { L3CR_L3CLK, ~0, " at" }, 129 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 130 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 131 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 132 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 133 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 134 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 135 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 136 { L3CR_L3CLK, ~0, " ratio" }, 137 { 0, 0, NULL }, 138 }; 139 140 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 141 { L2CR_L2E, 0, " disabled" }, 142 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 143 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 144 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 145 { 0, ~0, " 512KB" }, 146 { L2CR_L2WT, L2CR_L2WT, " WT" }, 147 { L2CR_L2WT, 0, " WB" }, 148 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 149 { 0, ~0, " L2 cache" }, 150 { 0, 0, NULL } 151 }; 152 153 static const struct fmttab cpu_l2cr_formats[] = { 154 { L2CR_L2E, 0, " disabled" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 157 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 158 { L2CR_L2PE, L2CR_L2PE, " parity" }, 159 { L2CR_L2PE, 0, " no-parity" }, 160 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 161 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 162 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 163 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 164 { L2CR_L2WT, L2CR_L2WT, " WT" }, 165 { L2CR_L2WT, 0, " WB" }, 166 { L2CR_L2E, ~0, " L2 cache" }, 167 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 168 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 169 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 170 { L2CR_L2CLK, ~0, " at" }, 171 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 172 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 173 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 174 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 175 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 176 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 177 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 178 { L2CR_L2CLK, ~0, " ratio" }, 179 { 0, 0, NULL } 180 }; 181 182 static void cpu_fmttab_print(const struct fmttab *, register_t); 183 184 struct cputab { 185 const char name[8]; 186 uint16_t version; 187 uint16_t revfmt; 188 }; 189 #define REVFMT_MAJMIN 1 /* %u.%u */ 190 #define REVFMT_HEX 2 /* 0x%04x */ 191 #define REVFMT_DEC 3 /* %u */ 192 static const struct cputab models[] = { 193 { "601", MPC601, REVFMT_DEC }, 194 { "602", MPC602, REVFMT_DEC }, 195 { "603", MPC603, REVFMT_MAJMIN }, 196 { "603e", MPC603e, REVFMT_MAJMIN }, 197 { "603ev", MPC603ev, REVFMT_MAJMIN }, 198 { "G2", MPCG2, REVFMT_MAJMIN }, 199 { "604", MPC604, REVFMT_MAJMIN }, 200 { "604e", MPC604e, REVFMT_MAJMIN }, 201 { "604ev", MPC604ev, REVFMT_MAJMIN }, 202 { "620", MPC620, REVFMT_HEX }, 203 { "750", MPC750, REVFMT_MAJMIN }, 204 { "750FX", IBM750FX, REVFMT_MAJMIN }, 205 { "7400", MPC7400, REVFMT_MAJMIN }, 206 { "7410", MPC7410, REVFMT_MAJMIN }, 207 { "7450", MPC7450, REVFMT_MAJMIN }, 208 { "7455", MPC7455, REVFMT_MAJMIN }, 209 { "7457", MPC7457, REVFMT_MAJMIN }, 210 { "7447A", MPC7447A, REVFMT_MAJMIN }, 211 { "7448", MPC7448, REVFMT_MAJMIN }, 212 { "8240", MPC8240, REVFMT_MAJMIN }, 213 { "8245", MPC8245, REVFMT_MAJMIN }, 214 { "970", IBM970, REVFMT_MAJMIN }, 215 { "970FX", IBM970FX, REVFMT_MAJMIN }, 216 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 217 { "", 0, REVFMT_HEX } 218 }; 219 220 #ifdef MULTIPROCESSOR 221 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 222 volatile struct cpu_hatch_data *cpu_hatch_data; 223 volatile int cpu_hatch_stack; 224 extern int ticks_per_intr; 225 #include <powerpc/oea/bat.h> 226 #include <arch/powerpc/pic/picvar.h> 227 #include <arch/powerpc/pic/ipivar.h> 228 extern struct bat battable[]; 229 #else 230 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 231 #endif /*MULTIPROCESSOR*/ 232 233 int cpu_altivec; 234 int cpu_psluserset, cpu_pslusermod; 235 char cpu_model[80]; 236 237 /* This is to be called from locore.S, and nowhere else. */ 238 239 void 240 cpu_model_init(void) 241 { 242 u_int pvr, vers; 243 244 pvr = mfpvr(); 245 vers = pvr >> 16; 246 247 oeacpufeat = 0; 248 249 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 250 vers == IBMCELL || vers == IBMPOWER6P5) 251 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 252 253 else if (vers == MPC601) 254 oeacpufeat |= OEACPU_601; 255 256 else if (MPC745X_P(vers) && vers != MPC7450) 257 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 258 } 259 260 void 261 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 262 { 263 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 264 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 265 (data & fmt->fmt_mask) == fmt->fmt_value) 266 aprint_normal("%s", fmt->fmt_string); 267 } 268 } 269 270 void 271 cpu_idlespin(void) 272 { 273 register_t msr; 274 275 if (powersave <= 0) 276 return; 277 278 __asm volatile( 279 "sync;" 280 "mfmsr %0;" 281 "oris %0,%0,%1@h;" /* enter power saving mode */ 282 "mtmsr %0;" 283 "isync;" 284 : "=r"(msr) 285 : "J"(PSL_POW)); 286 } 287 288 void 289 cpu_probe_cache(void) 290 { 291 u_int assoc, pvr, vers; 292 293 pvr = mfpvr(); 294 vers = pvr >> 16; 295 296 297 /* Presently common across almost all implementations. */ 298 curcpu()->ci_ci.dcache_line_size = 32; 299 curcpu()->ci_ci.icache_line_size = 32; 300 301 302 switch (vers) { 303 #define K *1024 304 case IBM750FX: 305 case MPC601: 306 case MPC750: 307 case MPC7447A: 308 case MPC7448: 309 case MPC7450: 310 case MPC7455: 311 case MPC7457: 312 curcpu()->ci_ci.dcache_size = 32 K; 313 curcpu()->ci_ci.icache_size = 32 K; 314 assoc = 8; 315 break; 316 case MPC603: 317 curcpu()->ci_ci.dcache_size = 8 K; 318 curcpu()->ci_ci.icache_size = 8 K; 319 assoc = 2; 320 break; 321 case MPC603e: 322 case MPC603ev: 323 case MPC604: 324 case MPC8240: 325 case MPC8245: 326 case MPCG2: 327 curcpu()->ci_ci.dcache_size = 16 K; 328 curcpu()->ci_ci.icache_size = 16 K; 329 assoc = 4; 330 break; 331 case MPC604e: 332 case MPC604ev: 333 curcpu()->ci_ci.dcache_size = 32 K; 334 curcpu()->ci_ci.icache_size = 32 K; 335 assoc = 4; 336 break; 337 case IBMPOWER3II: 338 curcpu()->ci_ci.dcache_size = 64 K; 339 curcpu()->ci_ci.icache_size = 32 K; 340 curcpu()->ci_ci.dcache_line_size = 128; 341 curcpu()->ci_ci.icache_line_size = 128; 342 assoc = 128; /* not a typo */ 343 break; 344 case IBM970: 345 case IBM970FX: 346 curcpu()->ci_ci.dcache_size = 32 K; 347 curcpu()->ci_ci.icache_size = 64 K; 348 curcpu()->ci_ci.dcache_line_size = 128; 349 curcpu()->ci_ci.icache_line_size = 128; 350 assoc = 2; 351 break; 352 353 default: 354 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 355 curcpu()->ci_ci.icache_size = PAGE_SIZE; 356 assoc = 1; 357 #undef K 358 } 359 360 /* 361 * Possibly recolor. 362 */ 363 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 364 } 365 366 struct cpu_info * 367 cpu_attach_common(struct device *self, int id) 368 { 369 struct cpu_info *ci; 370 u_int pvr, vers; 371 372 ci = &cpu_info[id]; 373 #ifndef MULTIPROCESSOR 374 /* 375 * If this isn't the primary CPU, print an error message 376 * and just bail out. 377 */ 378 if (id != 0) { 379 aprint_normal(": ID %d\n", id); 380 aprint_normal("%s: processor off-line; multiprocessor support " 381 "not present in kernel\n", self->dv_xname); 382 return (NULL); 383 } 384 #endif 385 386 ci->ci_cpuid = id; 387 ci->ci_intrdepth = -1; 388 ci->ci_dev = self; 389 ci->ci_idlespin = cpu_idlespin; 390 391 pvr = mfpvr(); 392 vers = (pvr >> 16) & 0xffff; 393 394 switch (id) { 395 case 0: 396 /* load my cpu_number to PIR */ 397 switch (vers) { 398 case MPC601: 399 case MPC604: 400 case MPC604e: 401 case MPC604ev: 402 case MPC7400: 403 case MPC7410: 404 case MPC7447A: 405 case MPC7448: 406 case MPC7450: 407 case MPC7455: 408 case MPC7457: 409 mtspr(SPR_PIR, id); 410 } 411 cpu_setup(self, ci); 412 break; 413 default: 414 if (id >= CPU_MAXNUM) { 415 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 416 panic("cpuattach"); 417 } 418 #ifndef MULTIPROCESSOR 419 aprint_normal(" not configured\n"); 420 return NULL; 421 #else 422 mi_cpu_attach(ci); 423 break; 424 #endif 425 } 426 return (ci); 427 } 428 429 void 430 cpu_setup(self, ci) 431 struct device *self; 432 struct cpu_info *ci; 433 { 434 u_int hid0, hid0_save, pvr, vers; 435 const char *bitmask; 436 char hidbuf[128]; 437 char model[80]; 438 439 pvr = mfpvr(); 440 vers = (pvr >> 16) & 0xffff; 441 442 cpu_identify(model, sizeof(model)); 443 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 444 cpu_number() == 0 ? " (primary)" : ""); 445 446 /* set the cpu number */ 447 ci->ci_cpuid = cpu_number(); 448 hid0_save = hid0 = mfspr(SPR_HID0); 449 450 cpu_probe_cache(); 451 452 /* 453 * Configure power-saving mode. 454 */ 455 switch (vers) { 456 case MPC604: 457 case MPC604e: 458 case MPC604ev: 459 /* 460 * Do not have HID0 support settings, but can support 461 * MSR[POW] off 462 */ 463 powersave = 1; 464 break; 465 466 case MPC603: 467 case MPC603e: 468 case MPC603ev: 469 case MPC750: 470 case IBM750FX: 471 case MPC7400: 472 case MPC7410: 473 case MPC8240: 474 case MPC8245: 475 case MPCG2: 476 /* Select DOZE mode. */ 477 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 478 hid0 |= HID0_DOZE | HID0_DPM; 479 powersave = 1; 480 break; 481 482 case MPC7447A: 483 case MPC7448: 484 case MPC7457: 485 case MPC7455: 486 case MPC7450: 487 /* Enable the 7450 branch caches */ 488 hid0 |= HID0_SGE | HID0_BTIC; 489 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 490 /* Enable more and larger BAT registers */ 491 if (oeacpufeat & OEACPU_XBSEN) 492 hid0 |= HID0_XBSEN; 493 if (oeacpufeat & OEACPU_HIGHBAT) 494 hid0 |= HID0_HIGH_BAT_EN; 495 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 496 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 497 hid0 &= ~HID0_BTIC; 498 /* Select NAP mode. */ 499 hid0 &= ~HID0_SLEEP; 500 hid0 |= HID0_NAP | HID0_DPM; 501 powersave = 1; 502 break; 503 504 case IBM970: 505 case IBM970FX: 506 case IBMPOWER3II: 507 default: 508 /* No power-saving mode is available. */ ; 509 } 510 511 #ifdef NAPMODE 512 switch (vers) { 513 case IBM750FX: 514 case MPC750: 515 case MPC7400: 516 /* Select NAP mode. */ 517 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 518 hid0 |= HID0_NAP; 519 break; 520 } 521 #endif 522 523 switch (vers) { 524 case IBM750FX: 525 case MPC750: 526 hid0 &= ~HID0_DBP; /* XXX correct? */ 527 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 528 break; 529 530 case MPC7400: 531 case MPC7410: 532 hid0 &= ~HID0_SPD; 533 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 534 hid0 |= HID0_EIEC; 535 break; 536 } 537 538 if (hid0 != hid0_save) { 539 mtspr(SPR_HID0, hid0); 540 __asm volatile("sync;isync"); 541 } 542 543 544 switch (vers) { 545 case MPC601: 546 bitmask = HID0_601_BITMASK; 547 break; 548 case MPC7450: 549 case MPC7455: 550 case MPC7457: 551 bitmask = HID0_7450_BITMASK; 552 break; 553 case IBM970: 554 case IBM970FX: 555 bitmask = 0; 556 break; 557 default: 558 bitmask = HID0_BITMASK; 559 break; 560 } 561 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 562 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 563 powersave); 564 565 ci->ci_khz = 0; 566 567 /* 568 * Display speed and cache configuration. 569 */ 570 switch (vers) { 571 case MPC604: 572 case MPC604e: 573 case MPC604ev: 574 case MPC750: 575 case IBM750FX: 576 case MPC7400: 577 case MPC7410: 578 case MPC7447A: 579 case MPC7448: 580 case MPC7450: 581 case MPC7455: 582 case MPC7457: 583 aprint_normal("%s: ", self->dv_xname); 584 cpu_probe_speed(ci); 585 aprint_normal("%u.%02u MHz", 586 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 587 switch (vers) { 588 case MPC7450: /* 7441 does not have L3! */ 589 case MPC7455: /* 7445 does not have L3! */ 590 case MPC7457: /* 7447 does not have L3! */ 591 cpu_config_l3cr(vers); 592 break; 593 case IBM750FX: 594 case MPC750: 595 case MPC7400: 596 case MPC7410: 597 case MPC7447A: 598 case MPC7448: 599 cpu_config_l2cr(pvr); 600 break; 601 default: 602 break; 603 } 604 aprint_normal("\n"); 605 break; 606 } 607 608 #if NSYSMON_ENVSYS > 0 609 /* 610 * Attach MPC750 temperature sensor to the envsys subsystem. 611 * XXX the 74xx series also has this sensor, but it is not 612 * XXX supported by Motorola and may return values that are off by 613 * XXX 35-55 degrees C. 614 */ 615 if (vers == MPC750 || vers == IBM750FX) 616 cpu_tau_setup(ci); 617 #endif 618 619 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 620 NULL, self->dv_xname, "clock"); 621 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 622 NULL, self->dv_xname, "soft clock"); 623 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 624 NULL, self->dv_xname, "soft net"); 625 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 626 NULL, self->dv_xname, "soft serial"); 627 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 628 NULL, self->dv_xname, "traps"); 629 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 630 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 631 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 632 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 633 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 634 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 635 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 636 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 637 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 638 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 639 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 640 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 641 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 642 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 643 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 644 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 645 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 646 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 647 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 648 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 649 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 650 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 651 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 652 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 653 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 654 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 655 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 656 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 657 #ifdef ALTIVEC 658 if (cpu_altivec) { 659 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 660 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 661 } 662 #endif 663 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 664 NULL, self->dv_xname, "IPIs"); 665 } 666 667 /* 668 * According to a document labeled "PVR Register Settings": 669 ** For integrated microprocessors the PVR register inside the device 670 ** will identify the version of the microprocessor core. You must also 671 ** read the Device ID, PCI register 02, to identify the part and the 672 ** Revision ID, PCI register 08, to identify the revision of the 673 ** integrated microprocessor. 674 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 675 */ 676 677 void 678 cpu_identify(char *str, size_t len) 679 { 680 u_int pvr, major, minor; 681 uint16_t vers, rev, revfmt; 682 const struct cputab *cp; 683 const char *name; 684 size_t n; 685 686 pvr = mfpvr(); 687 vers = pvr >> 16; 688 rev = pvr; 689 690 switch (vers) { 691 case MPC7410: 692 minor = (pvr >> 0) & 0xff; 693 major = minor <= 4 ? 1 : 2; 694 break; 695 case MPCG2: /*XXX see note above */ 696 major = (pvr >> 4) & 0xf; 697 minor = (pvr >> 0) & 0xf; 698 break; 699 default: 700 major = (pvr >> 8) & 0xf; 701 minor = (pvr >> 0) & 0xf; 702 } 703 704 for (cp = models; cp->name[0] != '\0'; cp++) { 705 if (cp->version == vers) 706 break; 707 } 708 709 if (str == NULL) { 710 str = cpu_model; 711 len = sizeof(cpu_model); 712 cpu = vers; 713 } 714 715 revfmt = cp->revfmt; 716 name = cp->name; 717 if (rev == MPC750 && pvr == 15) { 718 name = "755"; 719 revfmt = REVFMT_HEX; 720 } 721 722 if (cp->name[0] != '\0') { 723 n = snprintf(str, len, "%s (Revision ", cp->name); 724 } else { 725 n = snprintf(str, len, "Version %#x (Revision ", vers); 726 } 727 if (len > n) { 728 switch (revfmt) { 729 case REVFMT_MAJMIN: 730 snprintf(str + n, len - n, "%u.%u)", major, minor); 731 break; 732 case REVFMT_HEX: 733 snprintf(str + n, len - n, "0x%04x)", rev); 734 break; 735 case REVFMT_DEC: 736 snprintf(str + n, len - n, "%u)", rev); 737 break; 738 } 739 } 740 } 741 742 #ifdef L2CR_CONFIG 743 u_int l2cr_config = L2CR_CONFIG; 744 #else 745 u_int l2cr_config = 0; 746 #endif 747 748 #ifdef L3CR_CONFIG 749 u_int l3cr_config = L3CR_CONFIG; 750 #else 751 u_int l3cr_config = 0; 752 #endif 753 754 void 755 cpu_enable_l2cr(register_t l2cr) 756 { 757 register_t msr, x; 758 uint16_t vers; 759 760 vers = mfpvr() >> 16; 761 762 /* Disable interrupts and set the cache config bits. */ 763 msr = mfmsr(); 764 mtmsr(msr & ~PSL_EE); 765 #ifdef ALTIVEC 766 if (cpu_altivec) 767 __asm volatile("dssall"); 768 #endif 769 __asm volatile("sync"); 770 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 771 __asm volatile("sync"); 772 773 /* Wait for L2 clock to be stable (640 L2 clocks). */ 774 delay(100); 775 776 /* Invalidate all L2 contents. */ 777 if (MPC745X_P(vers)) { 778 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 779 do { 780 x = mfspr(SPR_L2CR); 781 } while (x & L2CR_L2I); 782 } else { 783 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 784 do { 785 x = mfspr(SPR_L2CR); 786 } while (x & L2CR_L2IP); 787 } 788 /* Enable L2 cache. */ 789 l2cr |= L2CR_L2E; 790 mtspr(SPR_L2CR, l2cr); 791 mtmsr(msr); 792 } 793 794 void 795 cpu_enable_l3cr(register_t l3cr) 796 { 797 register_t x; 798 799 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 800 801 /* 802 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 803 * L3CLKEN. (also mask off reserved bits in case they were included 804 * in L3CR_CONFIG) 805 */ 806 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 807 mtspr(SPR_L3CR, l3cr); 808 809 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 810 l3cr |= 0x04000000; 811 mtspr(SPR_L3CR, l3cr); 812 813 /* 3: Set L3CLKEN to 1*/ 814 l3cr |= L3CR_L3CLKEN; 815 mtspr(SPR_L3CR, l3cr); 816 817 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 818 __asm volatile("dssall;sync"); 819 /* L3 cache is already disabled, no need to clear L3E */ 820 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 821 do { 822 x = mfspr(SPR_L3CR); 823 } while (x & L3CR_L3I); 824 825 /* 6: Clear L3CLKEN to 0 */ 826 l3cr &= ~L3CR_L3CLKEN; 827 mtspr(SPR_L3CR, l3cr); 828 829 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 830 __asm volatile("sync"); 831 delay(100); 832 833 /* 8: Set L3E and L3CLKEN */ 834 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 835 mtspr(SPR_L3CR, l3cr); 836 837 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 838 __asm volatile("sync"); 839 delay(100); 840 } 841 842 void 843 cpu_config_l2cr(int pvr) 844 { 845 register_t l2cr; 846 u_int vers = (pvr >> 16) & 0xffff; 847 848 l2cr = mfspr(SPR_L2CR); 849 850 /* 851 * For MP systems, the firmware may only configure the L2 cache 852 * on the first CPU. In this case, assume that the other CPUs 853 * should use the same value for L2CR. 854 */ 855 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 856 l2cr_config = l2cr; 857 } 858 859 /* 860 * Configure L2 cache if not enabled. 861 */ 862 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 863 cpu_enable_l2cr(l2cr_config); 864 l2cr = mfspr(SPR_L2CR); 865 } 866 867 if ((l2cr & L2CR_L2E) == 0) { 868 aprint_normal(" L2 cache present but not enabled "); 869 return; 870 } 871 aprint_normal(","); 872 873 switch (vers) { 874 case IBM750FX: 875 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 876 break; 877 case MPC750: 878 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 879 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 880 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 881 else 882 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 883 break; 884 case MPC7447A: 885 case MPC7457: 886 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 887 return; 888 case MPC7448: 889 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 890 return; 891 case MPC7450: 892 case MPC7455: 893 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 894 break; 895 default: 896 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 897 break; 898 } 899 } 900 901 void 902 cpu_config_l3cr(int vers) 903 { 904 register_t l2cr; 905 register_t l3cr; 906 907 l2cr = mfspr(SPR_L2CR); 908 909 /* 910 * For MP systems, the firmware may only configure the L2 cache 911 * on the first CPU. In this case, assume that the other CPUs 912 * should use the same value for L2CR. 913 */ 914 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 915 l2cr_config = l2cr; 916 } 917 918 /* 919 * Configure L2 cache if not enabled. 920 */ 921 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 922 cpu_enable_l2cr(l2cr_config); 923 l2cr = mfspr(SPR_L2CR); 924 } 925 926 aprint_normal(","); 927 switch (vers) { 928 case MPC7447A: 929 case MPC7457: 930 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 931 return; 932 case MPC7448: 933 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 934 return; 935 default: 936 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 937 break; 938 } 939 940 l3cr = mfspr(SPR_L3CR); 941 942 /* 943 * For MP systems, the firmware may only configure the L3 cache 944 * on the first CPU. In this case, assume that the other CPUs 945 * should use the same value for L3CR. 946 */ 947 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 948 l3cr_config = l3cr; 949 } 950 951 /* 952 * Configure L3 cache if not enabled. 953 */ 954 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 955 cpu_enable_l3cr(l3cr_config); 956 l3cr = mfspr(SPR_L3CR); 957 } 958 959 if (l3cr & L3CR_L3E) { 960 aprint_normal(","); 961 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 962 } 963 } 964 965 void 966 cpu_probe_speed(struct cpu_info *ci) 967 { 968 uint64_t cps; 969 970 mtspr(SPR_MMCR0, MMCR0_FC); 971 mtspr(SPR_PMC1, 0); 972 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 973 delay(100000); 974 cps = (mfspr(SPR_PMC1) * 10) + 4999; 975 976 mtspr(SPR_MMCR0, MMCR0_FC); 977 978 ci->ci_khz = cps / 1000; 979 } 980 981 #if NSYSMON_ENVSYS > 0 982 void 983 cpu_tau_setup(struct cpu_info *ci) 984 { 985 struct sysmon_envsys *sme; 986 envsys_data_t sensor; 987 int error; 988 989 sme = sysmon_envsys_create(); 990 991 sensor.state = ENVSYS_SVALID; 992 sensor.units = ENVSYS_STEMP; 993 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 994 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 995 sysmon_envsys_destroy(sme); 996 return; 997 } 998 999 sme->sme_name = ci->ci_dev->dv_xname; 1000 sme->sme_cookie = ci; 1001 sme->sme_refresh = cpu_tau_refresh; 1002 1003 if ((error = sysmon_envsys_register(sme)) != 0) { 1004 aprint_error("%s: unable to register with sysmon (%d)\n", 1005 ci->ci_dev->dv_xname, error); 1006 sysmon_envsys_destroy(sme); 1007 } 1008 } 1009 1010 1011 /* Find the temperature of the CPU. */ 1012 void 1013 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1014 { 1015 int i, threshold, count; 1016 1017 threshold = 64; /* Half of the 7-bit sensor range */ 1018 mtspr(SPR_THRM1, 0); 1019 mtspr(SPR_THRM2, 0); 1020 /* XXX This counter is supposed to be "at least 20 microseonds, in 1021 * XXX units of clock cycles". Since we don't have convenient 1022 * XXX access to the CPU speed, set it to a conservative value, 1023 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 1024 * XXX the fastest G3 processor is 700MHz) . The cost is that 1025 * XXX measuring the temperature takes a bit longer. 1026 */ 1027 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 1028 1029 /* Successive-approximation code adapted from Motorola 1030 * application note AN1800/D, "Programming the Thermal Assist 1031 * Unit in the MPC750 Microprocessor". 1032 */ 1033 for (i = 4; i >= 0 ; i--) { 1034 mtspr(SPR_THRM1, 1035 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1036 count = 0; 1037 while ((count < 100) && 1038 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1039 count++; 1040 delay(1); 1041 } 1042 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1043 /* The interrupt bit was set, meaning the 1044 * temperature was above the threshold 1045 */ 1046 threshold += 2 << i; 1047 } else { 1048 /* Temperature was below the threshold */ 1049 threshold -= 2 << i; 1050 } 1051 } 1052 threshold += 2; 1053 1054 /* Convert the temperature in degrees C to microkelvin */ 1055 edata->value_cur = (threshold * 1000000) + 273150000; 1056 } 1057 #endif /* NSYSMON_ENVSYS > 0 */ 1058 1059 #ifdef MULTIPROCESSOR 1060 extern volatile u_int cpu_spinstart_ack; 1061 1062 int 1063 cpu_spinup(struct device *self, struct cpu_info *ci) 1064 { 1065 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1066 struct pglist mlist; 1067 int i, error, pvr, vers; 1068 char *cp, *hp; 1069 1070 pvr = mfpvr(); 1071 vers = pvr >> 16; 1072 KASSERT(ci != curcpu()); 1073 1074 /* 1075 * Allocate some contiguous pages for the intteup PCB and stack 1076 * from the lowest 256MB (because bat0 always maps it va == pa). 1077 * Must be 16 byte aligned. 1078 */ 1079 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1080 &mlist, 1, 1); 1081 if (error) { 1082 aprint_error(": unable to allocate idle stack\n"); 1083 return -1; 1084 } 1085 1086 KASSERT(ci != &cpu_info[0]); 1087 1088 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1089 memset(cp, 0, INTSTK); 1090 1091 ci->ci_intstk = cp; 1092 1093 /* Now allocate a hatch stack */ 1094 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1095 &mlist, 1, 1); 1096 if (error) { 1097 aprint_error(": unable to allocate hatch stack\n"); 1098 return -1; 1099 } 1100 1101 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1102 memset(hp, 0, 0x1000); 1103 1104 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1105 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1106 ci->ci_curpcb = &ci->ci_curlwp->l_addr->u_pcb; 1107 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1108 1109 cpu_hatch_data = h; 1110 h->running = 0; 1111 h->self = self; 1112 h->ci = ci; 1113 h->pir = ci->ci_cpuid; 1114 1115 cpu_hatch_stack = (uint32_t)hp; 1116 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1117 1118 /* copy special registers */ 1119 1120 h->hid0 = mfspr(SPR_HID0); 1121 1122 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1123 for (i = 0; i < 16; i++) { 1124 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1125 "r"(i << ADDR_SR_SHFT)); 1126 } 1127 if (oeacpufeat & OEACPU_64) 1128 h->asr = mfspr(SPR_ASR); 1129 else 1130 h->asr = 0; 1131 1132 /* copy the bat regs */ 1133 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1134 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1135 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1136 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1137 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1138 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1139 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1140 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1141 __asm volatile ("sync; isync"); 1142 1143 if (md_setup_trampoline(h, ci) == -1) 1144 return -1; 1145 md_presync_timebase(h); 1146 md_start_timebase(h); 1147 1148 /* wait for secondary printf */ 1149 1150 delay(200000); 1151 1152 if (h->running < 1) { 1153 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1154 ci->ci_cpuid, cpu_spinstart_ack); 1155 Debugger(); 1156 return -1; 1157 } 1158 1159 /* Register IPI Interrupt */ 1160 if (ipiops.ppc_establish_ipi) 1161 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1162 1163 return 0; 1164 } 1165 1166 static volatile int start_secondary_cpu; 1167 extern void tlbia(void); 1168 1169 register_t 1170 cpu_hatch(void) 1171 { 1172 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1173 struct cpu_info * const ci = h->ci; 1174 u_int msr; 1175 int i; 1176 1177 /* Initialize timebase. */ 1178 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1179 1180 /* 1181 * Set PIR (Processor Identification Register). i.e. whoami 1182 * Note that PIR is read-only on some CPU's. Try to work around 1183 * that as best as possible. Assume that if it is 0, it is meant 1184 * to be setup by us. 1185 */ 1186 1187 msr = mfspr(SPR_PIR); 1188 if (msr == 0) 1189 mtspr(SPR_PIR, h->pir); 1190 1191 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1192 cpu_spinstart_ack = 0; 1193 1194 /* Initialize MMU. */ 1195 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1196 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1197 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1198 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1199 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1200 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1201 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1202 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1203 1204 mtspr(SPR_HID0, h->hid0); 1205 1206 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1207 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1208 1209 __asm volatile ("sync"); 1210 for (i = 0; i < 16; i++) 1211 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1212 __asm volatile ("sync; isync"); 1213 1214 if (oeacpufeat & OEACPU_64) 1215 mtspr(SPR_ASR, h->asr); 1216 1217 cpu_spinstart_ack = 1; 1218 __asm ("ptesync"); 1219 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1220 __asm volatile ("sync; isync"); 1221 1222 cpu_spinstart_ack = 5; 1223 for (i = 0; i < 16; i++) 1224 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1225 "r"(i << ADDR_SR_SHFT)); 1226 1227 /* Enable I/D address translations. */ 1228 msr = mfmsr(); 1229 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1230 mtmsr(msr); 1231 __asm volatile ("sync; isync"); 1232 cpu_spinstart_ack = 2; 1233 1234 md_sync_timebase(h); 1235 1236 cpu_setup(h->self, ci); 1237 1238 h->running = 1; 1239 __asm volatile ("sync; isync"); 1240 1241 while (start_secondary_cpu == 0) 1242 ; 1243 1244 __asm volatile ("sync; isync"); 1245 1246 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1247 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1248 1249 md_setup_interrupts(); 1250 1251 ci->ci_ipending = 0; 1252 ci->ci_cpl = 0; 1253 1254 mtmsr(mfmsr() | PSL_EE); 1255 return ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp; 1256 } 1257 1258 void 1259 cpu_boot_secondary_processors() 1260 { 1261 start_secondary_cpu = 1; 1262 __asm volatile ("sync"); 1263 } 1264 1265 #endif /*MULTIPROCESSOR*/ 1266