1 /* $NetBSD: cpu_subr.c,v 1.80 2013/11/03 22:27:27 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.80 2013/11/03 22:27:27 mrg Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't realy matter since none of them supports SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 #define HATCH_STACK_SIZE 0x1000 241 extern int ticks_per_intr; 242 #include <powerpc/oea/bat.h> 243 #include <powerpc/pic/picvar.h> 244 #include <powerpc/pic/ipivar.h> 245 extern struct bat battable[]; 246 #else 247 struct cpu_info cpu_info[1] = { 248 [0] = { 249 .ci_curlwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 register_t cpu_psluserset; 256 register_t cpu_pslusermod; 257 register_t cpu_pslusermask = 0xffff; 258 char cpu_model[80]; 259 260 /* This is to be called from locore.S, and nowhere else. */ 261 262 void 263 cpu_model_init(void) 264 { 265 u_int pvr, vers; 266 267 pvr = mfpvr(); 268 vers = pvr >> 16; 269 270 oeacpufeat = 0; 271 272 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 273 vers == IBMCELL || vers == IBMPOWER6P5) { 274 oeacpufeat |= OEACPU_64; 275 oeacpufeat |= OEACPU_64_BRIDGE; 276 oeacpufeat |= OEACPU_NOBAT; 277 278 } else if (vers == MPC601) { 279 oeacpufeat |= OEACPU_601; 280 281 } else if (MPC745X_P(vers)) { 282 register_t hid1 = mfspr(SPR_HID1); 283 284 if (vers != MPC7450) { 285 register_t hid0 = mfspr(SPR_HID0); 286 287 /* Enable more SPRG registers */ 288 oeacpufeat |= OEACPU_HIGHSPRG; 289 290 /* Enable more BAT registers */ 291 oeacpufeat |= OEACPU_HIGHBAT; 292 hid0 |= HID0_HIGH_BAT_EN; 293 294 /* Enable larger BAT registers */ 295 oeacpufeat |= OEACPU_XBSEN; 296 hid0 |= HID0_XBSEN; 297 298 mtspr(SPR_HID0, hid0); 299 __asm volatile("sync;isync"); 300 } 301 302 /* Enable address broadcasting for MP systems */ 303 hid1 |= HID1_SYNCBE | HID1_ABE; 304 305 mtspr(SPR_HID1, hid1); 306 __asm volatile("sync;isync"); 307 308 } else if (vers == IBM750FX || vers == IBM750GX) { 309 oeacpufeat |= OEACPU_HIGHBAT; 310 } 311 } 312 313 void 314 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 315 { 316 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 317 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 318 (data & fmt->fmt_mask) == fmt->fmt_value) 319 aprint_normal("%s", fmt->fmt_string); 320 } 321 } 322 323 void 324 cpu_idlespin(void) 325 { 326 register_t msr; 327 328 if (powersave <= 0) 329 return; 330 331 __asm volatile( 332 "sync;" 333 "mfmsr %0;" 334 "oris %0,%0,%1@h;" /* enter power saving mode */ 335 "mtmsr %0;" 336 "isync;" 337 : "=r"(msr) 338 : "J"(PSL_POW)); 339 } 340 341 void 342 cpu_probe_cache(void) 343 { 344 u_int assoc, pvr, vers; 345 346 pvr = mfpvr(); 347 vers = pvr >> 16; 348 349 350 /* Presently common across almost all implementations. */ 351 curcpu()->ci_ci.dcache_line_size = 32; 352 curcpu()->ci_ci.icache_line_size = 32; 353 354 355 switch (vers) { 356 #define K *1024 357 case IBM750FX: 358 case IBM750GX: 359 case MPC601: 360 case MPC750: 361 case MPC7400: 362 case MPC7447A: 363 case MPC7448: 364 case MPC7450: 365 case MPC7455: 366 case MPC7457: 367 curcpu()->ci_ci.dcache_size = 32 K; 368 curcpu()->ci_ci.icache_size = 32 K; 369 assoc = 8; 370 break; 371 case MPC603: 372 curcpu()->ci_ci.dcache_size = 8 K; 373 curcpu()->ci_ci.icache_size = 8 K; 374 assoc = 2; 375 break; 376 case MPC603e: 377 case MPC603ev: 378 case MPC604: 379 case MPC8240: 380 case MPC8245: 381 case MPCG2: 382 curcpu()->ci_ci.dcache_size = 16 K; 383 curcpu()->ci_ci.icache_size = 16 K; 384 assoc = 4; 385 break; 386 case MPC604e: 387 case MPC604ev: 388 curcpu()->ci_ci.dcache_size = 32 K; 389 curcpu()->ci_ci.icache_size = 32 K; 390 assoc = 4; 391 break; 392 case IBMPOWER3II: 393 curcpu()->ci_ci.dcache_size = 64 K; 394 curcpu()->ci_ci.icache_size = 32 K; 395 curcpu()->ci_ci.dcache_line_size = 128; 396 curcpu()->ci_ci.icache_line_size = 128; 397 assoc = 128; /* not a typo */ 398 break; 399 case IBM970: 400 case IBM970FX: 401 case IBM970MP: 402 curcpu()->ci_ci.dcache_size = 32 K; 403 curcpu()->ci_ci.icache_size = 64 K; 404 curcpu()->ci_ci.dcache_line_size = 128; 405 curcpu()->ci_ci.icache_line_size = 128; 406 assoc = 2; 407 break; 408 409 default: 410 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 411 curcpu()->ci_ci.icache_size = PAGE_SIZE; 412 assoc = 1; 413 #undef K 414 } 415 416 /* 417 * Possibly recolor. 418 */ 419 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 420 } 421 422 struct cpu_info * 423 cpu_attach_common(device_t self, int id) 424 { 425 struct cpu_info *ci; 426 u_int pvr, vers; 427 428 ci = &cpu_info[id]; 429 #ifndef MULTIPROCESSOR 430 /* 431 * If this isn't the primary CPU, print an error message 432 * and just bail out. 433 */ 434 if (id != 0) { 435 aprint_naive("\n"); 436 aprint_normal(": ID %d\n", id); 437 aprint_normal_dev(self, 438 "processor off-line; " 439 "multiprocessor support not present in kernel\n"); 440 return (NULL); 441 } 442 #endif 443 444 ci->ci_cpuid = id; 445 ci->ci_idepth = -1; 446 ci->ci_dev = self; 447 ci->ci_idlespin = cpu_idlespin; 448 449 pvr = mfpvr(); 450 vers = (pvr >> 16) & 0xffff; 451 452 switch (id) { 453 case 0: 454 /* load my cpu_number to PIR */ 455 switch (vers) { 456 case MPC601: 457 case MPC604: 458 case MPC604e: 459 case MPC604ev: 460 case MPC7400: 461 case MPC7410: 462 case MPC7447A: 463 case MPC7448: 464 case MPC7450: 465 case MPC7455: 466 case MPC7457: 467 mtspr(SPR_PIR, id); 468 } 469 cpu_setup(self, ci); 470 break; 471 default: 472 aprint_naive("\n"); 473 if (id >= CPU_MAXNUM) { 474 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 475 panic("cpuattach"); 476 } 477 #ifndef MULTIPROCESSOR 478 aprint_normal(" not configured\n"); 479 return NULL; 480 #else 481 mi_cpu_attach(ci); 482 break; 483 #endif 484 } 485 return (ci); 486 } 487 488 void 489 cpu_setup(device_t self, struct cpu_info *ci) 490 { 491 u_int hid0, hid0_save, pvr, vers; 492 const char * const xname = device_xname(self); 493 const char *bitmask; 494 char hidbuf[128]; 495 char model[80]; 496 497 pvr = mfpvr(); 498 vers = (pvr >> 16) & 0xffff; 499 500 cpu_identify(model, sizeof(model)); 501 aprint_naive("\n"); 502 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 503 cpu_number() == 0 ? " (primary)" : ""); 504 505 /* set the cpu number */ 506 ci->ci_cpuid = cpu_number(); 507 hid0_save = hid0 = mfspr(SPR_HID0); 508 509 cpu_probe_cache(); 510 511 /* 512 * Configure power-saving mode. 513 */ 514 switch (vers) { 515 case MPC604: 516 case MPC604e: 517 case MPC604ev: 518 /* 519 * Do not have HID0 support settings, but can support 520 * MSR[POW] off 521 */ 522 powersave = 1; 523 break; 524 525 case MPC603: 526 case MPC603e: 527 case MPC603ev: 528 case MPC7400: 529 case MPC7410: 530 case MPC8240: 531 case MPC8245: 532 case MPCG2: 533 /* Select DOZE mode. */ 534 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 535 hid0 |= HID0_DOZE | HID0_DPM; 536 powersave = 1; 537 break; 538 539 case MPC750: 540 case IBM750FX: 541 case IBM750GX: 542 /* Select NAP mode. */ 543 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 544 hid0 |= HID0_NAP | HID0_DPM; 545 powersave = 1; 546 break; 547 548 case MPC7447A: 549 case MPC7448: 550 case MPC7457: 551 case MPC7455: 552 case MPC7450: 553 /* Enable the 7450 branch caches */ 554 hid0 |= HID0_SGE | HID0_BTIC; 555 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 556 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 557 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 558 hid0 &= ~HID0_BTIC; 559 /* Select NAP mode. */ 560 hid0 &= ~HID0_SLEEP; 561 hid0 |= HID0_NAP | HID0_DPM; 562 powersave = 1; 563 break; 564 565 case IBM970: 566 case IBM970FX: 567 case IBM970MP: 568 case IBMPOWER3II: 569 default: 570 /* No power-saving mode is available. */ ; 571 } 572 573 #ifdef NAPMODE 574 switch (vers) { 575 case IBM750FX: 576 case IBM750GX: 577 case MPC750: 578 case MPC7400: 579 /* Select NAP mode. */ 580 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 581 hid0 |= HID0_NAP; 582 break; 583 } 584 #endif 585 586 switch (vers) { 587 case IBM750FX: 588 case IBM750GX: 589 case MPC750: 590 hid0 &= ~HID0_DBP; /* XXX correct? */ 591 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 592 break; 593 594 case MPC7400: 595 case MPC7410: 596 hid0 &= ~HID0_SPD; 597 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 598 hid0 |= HID0_EIEC; 599 break; 600 } 601 602 #ifdef MULTIPROCESSOR 603 switch (vers) { 604 case MPC603e: 605 hid0 |= HID0_ABE; 606 } 607 #endif 608 609 if (hid0 != hid0_save) { 610 mtspr(SPR_HID0, hid0); 611 __asm volatile("sync;isync"); 612 } 613 614 615 switch (vers) { 616 case MPC601: 617 bitmask = HID0_601_BITMASK; 618 break; 619 case MPC7450: 620 case MPC7455: 621 case MPC7457: 622 bitmask = HID0_7450_BITMASK; 623 break; 624 case IBM970: 625 case IBM970FX: 626 case IBM970MP: 627 bitmask = 0; 628 break; 629 default: 630 bitmask = HID0_BITMASK; 631 break; 632 } 633 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 634 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 635 636 ci->ci_khz = 0; 637 638 /* 639 * Display speed and cache configuration. 640 */ 641 switch (vers) { 642 case MPC604: 643 case MPC604e: 644 case MPC604ev: 645 case MPC750: 646 case IBM750FX: 647 case IBM750GX: 648 case MPC7400: 649 case MPC7410: 650 case MPC7447A: 651 case MPC7448: 652 case MPC7450: 653 case MPC7455: 654 case MPC7457: 655 aprint_normal_dev(self, ""); 656 cpu_probe_speed(ci); 657 aprint_normal("%u.%02u MHz", 658 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 659 switch (vers) { 660 case MPC7450: /* 7441 does not have L3! */ 661 case MPC7455: /* 7445 does not have L3! */ 662 case MPC7457: /* 7447 does not have L3! */ 663 cpu_config_l3cr(vers); 664 break; 665 case IBM750FX: 666 case IBM750GX: 667 case MPC750: 668 case MPC7400: 669 case MPC7410: 670 case MPC7447A: 671 case MPC7448: 672 cpu_config_l2cr(pvr); 673 break; 674 default: 675 break; 676 } 677 aprint_normal("\n"); 678 break; 679 } 680 681 #if NSYSMON_ENVSYS > 0 682 /* 683 * Attach MPC750 temperature sensor to the envsys subsystem. 684 * XXX the 74xx series also has this sensor, but it is not 685 * XXX supported by Motorola and may return values that are off by 686 * XXX 35-55 degrees C. 687 */ 688 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 689 cpu_tau_setup(ci); 690 #endif 691 692 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 693 NULL, xname, "clock"); 694 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 695 NULL, xname, "traps"); 696 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 697 &ci->ci_ev_traps, xname, "kernel DSI traps"); 698 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 699 &ci->ci_ev_traps, xname, "user DSI traps"); 700 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 701 &ci->ci_ev_udsi, xname, "user DSI failures"); 702 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 703 &ci->ci_ev_traps, xname, "kernel ISI traps"); 704 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 705 &ci->ci_ev_traps, xname, "user ISI traps"); 706 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 707 &ci->ci_ev_isi, xname, "user ISI failures"); 708 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 709 &ci->ci_ev_traps, xname, "system call traps"); 710 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 711 &ci->ci_ev_traps, xname, "PGM traps"); 712 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 713 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 714 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 715 &ci->ci_ev_fpu, xname, "FPU context switches"); 716 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 717 &ci->ci_ev_traps, xname, "user alignment traps"); 718 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 719 &ci->ci_ev_ali, xname, "user alignment traps"); 720 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 721 &ci->ci_ev_umchk, xname, "user MCHK failures"); 722 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 723 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 724 #ifdef ALTIVEC 725 if (cpu_altivec) { 726 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 727 &ci->ci_ev_vec, xname, "AltiVec context switches"); 728 } 729 #endif 730 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 731 NULL, xname, "IPIs"); 732 } 733 734 /* 735 * According to a document labeled "PVR Register Settings": 736 ** For integrated microprocessors the PVR register inside the device 737 ** will identify the version of the microprocessor core. You must also 738 ** read the Device ID, PCI register 02, to identify the part and the 739 ** Revision ID, PCI register 08, to identify the revision of the 740 ** integrated microprocessor. 741 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 742 */ 743 744 void 745 cpu_identify(char *str, size_t len) 746 { 747 u_int pvr, major, minor; 748 uint16_t vers, rev, revfmt; 749 const struct cputab *cp; 750 size_t n; 751 752 pvr = mfpvr(); 753 vers = pvr >> 16; 754 rev = pvr; 755 756 switch (vers) { 757 case MPC7410: 758 minor = (pvr >> 0) & 0xff; 759 major = minor <= 4 ? 1 : 2; 760 break; 761 case MPCG2: /*XXX see note above */ 762 major = (pvr >> 4) & 0xf; 763 minor = (pvr >> 0) & 0xf; 764 break; 765 default: 766 major = (pvr >> 8) & 0xf; 767 minor = (pvr >> 0) & 0xf; 768 } 769 770 for (cp = models; cp->name[0] != '\0'; cp++) { 771 if (cp->version == vers) 772 break; 773 } 774 775 if (str == NULL) { 776 str = cpu_model; 777 len = sizeof(cpu_model); 778 cpu = vers; 779 } 780 781 revfmt = cp->revfmt; 782 if (rev == MPC750 && pvr == 15) { 783 revfmt = REVFMT_HEX; 784 } 785 786 if (cp->name[0] != '\0') { 787 n = snprintf(str, len, "%s (Revision ", cp->name); 788 } else { 789 n = snprintf(str, len, "Version %#x (Revision ", vers); 790 } 791 if (len > n) { 792 switch (revfmt) { 793 case REVFMT_MAJMIN: 794 snprintf(str + n, len - n, "%u.%u)", major, minor); 795 break; 796 case REVFMT_HEX: 797 snprintf(str + n, len - n, "0x%04x)", rev); 798 break; 799 case REVFMT_DEC: 800 snprintf(str + n, len - n, "%u)", rev); 801 break; 802 } 803 } 804 } 805 806 #ifdef L2CR_CONFIG 807 u_int l2cr_config = L2CR_CONFIG; 808 #else 809 u_int l2cr_config = 0; 810 #endif 811 812 #ifdef L3CR_CONFIG 813 u_int l3cr_config = L3CR_CONFIG; 814 #else 815 u_int l3cr_config = 0; 816 #endif 817 818 void 819 cpu_enable_l2cr(register_t l2cr) 820 { 821 register_t msr, x; 822 uint16_t vers; 823 824 vers = mfpvr() >> 16; 825 826 /* Disable interrupts and set the cache config bits. */ 827 msr = mfmsr(); 828 mtmsr(msr & ~PSL_EE); 829 #ifdef ALTIVEC 830 if (cpu_altivec) 831 __asm volatile("dssall"); 832 #endif 833 __asm volatile("sync"); 834 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 835 __asm volatile("sync"); 836 837 /* Wait for L2 clock to be stable (640 L2 clocks). */ 838 delay(100); 839 840 /* Invalidate all L2 contents. */ 841 if (MPC745X_P(vers)) { 842 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 843 do { 844 x = mfspr(SPR_L2CR); 845 } while (x & L2CR_L2I); 846 } else { 847 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 848 do { 849 x = mfspr(SPR_L2CR); 850 } while (x & L2CR_L2IP); 851 } 852 /* Enable L2 cache. */ 853 l2cr |= L2CR_L2E; 854 mtspr(SPR_L2CR, l2cr); 855 mtmsr(msr); 856 } 857 858 void 859 cpu_enable_l3cr(register_t l3cr) 860 { 861 register_t x; 862 863 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 864 865 /* 866 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 867 * L3CLKEN. (also mask off reserved bits in case they were included 868 * in L3CR_CONFIG) 869 */ 870 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 871 mtspr(SPR_L3CR, l3cr); 872 873 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 874 l3cr |= 0x04000000; 875 mtspr(SPR_L3CR, l3cr); 876 877 /* 3: Set L3CLKEN to 1*/ 878 l3cr |= L3CR_L3CLKEN; 879 mtspr(SPR_L3CR, l3cr); 880 881 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 882 __asm volatile("dssall;sync"); 883 /* L3 cache is already disabled, no need to clear L3E */ 884 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 885 do { 886 x = mfspr(SPR_L3CR); 887 } while (x & L3CR_L3I); 888 889 /* 6: Clear L3CLKEN to 0 */ 890 l3cr &= ~L3CR_L3CLKEN; 891 mtspr(SPR_L3CR, l3cr); 892 893 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 894 __asm volatile("sync"); 895 delay(100); 896 897 /* 8: Set L3E and L3CLKEN */ 898 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 899 mtspr(SPR_L3CR, l3cr); 900 901 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 902 __asm volatile("sync"); 903 delay(100); 904 } 905 906 void 907 cpu_config_l2cr(int pvr) 908 { 909 register_t l2cr; 910 u_int vers = (pvr >> 16) & 0xffff; 911 912 l2cr = mfspr(SPR_L2CR); 913 914 /* 915 * For MP systems, the firmware may only configure the L2 cache 916 * on the first CPU. In this case, assume that the other CPUs 917 * should use the same value for L2CR. 918 */ 919 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 920 l2cr_config = l2cr; 921 } 922 923 /* 924 * Configure L2 cache if not enabled. 925 */ 926 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 927 cpu_enable_l2cr(l2cr_config); 928 l2cr = mfspr(SPR_L2CR); 929 } 930 931 if ((l2cr & L2CR_L2E) == 0) { 932 aprint_normal(" L2 cache present but not enabled "); 933 return; 934 } 935 aprint_normal(","); 936 937 switch (vers) { 938 case IBM750FX: 939 case IBM750GX: 940 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 941 break; 942 case MPC750: 943 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 944 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 945 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 946 else 947 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 948 break; 949 case MPC7447A: 950 case MPC7457: 951 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 952 return; 953 case MPC7448: 954 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 955 return; 956 case MPC7450: 957 case MPC7455: 958 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 959 break; 960 default: 961 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 962 break; 963 } 964 } 965 966 void 967 cpu_config_l3cr(int vers) 968 { 969 register_t l2cr; 970 register_t l3cr; 971 972 l2cr = mfspr(SPR_L2CR); 973 974 /* 975 * For MP systems, the firmware may only configure the L2 cache 976 * on the first CPU. In this case, assume that the other CPUs 977 * should use the same value for L2CR. 978 */ 979 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 980 l2cr_config = l2cr; 981 } 982 983 /* 984 * Configure L2 cache if not enabled. 985 */ 986 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 987 cpu_enable_l2cr(l2cr_config); 988 l2cr = mfspr(SPR_L2CR); 989 } 990 991 aprint_normal(","); 992 switch (vers) { 993 case MPC7447A: 994 case MPC7457: 995 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 996 return; 997 case MPC7448: 998 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 999 return; 1000 default: 1001 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1002 break; 1003 } 1004 1005 l3cr = mfspr(SPR_L3CR); 1006 1007 /* 1008 * For MP systems, the firmware may only configure the L3 cache 1009 * on the first CPU. In this case, assume that the other CPUs 1010 * should use the same value for L3CR. 1011 */ 1012 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1013 l3cr_config = l3cr; 1014 } 1015 1016 /* 1017 * Configure L3 cache if not enabled. 1018 */ 1019 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1020 cpu_enable_l3cr(l3cr_config); 1021 l3cr = mfspr(SPR_L3CR); 1022 } 1023 1024 if (l3cr & L3CR_L3E) { 1025 aprint_normal(","); 1026 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1027 } 1028 } 1029 1030 void 1031 cpu_probe_speed(struct cpu_info *ci) 1032 { 1033 uint64_t cps; 1034 1035 mtspr(SPR_MMCR0, MMCR0_FC); 1036 mtspr(SPR_PMC1, 0); 1037 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1038 delay(100000); 1039 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1040 1041 mtspr(SPR_MMCR0, MMCR0_FC); 1042 1043 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1044 } 1045 1046 /* 1047 * Read the Dynamic Frequency Switching state and return a divisor for 1048 * the maximum frequency. 1049 */ 1050 int 1051 cpu_get_dfs(void) 1052 { 1053 u_int pvr, vers; 1054 1055 pvr = mfpvr(); 1056 vers = pvr >> 16; 1057 1058 switch (vers) { 1059 case MPC7448: 1060 if (mfspr(SPR_HID1) & HID1_DFS4) 1061 return 4; 1062 case MPC7447A: 1063 if (mfspr(SPR_HID1) & HID1_DFS2) 1064 return 2; 1065 } 1066 return 1; 1067 } 1068 1069 /* 1070 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1071 */ 1072 void 1073 cpu_set_dfs(int div) 1074 { 1075 uint64_t where; 1076 u_int dfs_mask, pvr, vers; 1077 1078 pvr = mfpvr(); 1079 vers = pvr >> 16; 1080 dfs_mask = 0; 1081 1082 switch (vers) { 1083 case MPC7448: 1084 dfs_mask |= HID1_DFS4; 1085 case MPC7447A: 1086 dfs_mask |= HID1_DFS2; 1087 break; 1088 default: 1089 printf("cpu_set_dfs: DFS not supported\n"); 1090 return; 1091 1092 } 1093 1094 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1095 xc_wait(where); 1096 } 1097 1098 static void 1099 cpu_set_dfs_xcall(void *arg1, void *arg2) 1100 { 1101 u_int dfs_mask, hid1, old_hid1; 1102 int *divisor, s; 1103 1104 divisor = arg1; 1105 dfs_mask = *(u_int *)arg2; 1106 1107 s = splhigh(); 1108 hid1 = old_hid1 = mfspr(SPR_HID1); 1109 1110 switch (*divisor) { 1111 case 1: 1112 hid1 &= ~dfs_mask; 1113 break; 1114 case 2: 1115 hid1 &= ~(dfs_mask & HID1_DFS4); 1116 hid1 |= dfs_mask & HID1_DFS2; 1117 break; 1118 case 4: 1119 hid1 &= ~(dfs_mask & HID1_DFS2); 1120 hid1 |= dfs_mask & HID1_DFS4; 1121 break; 1122 } 1123 1124 if (hid1 != old_hid1) { 1125 __asm volatile("sync"); 1126 mtspr(SPR_HID1, hid1); 1127 __asm volatile("sync;isync"); 1128 } 1129 1130 splx(s); 1131 } 1132 1133 #if NSYSMON_ENVSYS > 0 1134 void 1135 cpu_tau_setup(struct cpu_info *ci) 1136 { 1137 struct sysmon_envsys *sme; 1138 int error, therm_delay; 1139 1140 mtspr(SPR_THRM1, SPR_THRM_VALID); 1141 mtspr(SPR_THRM2, 0); 1142 1143 /* 1144 * we need to figure out how much 20+us in units of CPU clock cycles 1145 * are 1146 */ 1147 1148 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1149 1150 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1151 1152 sme = sysmon_envsys_create(); 1153 1154 sensor.units = ENVSYS_STEMP; 1155 sensor.state = ENVSYS_SINVALID; 1156 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1157 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1158 sysmon_envsys_destroy(sme); 1159 return; 1160 } 1161 1162 sme->sme_name = device_xname(ci->ci_dev); 1163 sme->sme_cookie = ci; 1164 sme->sme_refresh = cpu_tau_refresh; 1165 1166 if ((error = sysmon_envsys_register(sme)) != 0) { 1167 aprint_error_dev(ci->ci_dev, 1168 " unable to register with sysmon (%d)\n", error); 1169 sysmon_envsys_destroy(sme); 1170 } 1171 } 1172 1173 1174 /* Find the temperature of the CPU. */ 1175 void 1176 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1177 { 1178 int i, threshold, count; 1179 1180 threshold = 64; /* Half of the 7-bit sensor range */ 1181 1182 /* Successive-approximation code adapted from Motorola 1183 * application note AN1800/D, "Programming the Thermal Assist 1184 * Unit in the MPC750 Microprocessor". 1185 */ 1186 for (i = 5; i >= 0 ; i--) { 1187 mtspr(SPR_THRM1, 1188 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1189 count = 0; 1190 while ((count < 100000) && 1191 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1192 count++; 1193 delay(1); 1194 } 1195 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1196 /* The interrupt bit was set, meaning the 1197 * temperature was above the threshold 1198 */ 1199 threshold += 1 << i; 1200 } else { 1201 /* Temperature was below the threshold */ 1202 threshold -= 1 << i; 1203 } 1204 } 1205 threshold += 2; 1206 1207 /* Convert the temperature in degrees C to microkelvin */ 1208 edata->value_cur = (threshold * 1000000) + 273150000; 1209 edata->state = ENVSYS_SVALID; 1210 } 1211 #endif /* NSYSMON_ENVSYS > 0 */ 1212 1213 #ifdef MULTIPROCESSOR 1214 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1215 1216 int 1217 cpu_spinup(device_t self, struct cpu_info *ci) 1218 { 1219 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1220 struct pglist mlist; 1221 int i, error, pvr, vers; 1222 char *hp; 1223 1224 pvr = mfpvr(); 1225 vers = pvr >> 16; 1226 KASSERT(ci != curcpu()); 1227 1228 /* Now allocate a hatch stack */ 1229 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1230 &mlist, 1, 1); 1231 if (error) { 1232 aprint_error(": unable to allocate hatch stack\n"); 1233 return -1; 1234 } 1235 1236 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1237 memset(hp, 0, HATCH_STACK_SIZE); 1238 1239 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1240 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1241 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1242 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1243 1244 cpu_hatch_data = h; 1245 h->hatch_running = 0; 1246 h->hatch_self = self; 1247 h->hatch_ci = ci; 1248 h->hatch_pir = ci->ci_cpuid; 1249 1250 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1251 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1252 1253 /* copy special registers */ 1254 1255 h->hatch_hid0 = mfspr(SPR_HID0); 1256 1257 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1258 for (i = 0; i < 16; i++) { 1259 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1260 "r"(i << ADDR_SR_SHFT)); 1261 } 1262 if (oeacpufeat & OEACPU_64) 1263 h->hatch_asr = mfspr(SPR_ASR); 1264 else 1265 h->hatch_asr = 0; 1266 1267 /* copy the bat regs */ 1268 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1269 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1270 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1271 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1272 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1273 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1274 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1275 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1276 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1277 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1278 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1279 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1280 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1281 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1282 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1283 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1284 __asm volatile ("sync; isync"); 1285 1286 if (md_setup_trampoline(h, ci) == -1) 1287 return -1; 1288 md_presync_timebase(h); 1289 md_start_timebase(h); 1290 1291 /* wait for secondary printf */ 1292 1293 delay(200000); 1294 1295 #ifdef CACHE_PROTO_MEI 1296 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1297 __asm volatile ("sync; isync"); 1298 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1299 __asm volatile ("sync; isync"); 1300 #endif 1301 if (h->hatch_running < 1) { 1302 #ifdef CACHE_PROTO_MEI 1303 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1304 __asm volatile ("sync; isync"); 1305 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1306 __asm volatile ("sync; isync"); 1307 #endif 1308 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1309 ci->ci_cpuid, cpu_spinstart_ack); 1310 Debugger(); 1311 return -1; 1312 } 1313 1314 /* Register IPI Interrupt */ 1315 if (ipiops.ppc_establish_ipi) 1316 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1317 1318 return 0; 1319 } 1320 1321 static volatile int start_secondary_cpu; 1322 1323 register_t 1324 cpu_hatch(void) 1325 { 1326 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1327 struct cpu_info * const ci = h->hatch_ci; 1328 struct pcb *pcb; 1329 u_int msr; 1330 int i; 1331 1332 /* Initialize timebase. */ 1333 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1334 1335 /* 1336 * Set PIR (Processor Identification Register). i.e. whoami 1337 * Note that PIR is read-only on some CPU versions, so we write to it 1338 * only if it has a different value than we need. 1339 */ 1340 1341 msr = mfspr(SPR_PIR); 1342 if (msr != h->hatch_pir) 1343 mtspr(SPR_PIR, h->hatch_pir); 1344 1345 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1346 curlwp = ci->ci_curlwp; 1347 cpu_spinstart_ack = 0; 1348 1349 /* Initialize MMU. */ 1350 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1351 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1352 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1353 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1354 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1355 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1356 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1357 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1358 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1359 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1360 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1361 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1362 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1363 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1364 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1365 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1366 1367 mtspr(SPR_HID0, h->hatch_hid0); 1368 1369 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1370 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1371 1372 __asm volatile ("sync"); 1373 for (i = 0; i < 16; i++) 1374 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1375 __asm volatile ("sync; isync"); 1376 1377 if (oeacpufeat & OEACPU_64) 1378 mtspr(SPR_ASR, h->hatch_asr); 1379 1380 cpu_spinstart_ack = 1; 1381 __asm ("ptesync"); 1382 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1383 __asm volatile ("sync; isync"); 1384 1385 cpu_spinstart_ack = 5; 1386 for (i = 0; i < 16; i++) 1387 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1388 "r"(i << ADDR_SR_SHFT)); 1389 1390 /* Enable I/D address translations. */ 1391 msr = mfmsr(); 1392 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1393 mtmsr(msr); 1394 __asm volatile ("sync; isync"); 1395 cpu_spinstart_ack = 2; 1396 1397 md_sync_timebase(h); 1398 1399 cpu_setup(h->hatch_self, ci); 1400 1401 h->hatch_running = 1; 1402 __asm volatile ("sync; isync"); 1403 1404 while (start_secondary_cpu == 0) 1405 ; 1406 1407 __asm volatile ("sync; isync"); 1408 1409 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1410 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1411 1412 md_setup_interrupts(); 1413 1414 ci->ci_ipending = 0; 1415 ci->ci_cpl = 0; 1416 1417 mtmsr(mfmsr() | PSL_EE); 1418 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1419 return pcb->pcb_sp; 1420 } 1421 1422 void 1423 cpu_boot_secondary_processors(void) 1424 { 1425 start_secondary_cpu = 1; 1426 __asm volatile ("sync"); 1427 } 1428 1429 #endif /*MULTIPROCESSOR*/ 1430