1 /* $NetBSD: cpu_subr.c,v 1.68 2011/06/20 16:31:28 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.68 2011/06/20 16:31:28 pgoyette Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/malloc.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't realy matter since none of them supports SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 extern int ticks_per_intr; 241 #include <powerpc/oea/bat.h> 242 #include <powerpc/pic/picvar.h> 243 #include <powerpc/pic/ipivar.h> 244 extern struct bat battable[]; 245 #else 246 struct cpu_info cpu_info[1] = { 247 [0] = { 248 .ci_curlwp = &lwp0, 249 }, 250 }; 251 #endif /*MULTIPROCESSOR*/ 252 253 int cpu_altivec; 254 register_t cpu_psluserset; 255 register_t cpu_pslusermod; 256 register_t cpu_pslusermask = 0xffff; 257 char cpu_model[80]; 258 259 /* This is to be called from locore.S, and nowhere else. */ 260 261 void 262 cpu_model_init(void) 263 { 264 u_int pvr, vers; 265 266 pvr = mfpvr(); 267 vers = pvr >> 16; 268 269 oeacpufeat = 0; 270 271 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 272 vers == IBMCELL || vers == IBMPOWER6P5) 273 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 274 275 else if (vers == MPC601) 276 oeacpufeat |= OEACPU_601; 277 278 else if (MPC745X_P(vers) && vers != MPC7450) 279 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 280 281 else if (vers == IBM750FX || vers == IBM750GX) 282 oeacpufeat |= OEACPU_HIGHBAT; 283 } 284 285 void 286 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 287 { 288 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 289 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 290 (data & fmt->fmt_mask) == fmt->fmt_value) 291 aprint_normal("%s", fmt->fmt_string); 292 } 293 } 294 295 void 296 cpu_idlespin(void) 297 { 298 register_t msr; 299 300 if (powersave <= 0) 301 return; 302 303 __asm volatile( 304 "sync;" 305 "mfmsr %0;" 306 "oris %0,%0,%1@h;" /* enter power saving mode */ 307 "mtmsr %0;" 308 "isync;" 309 : "=r"(msr) 310 : "J"(PSL_POW)); 311 } 312 313 void 314 cpu_probe_cache(void) 315 { 316 u_int assoc, pvr, vers; 317 318 pvr = mfpvr(); 319 vers = pvr >> 16; 320 321 322 /* Presently common across almost all implementations. */ 323 curcpu()->ci_ci.dcache_line_size = 32; 324 curcpu()->ci_ci.icache_line_size = 32; 325 326 327 switch (vers) { 328 #define K *1024 329 case IBM750FX: 330 case IBM750GX: 331 case MPC601: 332 case MPC750: 333 case MPC7400: 334 case MPC7447A: 335 case MPC7448: 336 case MPC7450: 337 case MPC7455: 338 case MPC7457: 339 curcpu()->ci_ci.dcache_size = 32 K; 340 curcpu()->ci_ci.icache_size = 32 K; 341 assoc = 8; 342 break; 343 case MPC603: 344 curcpu()->ci_ci.dcache_size = 8 K; 345 curcpu()->ci_ci.icache_size = 8 K; 346 assoc = 2; 347 break; 348 case MPC603e: 349 case MPC603ev: 350 case MPC604: 351 case MPC8240: 352 case MPC8245: 353 case MPCG2: 354 curcpu()->ci_ci.dcache_size = 16 K; 355 curcpu()->ci_ci.icache_size = 16 K; 356 assoc = 4; 357 break; 358 case MPC604e: 359 case MPC604ev: 360 curcpu()->ci_ci.dcache_size = 32 K; 361 curcpu()->ci_ci.icache_size = 32 K; 362 assoc = 4; 363 break; 364 case IBMPOWER3II: 365 curcpu()->ci_ci.dcache_size = 64 K; 366 curcpu()->ci_ci.icache_size = 32 K; 367 curcpu()->ci_ci.dcache_line_size = 128; 368 curcpu()->ci_ci.icache_line_size = 128; 369 assoc = 128; /* not a typo */ 370 break; 371 case IBM970: 372 case IBM970FX: 373 case IBM970MP: 374 curcpu()->ci_ci.dcache_size = 32 K; 375 curcpu()->ci_ci.icache_size = 64 K; 376 curcpu()->ci_ci.dcache_line_size = 128; 377 curcpu()->ci_ci.icache_line_size = 128; 378 assoc = 2; 379 break; 380 381 default: 382 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 383 curcpu()->ci_ci.icache_size = PAGE_SIZE; 384 assoc = 1; 385 #undef K 386 } 387 388 /* 389 * Possibly recolor. 390 */ 391 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 392 } 393 394 struct cpu_info * 395 cpu_attach_common(device_t self, int id) 396 { 397 struct cpu_info *ci; 398 u_int pvr, vers; 399 400 ci = &cpu_info[id]; 401 #ifndef MULTIPROCESSOR 402 /* 403 * If this isn't the primary CPU, print an error message 404 * and just bail out. 405 */ 406 if (id != 0) { 407 aprint_normal(": ID %d\n", id); 408 aprint_normal_dev(self, 409 "processor off-line; " 410 "multiprocessor support not present in kernel\n"); 411 return (NULL); 412 } 413 #endif 414 415 ci->ci_cpuid = id; 416 ci->ci_idepth = -1; 417 ci->ci_dev = self; 418 ci->ci_idlespin = cpu_idlespin; 419 420 pvr = mfpvr(); 421 vers = (pvr >> 16) & 0xffff; 422 423 switch (id) { 424 case 0: 425 /* load my cpu_number to PIR */ 426 switch (vers) { 427 case MPC601: 428 case MPC604: 429 case MPC604e: 430 case MPC604ev: 431 case MPC7400: 432 case MPC7410: 433 case MPC7447A: 434 case MPC7448: 435 case MPC7450: 436 case MPC7455: 437 case MPC7457: 438 mtspr(SPR_PIR, id); 439 } 440 cpu_setup(self, ci); 441 break; 442 default: 443 if (id >= CPU_MAXNUM) { 444 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 445 panic("cpuattach"); 446 } 447 #ifndef MULTIPROCESSOR 448 aprint_normal(" not configured\n"); 449 return NULL; 450 #else 451 mi_cpu_attach(ci); 452 break; 453 #endif 454 } 455 return (ci); 456 } 457 458 void 459 cpu_setup(device_t self, struct cpu_info *ci) 460 { 461 u_int hid0, hid0_save, pvr, vers; 462 const char * const xname = device_xname(self); 463 const char *bitmask; 464 char hidbuf[128]; 465 char model[80]; 466 467 pvr = mfpvr(); 468 vers = (pvr >> 16) & 0xffff; 469 470 cpu_identify(model, sizeof(model)); 471 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 472 cpu_number() == 0 ? " (primary)" : ""); 473 474 /* set the cpu number */ 475 ci->ci_cpuid = cpu_number(); 476 hid0_save = hid0 = mfspr(SPR_HID0); 477 478 cpu_probe_cache(); 479 480 /* 481 * Configure power-saving mode. 482 */ 483 switch (vers) { 484 case MPC604: 485 case MPC604e: 486 case MPC604ev: 487 /* 488 * Do not have HID0 support settings, but can support 489 * MSR[POW] off 490 */ 491 powersave = 1; 492 break; 493 494 case MPC603: 495 case MPC603e: 496 case MPC603ev: 497 case MPC7400: 498 case MPC7410: 499 case MPC8240: 500 case MPC8245: 501 case MPCG2: 502 /* Select DOZE mode. */ 503 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 504 hid0 |= HID0_DOZE | HID0_DPM; 505 powersave = 1; 506 break; 507 508 case MPC750: 509 case IBM750FX: 510 case IBM750GX: 511 /* Select NAP mode. */ 512 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 513 hid0 |= HID0_NAP | HID0_DPM; 514 powersave = 1; 515 break; 516 517 case MPC7447A: 518 case MPC7448: 519 case MPC7457: 520 case MPC7455: 521 case MPC7450: 522 /* Enable the 7450 branch caches */ 523 hid0 |= HID0_SGE | HID0_BTIC; 524 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 525 /* Enable more and larger BAT registers */ 526 if (oeacpufeat & OEACPU_XBSEN) 527 hid0 |= HID0_XBSEN; 528 if (oeacpufeat & OEACPU_HIGHBAT) 529 hid0 |= HID0_HIGH_BAT_EN; 530 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 531 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 532 hid0 &= ~HID0_BTIC; 533 /* Select NAP mode. */ 534 hid0 &= ~HID0_SLEEP; 535 hid0 |= HID0_NAP | HID0_DPM; 536 powersave = 1; 537 break; 538 539 case IBM970: 540 case IBM970FX: 541 case IBM970MP: 542 case IBMPOWER3II: 543 default: 544 /* No power-saving mode is available. */ ; 545 } 546 547 #ifdef NAPMODE 548 switch (vers) { 549 case IBM750FX: 550 case IBM750GX: 551 case MPC750: 552 case MPC7400: 553 /* Select NAP mode. */ 554 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 555 hid0 |= HID0_NAP; 556 break; 557 } 558 #endif 559 560 switch (vers) { 561 case IBM750FX: 562 case IBM750GX: 563 case MPC750: 564 hid0 &= ~HID0_DBP; /* XXX correct? */ 565 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 566 break; 567 568 case MPC7400: 569 case MPC7410: 570 hid0 &= ~HID0_SPD; 571 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 572 hid0 |= HID0_EIEC; 573 break; 574 } 575 576 if (hid0 != hid0_save) { 577 mtspr(SPR_HID0, hid0); 578 __asm volatile("sync;isync"); 579 } 580 581 582 switch (vers) { 583 case MPC601: 584 bitmask = HID0_601_BITMASK; 585 break; 586 case MPC7450: 587 case MPC7455: 588 case MPC7457: 589 bitmask = HID0_7450_BITMASK; 590 break; 591 case IBM970: 592 case IBM970FX: 593 case IBM970MP: 594 bitmask = 0; 595 break; 596 default: 597 bitmask = HID0_BITMASK; 598 break; 599 } 600 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 601 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave); 602 603 ci->ci_khz = 0; 604 605 /* 606 * Display speed and cache configuration. 607 */ 608 switch (vers) { 609 case MPC604: 610 case MPC604e: 611 case MPC604ev: 612 case MPC750: 613 case IBM750FX: 614 case IBM750GX: 615 case MPC7400: 616 case MPC7410: 617 case MPC7447A: 618 case MPC7448: 619 case MPC7450: 620 case MPC7455: 621 case MPC7457: 622 aprint_normal_dev(self, ""); 623 cpu_probe_speed(ci); 624 aprint_normal("%u.%02u MHz", 625 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 626 switch (vers) { 627 case MPC7450: /* 7441 does not have L3! */ 628 case MPC7455: /* 7445 does not have L3! */ 629 case MPC7457: /* 7447 does not have L3! */ 630 cpu_config_l3cr(vers); 631 break; 632 case IBM750FX: 633 case IBM750GX: 634 case MPC750: 635 case MPC7400: 636 case MPC7410: 637 case MPC7447A: 638 case MPC7448: 639 cpu_config_l2cr(pvr); 640 break; 641 default: 642 break; 643 } 644 aprint_normal("\n"); 645 break; 646 } 647 648 #if NSYSMON_ENVSYS > 0 649 /* 650 * Attach MPC750 temperature sensor to the envsys subsystem. 651 * XXX the 74xx series also has this sensor, but it is not 652 * XXX supported by Motorola and may return values that are off by 653 * XXX 35-55 degrees C. 654 */ 655 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 656 cpu_tau_setup(ci); 657 #endif 658 659 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 660 NULL, xname, "clock"); 661 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 662 NULL, xname, "soft clock"); 663 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 664 NULL, xname, "soft net"); 665 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 666 NULL, xname, "soft serial"); 667 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 668 NULL, xname, "traps"); 669 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 670 &ci->ci_ev_traps, xname, "kernel DSI traps"); 671 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 672 &ci->ci_ev_traps, xname, "user DSI traps"); 673 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 674 &ci->ci_ev_udsi, xname, "user DSI failures"); 675 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 676 &ci->ci_ev_traps, xname, "kernel ISI traps"); 677 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 678 &ci->ci_ev_traps, xname, "user ISI traps"); 679 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 680 &ci->ci_ev_isi, xname, "user ISI failures"); 681 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 682 &ci->ci_ev_traps, xname, "system call traps"); 683 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 684 &ci->ci_ev_traps, xname, "PGM traps"); 685 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 686 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 687 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 688 &ci->ci_ev_fpu, xname, "FPU context switches"); 689 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 690 &ci->ci_ev_traps, xname, "user alignment traps"); 691 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 692 &ci->ci_ev_ali, xname, "user alignment traps"); 693 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 694 &ci->ci_ev_umchk, xname, "user MCHK failures"); 695 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 696 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 697 #ifdef ALTIVEC 698 if (cpu_altivec) { 699 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 700 &ci->ci_ev_vec, xname, "AltiVec context switches"); 701 } 702 #endif 703 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 704 NULL, xname, "IPIs"); 705 } 706 707 /* 708 * According to a document labeled "PVR Register Settings": 709 ** For integrated microprocessors the PVR register inside the device 710 ** will identify the version of the microprocessor core. You must also 711 ** read the Device ID, PCI register 02, to identify the part and the 712 ** Revision ID, PCI register 08, to identify the revision of the 713 ** integrated microprocessor. 714 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 715 */ 716 717 void 718 cpu_identify(char *str, size_t len) 719 { 720 u_int pvr, major, minor; 721 uint16_t vers, rev, revfmt; 722 const struct cputab *cp; 723 const char *name; 724 size_t n; 725 726 pvr = mfpvr(); 727 vers = pvr >> 16; 728 rev = pvr; 729 730 switch (vers) { 731 case MPC7410: 732 minor = (pvr >> 0) & 0xff; 733 major = minor <= 4 ? 1 : 2; 734 break; 735 case MPCG2: /*XXX see note above */ 736 major = (pvr >> 4) & 0xf; 737 minor = (pvr >> 0) & 0xf; 738 break; 739 default: 740 major = (pvr >> 8) & 0xf; 741 minor = (pvr >> 0) & 0xf; 742 } 743 744 for (cp = models; cp->name[0] != '\0'; cp++) { 745 if (cp->version == vers) 746 break; 747 } 748 749 if (str == NULL) { 750 str = cpu_model; 751 len = sizeof(cpu_model); 752 cpu = vers; 753 } 754 755 revfmt = cp->revfmt; 756 name = cp->name; 757 if (rev == MPC750 && pvr == 15) { 758 name = "755"; 759 revfmt = REVFMT_HEX; 760 } 761 762 if (cp->name[0] != '\0') { 763 n = snprintf(str, len, "%s (Revision ", cp->name); 764 } else { 765 n = snprintf(str, len, "Version %#x (Revision ", vers); 766 } 767 if (len > n) { 768 switch (revfmt) { 769 case REVFMT_MAJMIN: 770 snprintf(str + n, len - n, "%u.%u)", major, minor); 771 break; 772 case REVFMT_HEX: 773 snprintf(str + n, len - n, "0x%04x)", rev); 774 break; 775 case REVFMT_DEC: 776 snprintf(str + n, len - n, "%u)", rev); 777 break; 778 } 779 } 780 } 781 782 #ifdef L2CR_CONFIG 783 u_int l2cr_config = L2CR_CONFIG; 784 #else 785 u_int l2cr_config = 0; 786 #endif 787 788 #ifdef L3CR_CONFIG 789 u_int l3cr_config = L3CR_CONFIG; 790 #else 791 u_int l3cr_config = 0; 792 #endif 793 794 void 795 cpu_enable_l2cr(register_t l2cr) 796 { 797 register_t msr, x; 798 uint16_t vers; 799 800 vers = mfpvr() >> 16; 801 802 /* Disable interrupts and set the cache config bits. */ 803 msr = mfmsr(); 804 mtmsr(msr & ~PSL_EE); 805 #ifdef ALTIVEC 806 if (cpu_altivec) 807 __asm volatile("dssall"); 808 #endif 809 __asm volatile("sync"); 810 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 811 __asm volatile("sync"); 812 813 /* Wait for L2 clock to be stable (640 L2 clocks). */ 814 delay(100); 815 816 /* Invalidate all L2 contents. */ 817 if (MPC745X_P(vers)) { 818 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 819 do { 820 x = mfspr(SPR_L2CR); 821 } while (x & L2CR_L2I); 822 } else { 823 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 824 do { 825 x = mfspr(SPR_L2CR); 826 } while (x & L2CR_L2IP); 827 } 828 /* Enable L2 cache. */ 829 l2cr |= L2CR_L2E; 830 mtspr(SPR_L2CR, l2cr); 831 mtmsr(msr); 832 } 833 834 void 835 cpu_enable_l3cr(register_t l3cr) 836 { 837 register_t x; 838 839 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 840 841 /* 842 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 843 * L3CLKEN. (also mask off reserved bits in case they were included 844 * in L3CR_CONFIG) 845 */ 846 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 847 mtspr(SPR_L3CR, l3cr); 848 849 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 850 l3cr |= 0x04000000; 851 mtspr(SPR_L3CR, l3cr); 852 853 /* 3: Set L3CLKEN to 1*/ 854 l3cr |= L3CR_L3CLKEN; 855 mtspr(SPR_L3CR, l3cr); 856 857 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 858 __asm volatile("dssall;sync"); 859 /* L3 cache is already disabled, no need to clear L3E */ 860 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 861 do { 862 x = mfspr(SPR_L3CR); 863 } while (x & L3CR_L3I); 864 865 /* 6: Clear L3CLKEN to 0 */ 866 l3cr &= ~L3CR_L3CLKEN; 867 mtspr(SPR_L3CR, l3cr); 868 869 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 870 __asm volatile("sync"); 871 delay(100); 872 873 /* 8: Set L3E and L3CLKEN */ 874 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 875 mtspr(SPR_L3CR, l3cr); 876 877 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 878 __asm volatile("sync"); 879 delay(100); 880 } 881 882 void 883 cpu_config_l2cr(int pvr) 884 { 885 register_t l2cr; 886 u_int vers = (pvr >> 16) & 0xffff; 887 888 l2cr = mfspr(SPR_L2CR); 889 890 /* 891 * For MP systems, the firmware may only configure the L2 cache 892 * on the first CPU. In this case, assume that the other CPUs 893 * should use the same value for L2CR. 894 */ 895 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 896 l2cr_config = l2cr; 897 } 898 899 /* 900 * Configure L2 cache if not enabled. 901 */ 902 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 903 cpu_enable_l2cr(l2cr_config); 904 l2cr = mfspr(SPR_L2CR); 905 } 906 907 if ((l2cr & L2CR_L2E) == 0) { 908 aprint_normal(" L2 cache present but not enabled "); 909 return; 910 } 911 aprint_normal(","); 912 913 switch (vers) { 914 case IBM750FX: 915 case IBM750GX: 916 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 917 break; 918 case MPC750: 919 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 920 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 921 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 922 else 923 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 924 break; 925 case MPC7447A: 926 case MPC7457: 927 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 928 return; 929 case MPC7448: 930 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 931 return; 932 case MPC7450: 933 case MPC7455: 934 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 935 break; 936 default: 937 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 938 break; 939 } 940 } 941 942 void 943 cpu_config_l3cr(int vers) 944 { 945 register_t l2cr; 946 register_t l3cr; 947 948 l2cr = mfspr(SPR_L2CR); 949 950 /* 951 * For MP systems, the firmware may only configure the L2 cache 952 * on the first CPU. In this case, assume that the other CPUs 953 * should use the same value for L2CR. 954 */ 955 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 956 l2cr_config = l2cr; 957 } 958 959 /* 960 * Configure L2 cache if not enabled. 961 */ 962 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 963 cpu_enable_l2cr(l2cr_config); 964 l2cr = mfspr(SPR_L2CR); 965 } 966 967 aprint_normal(","); 968 switch (vers) { 969 case MPC7447A: 970 case MPC7457: 971 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 972 return; 973 case MPC7448: 974 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 975 return; 976 default: 977 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 978 break; 979 } 980 981 l3cr = mfspr(SPR_L3CR); 982 983 /* 984 * For MP systems, the firmware may only configure the L3 cache 985 * on the first CPU. In this case, assume that the other CPUs 986 * should use the same value for L3CR. 987 */ 988 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 989 l3cr_config = l3cr; 990 } 991 992 /* 993 * Configure L3 cache if not enabled. 994 */ 995 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 996 cpu_enable_l3cr(l3cr_config); 997 l3cr = mfspr(SPR_L3CR); 998 } 999 1000 if (l3cr & L3CR_L3E) { 1001 aprint_normal(","); 1002 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1003 } 1004 } 1005 1006 void 1007 cpu_probe_speed(struct cpu_info *ci) 1008 { 1009 uint64_t cps; 1010 1011 mtspr(SPR_MMCR0, MMCR0_FC); 1012 mtspr(SPR_PMC1, 0); 1013 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1014 delay(100000); 1015 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1016 1017 mtspr(SPR_MMCR0, MMCR0_FC); 1018 1019 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1020 } 1021 1022 /* 1023 * Read the Dynamic Frequency Switching state and return a divisor for 1024 * the maximum frequency. 1025 */ 1026 int 1027 cpu_get_dfs(void) 1028 { 1029 u_int pvr, vers; 1030 1031 pvr = mfpvr(); 1032 vers = pvr >> 16; 1033 1034 switch (vers) { 1035 case MPC7448: 1036 if (mfspr(SPR_HID1) & HID1_DFS4) 1037 return 4; 1038 case MPC7447A: 1039 if (mfspr(SPR_HID1) & HID1_DFS2) 1040 return 2; 1041 } 1042 return 1; 1043 } 1044 1045 /* 1046 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1047 */ 1048 void 1049 cpu_set_dfs(int div) 1050 { 1051 uint64_t where; 1052 u_int dfs_mask, pvr, vers; 1053 1054 pvr = mfpvr(); 1055 vers = pvr >> 16; 1056 dfs_mask = 0; 1057 1058 switch (vers) { 1059 case MPC7448: 1060 dfs_mask |= HID1_DFS4; 1061 case MPC7447A: 1062 dfs_mask |= HID1_DFS2; 1063 break; 1064 default: 1065 printf("cpu_set_dfs: DFS not supported\n"); 1066 return; 1067 1068 } 1069 1070 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1071 xc_wait(where); 1072 } 1073 1074 static void 1075 cpu_set_dfs_xcall(void *arg1, void *arg2) 1076 { 1077 u_int dfs_mask, hid1, old_hid1; 1078 int *divisor, s; 1079 1080 divisor = arg1; 1081 dfs_mask = *(u_int *)arg2; 1082 1083 s = splhigh(); 1084 hid1 = old_hid1 = mfspr(SPR_HID1); 1085 1086 switch (*divisor) { 1087 case 1: 1088 hid1 &= ~dfs_mask; 1089 break; 1090 case 2: 1091 hid1 &= ~(dfs_mask & HID1_DFS4); 1092 hid1 |= dfs_mask & HID1_DFS2; 1093 break; 1094 case 4: 1095 hid1 &= ~(dfs_mask & HID1_DFS2); 1096 hid1 |= dfs_mask & HID1_DFS4; 1097 break; 1098 } 1099 1100 if (hid1 != old_hid1) { 1101 __asm volatile("sync"); 1102 mtspr(SPR_HID1, hid1); 1103 __asm volatile("sync;isync"); 1104 } 1105 1106 splx(s); 1107 } 1108 1109 #if NSYSMON_ENVSYS > 0 1110 void 1111 cpu_tau_setup(struct cpu_info *ci) 1112 { 1113 struct sysmon_envsys *sme; 1114 int error, therm_delay; 1115 1116 mtspr(SPR_THRM1, SPR_THRM_VALID); 1117 mtspr(SPR_THRM2, 0); 1118 1119 /* 1120 * we need to figure out how much 20+us in units of CPU clock cycles 1121 * are 1122 */ 1123 1124 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1125 1126 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1127 1128 sme = sysmon_envsys_create(); 1129 1130 sensor.units = ENVSYS_STEMP; 1131 sensor.state = ENVSYS_SINVALID; 1132 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1133 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1134 sysmon_envsys_destroy(sme); 1135 return; 1136 } 1137 1138 sme->sme_name = device_xname(ci->ci_dev); 1139 sme->sme_cookie = ci; 1140 sme->sme_refresh = cpu_tau_refresh; 1141 1142 if ((error = sysmon_envsys_register(sme)) != 0) { 1143 aprint_error_dev(ci->ci_dev, 1144 " unable to register with sysmon (%d)\n", error); 1145 sysmon_envsys_destroy(sme); 1146 } 1147 } 1148 1149 1150 /* Find the temperature of the CPU. */ 1151 void 1152 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1153 { 1154 int i, threshold, count; 1155 1156 threshold = 64; /* Half of the 7-bit sensor range */ 1157 1158 /* Successive-approximation code adapted from Motorola 1159 * application note AN1800/D, "Programming the Thermal Assist 1160 * Unit in the MPC750 Microprocessor". 1161 */ 1162 for (i = 5; i >= 0 ; i--) { 1163 mtspr(SPR_THRM1, 1164 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1165 count = 0; 1166 while ((count < 100000) && 1167 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1168 count++; 1169 delay(1); 1170 } 1171 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1172 /* The interrupt bit was set, meaning the 1173 * temperature was above the threshold 1174 */ 1175 threshold += 1 << i; 1176 } else { 1177 /* Temperature was below the threshold */ 1178 threshold -= 1 << i; 1179 } 1180 1181 } 1182 threshold += 2; 1183 1184 /* Convert the temperature in degrees C to microkelvin */ 1185 edata->value_cur = (threshold * 1000000) + 273150000; 1186 edata->state = ENVSYS_SVALID; 1187 } 1188 #endif /* NSYSMON_ENVSYS > 0 */ 1189 1190 #ifdef MULTIPROCESSOR 1191 extern volatile u_int cpu_spinstart_ack; 1192 1193 int 1194 cpu_spinup(device_t self, struct cpu_info *ci) 1195 { 1196 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1197 struct pglist mlist; 1198 int i, error, pvr, vers; 1199 char *hp; 1200 1201 pvr = mfpvr(); 1202 vers = pvr >> 16; 1203 KASSERT(ci != curcpu()); 1204 1205 /* Now allocate a hatch stack */ 1206 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1207 &mlist, 1, 1); 1208 if (error) { 1209 aprint_error(": unable to allocate hatch stack\n"); 1210 return -1; 1211 } 1212 1213 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1214 memset(hp, 0, 0x1000); 1215 1216 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1217 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1218 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1219 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1220 1221 cpu_hatch_data = h; 1222 h->running = 0; 1223 h->self = self; 1224 h->ci = ci; 1225 h->pir = ci->ci_cpuid; 1226 1227 cpu_hatch_stack = (uint32_t)hp; 1228 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1229 1230 /* copy special registers */ 1231 1232 h->hid0 = mfspr(SPR_HID0); 1233 1234 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1235 for (i = 0; i < 16; i++) { 1236 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1237 "r"(i << ADDR_SR_SHFT)); 1238 } 1239 if (oeacpufeat & OEACPU_64) 1240 h->asr = mfspr(SPR_ASR); 1241 else 1242 h->asr = 0; 1243 1244 /* copy the bat regs */ 1245 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1246 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1247 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1248 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1249 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1250 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1251 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1252 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1253 __asm volatile ("sync; isync"); 1254 1255 if (md_setup_trampoline(h, ci) == -1) 1256 return -1; 1257 md_presync_timebase(h); 1258 md_start_timebase(h); 1259 1260 /* wait for secondary printf */ 1261 1262 delay(200000); 1263 1264 if (h->running < 1) { 1265 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1266 ci->ci_cpuid, cpu_spinstart_ack); 1267 Debugger(); 1268 return -1; 1269 } 1270 1271 /* Register IPI Interrupt */ 1272 if (ipiops.ppc_establish_ipi) 1273 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1274 1275 return 0; 1276 } 1277 1278 static volatile int start_secondary_cpu; 1279 extern void tlbia(void); 1280 1281 register_t 1282 cpu_hatch(void) 1283 { 1284 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1285 struct cpu_info * const ci = h->ci; 1286 struct pcb *pcb; 1287 u_int msr; 1288 int i; 1289 1290 /* Initialize timebase. */ 1291 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1292 1293 /* 1294 * Set PIR (Processor Identification Register). i.e. whoami 1295 * Note that PIR is read-only on some CPU versions, so we write to it 1296 * only if it has a different value than we need. 1297 */ 1298 1299 msr = mfspr(SPR_PIR); 1300 if (msr != h->pir) 1301 mtspr(SPR_PIR, h->pir); 1302 1303 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1304 curlwp = ci->ci_curlwp; 1305 cpu_spinstart_ack = 0; 1306 1307 /* Initialize MMU. */ 1308 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1309 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1310 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1311 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1312 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1313 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1314 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1315 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1316 1317 mtspr(SPR_HID0, h->hid0); 1318 1319 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1320 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1321 1322 __asm volatile ("sync"); 1323 for (i = 0; i < 16; i++) 1324 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1325 __asm volatile ("sync; isync"); 1326 1327 if (oeacpufeat & OEACPU_64) 1328 mtspr(SPR_ASR, h->asr); 1329 1330 cpu_spinstart_ack = 1; 1331 __asm ("ptesync"); 1332 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1333 __asm volatile ("sync; isync"); 1334 1335 cpu_spinstart_ack = 5; 1336 for (i = 0; i < 16; i++) 1337 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1338 "r"(i << ADDR_SR_SHFT)); 1339 1340 /* Enable I/D address translations. */ 1341 msr = mfmsr(); 1342 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1343 mtmsr(msr); 1344 __asm volatile ("sync; isync"); 1345 cpu_spinstart_ack = 2; 1346 1347 md_sync_timebase(h); 1348 1349 cpu_setup(h->self, ci); 1350 1351 h->running = 1; 1352 __asm volatile ("sync; isync"); 1353 1354 while (start_secondary_cpu == 0) 1355 ; 1356 1357 __asm volatile ("sync; isync"); 1358 1359 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1360 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1361 1362 md_setup_interrupts(); 1363 1364 ci->ci_ipending = 0; 1365 ci->ci_cpl = 0; 1366 1367 mtmsr(mfmsr() | PSL_EE); 1368 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1369 return pcb->pcb_sp; 1370 } 1371 1372 void 1373 cpu_boot_secondary_processors(void) 1374 { 1375 start_secondary_cpu = 1; 1376 __asm volatile ("sync"); 1377 } 1378 1379 #endif /*MULTIPROCESSOR*/ 1380