1 /* $NetBSD: cpu_subr.c,v 1.13 2004/03/11 15:40:13 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.13 2004/03/11 15:40:13 christos Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 #if NSYSMON_ENVSYS > 0 63 static void cpu_tau_setup(struct cpu_info *); 64 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 65 struct envsys_tre_data *)); 66 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 67 struct envsys_basic_info *)); 68 #endif 69 70 int cpu; 71 int ncpus; 72 73 struct fmttab { 74 register_t fmt_mask; 75 register_t fmt_value; 76 const char *fmt_string; 77 }; 78 79 static const struct fmttab cpu_7450_l2cr_formats[] = { 80 { L2CR_L2E, 0, " disabled" }, 81 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 84 { L2CR_L2E, ~0, " 256KB L2 cache" }, 85 { 0 } 86 }; 87 88 static const struct fmttab cpu_7457_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 512KB L2 cache" }, 94 { 0 } 95 }; 96 97 static const struct fmttab cpu_7450_l3cr_formats[] = { 98 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 99 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 100 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 101 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 102 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 103 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 104 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 105 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 106 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 107 { L3CR_L3SIZ, ~0, " L3 cache" }, 108 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 109 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 110 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 111 { L3CR_L3CLK, ~0, " at" }, 112 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 113 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 114 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 115 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 116 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 117 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 118 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 119 { L3CR_L3CLK, ~0, " ratio" }, 120 { 0, 0 }, 121 }; 122 123 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 124 { L2CR_L2E, 0, " disabled" }, 125 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 126 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 127 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 128 { 0, ~0, " 512KB" }, 129 { L2CR_L2WT, L2CR_L2WT, " WT" }, 130 { L2CR_L2WT, 0, " WB" }, 131 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 132 { 0, ~0, " L2 cache" }, 133 { 0 } 134 }; 135 136 static const struct fmttab cpu_l2cr_formats[] = { 137 { L2CR_L2E, 0, " disabled" }, 138 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 139 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 140 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 141 { L2CR_L2PE, L2CR_L2PE, " parity" }, 142 { L2CR_L2PE, 0, " no-parity" }, 143 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 144 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 145 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 146 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 147 { L2CR_L2WT, L2CR_L2WT, " WT" }, 148 { L2CR_L2WT, 0, " WB" }, 149 { L2CR_L2E, ~0, " L2 cache" }, 150 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 151 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 152 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 153 { L2CR_L2CLK, ~0, " at" }, 154 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 155 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 156 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 157 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 158 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 159 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 160 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 161 { L2CR_L2CLK, ~0, " ratio" }, 162 { 0 } 163 }; 164 165 static void cpu_fmttab_print(const struct fmttab *, register_t); 166 167 struct cputab { 168 const char name[8]; 169 uint16_t version; 170 uint16_t revfmt; 171 }; 172 #define REVFMT_MAJMIN 1 /* %u.%u */ 173 #define REVFMT_HEX 2 /* 0x%04x */ 174 #define REVFMT_DEC 3 /* %u */ 175 static const struct cputab models[] = { 176 { "601", MPC601, REVFMT_DEC }, 177 { "602", MPC602, REVFMT_DEC }, 178 { "603", MPC603, REVFMT_MAJMIN }, 179 { "603e", MPC603e, REVFMT_MAJMIN }, 180 { "603ev", MPC603ev, REVFMT_MAJMIN }, 181 { "604", MPC604, REVFMT_MAJMIN }, 182 { "604ev", MPC604ev, REVFMT_MAJMIN }, 183 { "620", MPC620, REVFMT_HEX }, 184 { "750", MPC750, REVFMT_MAJMIN }, 185 { "750FX", IBM750FX, REVFMT_MAJMIN }, 186 { "7400", MPC7400, REVFMT_MAJMIN }, 187 { "7410", MPC7410, REVFMT_MAJMIN }, 188 { "7450", MPC7450, REVFMT_MAJMIN }, 189 { "7455", MPC7455, REVFMT_MAJMIN }, 190 { "7457", MPC7457, REVFMT_MAJMIN }, 191 { "8240", MPC8240, REVFMT_MAJMIN }, 192 { "", 0, REVFMT_HEX } 193 }; 194 195 196 #ifdef MULTIPROCESSOR 197 struct cpu_info cpu_info[CPU_MAXNUM]; 198 #else 199 struct cpu_info cpu_info[1]; 200 #endif 201 202 int cpu_altivec; 203 char cpu_model[80]; 204 205 void 206 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 207 { 208 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 209 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 210 (data & fmt->fmt_mask) == fmt->fmt_value) 211 aprint_normal("%s", fmt->fmt_string); 212 } 213 } 214 215 void 216 cpu_probe_cache(void) 217 { 218 u_int assoc, pvr, vers; 219 220 pvr = mfpvr(); 221 vers = pvr >> 16; 222 223 switch (vers) { 224 #define K *1024 225 case IBM750FX: 226 case MPC601: 227 case MPC750: 228 case MPC7450: 229 case MPC7455: 230 case MPC7457: 231 curcpu()->ci_ci.dcache_size = 32 K; 232 curcpu()->ci_ci.icache_size = 32 K; 233 assoc = 8; 234 break; 235 case MPC603: 236 curcpu()->ci_ci.dcache_size = 8 K; 237 curcpu()->ci_ci.icache_size = 8 K; 238 assoc = 2; 239 break; 240 case MPC603e: 241 case MPC603ev: 242 case MPC604: 243 case MPC8240: 244 case MPC8245: 245 curcpu()->ci_ci.dcache_size = 16 K; 246 curcpu()->ci_ci.icache_size = 16 K; 247 assoc = 4; 248 break; 249 case MPC604ev: 250 curcpu()->ci_ci.dcache_size = 32 K; 251 curcpu()->ci_ci.icache_size = 32 K; 252 assoc = 4; 253 break; 254 default: 255 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 256 curcpu()->ci_ci.icache_size = PAGE_SIZE; 257 assoc = 1; 258 #undef K 259 } 260 261 /* Presently common across all implementations. */ 262 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 263 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 264 265 /* 266 * Possibly recolor. 267 */ 268 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 269 } 270 271 struct cpu_info * 272 cpu_attach_common(struct device *self, int id) 273 { 274 struct cpu_info *ci; 275 u_int pvr, vers; 276 277 ncpus++; 278 ci = &cpu_info[id]; 279 #ifndef MULTIPROCESSOR 280 /* 281 * If this isn't the primary CPU, print an error message 282 * and just bail out. 283 */ 284 if (id != 0) { 285 aprint_normal(": ID %d\n", id); 286 aprint_normal("%s: processor off-line; multiprocessor support " 287 "not present in kernel\n", self->dv_xname); 288 return (NULL); 289 } 290 #endif 291 292 ci->ci_cpuid = id; 293 ci->ci_intrdepth = -1; 294 ci->ci_dev = self; 295 296 pvr = mfpvr(); 297 vers = (pvr >> 16) & 0xffff; 298 299 switch (id) { 300 case 0: 301 /* load my cpu_number to PIR */ 302 switch (vers) { 303 case MPC601: 304 case MPC604: 305 case MPC604ev: 306 case MPC7400: 307 case MPC7410: 308 case MPC7450: 309 case MPC7455: 310 case MPC7457: 311 mtspr(SPR_PIR, id); 312 } 313 cpu_setup(self, ci); 314 break; 315 default: 316 if (id >= CPU_MAXNUM) { 317 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 318 panic("cpuattach"); 319 } 320 #ifndef MULTIPROCESSOR 321 aprint_normal(" not configured\n"); 322 return NULL; 323 #endif 324 } 325 return (ci); 326 } 327 328 void 329 cpu_setup(self, ci) 330 struct device *self; 331 struct cpu_info *ci; 332 { 333 u_int hid0, pvr, vers; 334 char *bitmask, hidbuf[128]; 335 char model[80]; 336 337 pvr = mfpvr(); 338 vers = (pvr >> 16) & 0xffff; 339 340 cpu_identify(model, sizeof(model)); 341 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 342 cpu_number() == 0 ? " (primary)" : ""); 343 344 hid0 = mfspr(SPR_HID0); 345 cpu_probe_cache(); 346 347 /* 348 * Configure power-saving mode. 349 */ 350 switch (vers) { 351 case MPC603: 352 case MPC603e: 353 case MPC603ev: 354 case MPC604ev: 355 case MPC750: 356 case IBM750FX: 357 case MPC7400: 358 case MPC7410: 359 case MPC8240: 360 case MPC8245: 361 /* Select DOZE mode. */ 362 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 363 hid0 |= HID0_DOZE | HID0_DPM; 364 powersave = 1; 365 break; 366 367 case MPC7457: 368 case MPC7455: 369 case MPC7450: 370 /* Enable the 7450 branch caches */ 371 hid0 |= HID0_SGE | HID0_BTIC; 372 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 373 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 374 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 375 hid0 &= ~HID0_BTIC; 376 /* Select NAP mode. */ 377 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 378 hid0 |= HID0_NAP | HID0_DPM; 379 powersave = 0; /* but don't use it */ 380 break; 381 382 default: 383 /* No power-saving mode is available. */ ; 384 } 385 386 #ifdef NAPMODE 387 switch (vers) { 388 case IBM750FX: 389 case MPC750: 390 case MPC7400: 391 /* Select NAP mode. */ 392 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 393 hid0 |= HID0_NAP; 394 break; 395 } 396 #endif 397 398 switch (vers) { 399 case IBM750FX: 400 case MPC750: 401 hid0 &= ~HID0_DBP; /* XXX correct? */ 402 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 403 break; 404 405 case MPC7400: 406 case MPC7410: 407 hid0 &= ~HID0_SPD; 408 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 409 hid0 |= HID0_EIEC; 410 break; 411 } 412 413 mtspr(SPR_HID0, hid0); 414 415 switch (vers) { 416 case MPC601: 417 bitmask = HID0_601_BITMASK; 418 break; 419 case MPC7450: 420 case MPC7455: 421 case MPC7457: 422 bitmask = HID0_7450_BITMASK; 423 break; 424 default: 425 bitmask = HID0_BITMASK; 426 break; 427 } 428 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 429 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 430 431 /* 432 * Display speed and cache configuration. 433 */ 434 if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX || 435 vers == MPC7410 || MPC745X_P(vers)) { 436 aprint_normal("%s: ", self->dv_xname); 437 cpu_print_speed(); 438 if (MPC745X_P(vers)) { 439 cpu_config_l3cr(vers); 440 } else { 441 cpu_config_l2cr(pvr); 442 } 443 aprint_normal("\n"); 444 } 445 446 #if NSYSMON_ENVSYS > 0 447 /* 448 * Attach MPC750 temperature sensor to the envsys subsystem. 449 * XXX the 74xx series also has this sensor, but it is not 450 * XXX supported by Motorola and may return values that are off by 451 * XXX 35-55 degrees C. 452 */ 453 if (vers == MPC750 || vers == IBM750FX) 454 cpu_tau_setup(ci); 455 #endif 456 457 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 458 NULL, self->dv_xname, "clock"); 459 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 460 NULL, self->dv_xname, "soft clock"); 461 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 462 NULL, self->dv_xname, "soft net"); 463 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 464 NULL, self->dv_xname, "soft serial"); 465 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 466 NULL, self->dv_xname, "traps"); 467 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 468 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 469 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 470 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 471 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 472 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 473 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 474 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 475 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 476 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 477 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 478 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 479 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 480 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 481 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 482 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 483 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 484 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 485 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 486 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 487 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 488 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 489 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 490 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 491 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 492 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 493 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 494 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 495 #ifdef ALTIVEC 496 if (cpu_altivec) { 497 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 498 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 499 } 500 #endif 501 } 502 503 void 504 cpu_identify(char *str, size_t len) 505 { 506 u_int pvr, maj, min; 507 uint16_t vers, rev, revfmt; 508 const struct cputab *cp; 509 const char *name; 510 size_t n; 511 512 pvr = mfpvr(); 513 vers = pvr >> 16; 514 rev = pvr; 515 switch (vers) { 516 case MPC7410: 517 min = (pvr >> 0) & 0xff; 518 maj = min <= 4 ? 1 : 2; 519 break; 520 default: 521 maj = (pvr >> 8) & 0xf; 522 min = (pvr >> 0) & 0xf; 523 } 524 525 for (cp = models; cp->name[0] != '\0'; cp++) { 526 if (cp->version == vers) 527 break; 528 } 529 530 if (str == NULL) { 531 str = cpu_model; 532 len = sizeof(cpu_model); 533 cpu = vers; 534 } 535 536 revfmt = cp->revfmt; 537 name = cp->name; 538 if (rev == MPC750 && pvr == 15) { 539 name = "755"; 540 revfmt = REVFMT_HEX; 541 } 542 543 if (cp->name[0] != '\0') { 544 n = snprintf(str, len, "%s (Revision ", cp->name); 545 } else { 546 n = snprintf(str, len, "Version %#x (Revision ", vers); 547 } 548 if (len > n) { 549 switch (revfmt) { 550 case REVFMT_MAJMIN: 551 snprintf(str + n, len - n, "%u.%u)", maj, min); 552 break; 553 case REVFMT_HEX: 554 snprintf(str + n, len - n, "0x%04x)", rev); 555 break; 556 case REVFMT_DEC: 557 snprintf(str + n, len - n, "%u)", rev); 558 break; 559 } 560 } 561 } 562 563 #ifdef L2CR_CONFIG 564 u_int l2cr_config = L2CR_CONFIG; 565 #else 566 u_int l2cr_config = 0; 567 #endif 568 569 #ifdef L3CR_CONFIG 570 u_int l3cr_config = L3CR_CONFIG; 571 #else 572 u_int l3cr_config = 0; 573 #endif 574 575 void 576 cpu_enable_l2cr(register_t l2cr) 577 { 578 register_t msr, x; 579 580 /* Disable interrupts and set the cache config bits. */ 581 msr = mfmsr(); 582 mtmsr(msr & ~PSL_EE); 583 #ifdef ALTIVEC 584 if (cpu_altivec) 585 __asm __volatile("dssall"); 586 #endif 587 __asm __volatile("sync"); 588 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 589 __asm __volatile("sync"); 590 591 /* Wait for L2 clock to be stable (640 L2 clocks). */ 592 delay(100); 593 594 /* Invalidate all L2 contents. */ 595 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 596 do { 597 x = mfspr(SPR_L2CR); 598 } while (x & L2CR_L2IP); 599 600 /* Enable L2 cache. */ 601 l2cr |= L2CR_L2E; 602 mtspr(SPR_L2CR, l2cr); 603 mtmsr(msr); 604 } 605 606 void 607 cpu_enable_l3cr(register_t l3cr) 608 { 609 register_t x; 610 611 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 612 613 /* 614 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 615 * L3CLKEN. (also mask off reserved bits in case they were included 616 * in L3CR_CONFIG) 617 */ 618 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 619 mtspr(SPR_L3CR, l3cr); 620 621 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 622 l3cr |= 0x04000000; 623 mtspr(SPR_L3CR, l3cr); 624 625 /* 3: Set L3CLKEN to 1*/ 626 l3cr |= L3CR_L3CLKEN; 627 mtspr(SPR_L3CR, l3cr); 628 629 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 630 __asm __volatile("dssall;sync"); 631 /* L3 cache is already disabled, no need to clear L3E */ 632 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 633 do { 634 x = mfspr(SPR_L3CR); 635 } while (x & L3CR_L3I); 636 637 /* 6: Clear L3CLKEN to 0 */ 638 l3cr &= ~L3CR_L3CLKEN; 639 mtspr(SPR_L3CR, l3cr); 640 641 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 642 __asm __volatile("sync"); 643 delay(100); 644 645 /* 8: Set L3E and L3CLKEN */ 646 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 647 mtspr(SPR_L3CR, l3cr); 648 649 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 650 __asm __volatile("sync"); 651 delay(100); 652 } 653 654 void 655 cpu_config_l2cr(int pvr) 656 { 657 register_t l2cr; 658 659 l2cr = mfspr(SPR_L2CR); 660 661 /* 662 * For MP systems, the firmware may only configure the L2 cache 663 * on the first CPU. In this case, assume that the other CPUs 664 * should use the same value for L2CR. 665 */ 666 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 667 l2cr_config = l2cr; 668 } 669 670 /* 671 * Configure L2 cache if not enabled. 672 */ 673 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 674 cpu_enable_l2cr(l2cr_config); 675 l2cr = mfspr(SPR_L2CR); 676 } 677 678 if ((l2cr & L2CR_L2E) == 0) 679 return; 680 681 aprint_normal(","); 682 if ((pvr >> 16) == IBM750FX || 683 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 684 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 685 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 686 } else { 687 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 688 } 689 } 690 691 void 692 cpu_config_l3cr(int vers) 693 { 694 register_t l2cr; 695 register_t l3cr; 696 697 l2cr = mfspr(SPR_L2CR); 698 699 /* 700 * For MP systems, the firmware may only configure the L2 cache 701 * on the first CPU. In this case, assume that the other CPUs 702 * should use the same value for L2CR. 703 */ 704 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 705 l2cr_config = l2cr; 706 } 707 708 /* 709 * Configure L2 cache if not enabled. 710 */ 711 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 712 cpu_enable_l2cr(l2cr_config); 713 l2cr = mfspr(SPR_L2CR); 714 } 715 716 aprint_normal(","); 717 cpu_fmttab_print(vers == MPC7457 718 ? cpu_7457_l2cr_formats : cpu_7450_l2cr_formats, l2cr); 719 720 l3cr = mfspr(SPR_L3CR); 721 722 /* 723 * For MP systems, the firmware may only configure the L3 cache 724 * on the first CPU. In this case, assume that the other CPUs 725 * should use the same value for L3CR. 726 */ 727 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 728 l3cr_config = l3cr; 729 } 730 731 /* 732 * Configure L3 cache if not enabled. 733 */ 734 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 735 cpu_enable_l3cr(l3cr_config); 736 l3cr = mfspr(SPR_L3CR); 737 } 738 739 if (l3cr & L3CR_L3E) { 740 aprint_normal(","); 741 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 742 } 743 } 744 745 void 746 cpu_print_speed(void) 747 { 748 uint64_t cps; 749 750 mtspr(SPR_MMCR0, MMCR0_FC); 751 mtspr(SPR_PMC1, 0); 752 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 753 delay(100000); 754 cps = (mfspr(SPR_PMC1) * 10) + 4999; 755 756 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 757 } 758 759 #if NSYSMON_ENVSYS > 0 760 const struct envsys_range cpu_tau_ranges[] = { 761 { 0, 0, ENVSYS_STEMP} 762 }; 763 764 struct envsys_basic_info cpu_tau_info[] = { 765 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 766 }; 767 768 void 769 cpu_tau_setup(struct cpu_info *ci) 770 { 771 struct { 772 struct sysmon_envsys sme; 773 struct envsys_tre_data tau_info; 774 } *datap; 775 int error; 776 777 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 778 779 ci->ci_sysmon_cookie = &datap->sme; 780 datap->sme.sme_nsensors = 1; 781 datap->sme.sme_envsys_version = 1000; 782 datap->sme.sme_ranges = cpu_tau_ranges; 783 datap->sme.sme_sensor_info = cpu_tau_info; 784 datap->sme.sme_sensor_data = &datap->tau_info; 785 786 datap->sme.sme_sensor_data->sensor = 0; 787 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 788 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 789 datap->sme.sme_cookie = ci; 790 datap->sme.sme_gtredata = cpu_tau_gtredata; 791 datap->sme.sme_streinfo = cpu_tau_streinfo; 792 datap->sme.sme_flags = 0; 793 794 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 795 aprint_error("%s: unable to register with sysmon (%d)\n", 796 ci->ci_dev->dv_xname, error); 797 } 798 799 800 /* Find the temperature of the CPU. */ 801 int 802 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 803 { 804 int i, threshold, count; 805 806 if (tred->sensor != 0) { 807 tred->validflags = 0; 808 return 0; 809 } 810 811 threshold = 64; /* Half of the 7-bit sensor range */ 812 mtspr(SPR_THRM1, 0); 813 mtspr(SPR_THRM2, 0); 814 /* XXX This counter is supposed to be "at least 20 microseonds, in 815 * XXX units of clock cycles". Since we don't have convenient 816 * XXX access to the CPU speed, set it to a conservative value, 817 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 818 * XXX the fastest G3 processor is 700MHz) . The cost is that 819 * XXX measuring the temperature takes a bit longer. 820 */ 821 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 822 823 /* Successive-approximation code adapted from Motorola 824 * application note AN1800/D, "Programming the Thermal Assist 825 * Unit in the MPC750 Microprocessor". 826 */ 827 for (i = 4; i >= 0 ; i--) { 828 mtspr(SPR_THRM1, 829 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 830 count = 0; 831 while ((count < 100) && 832 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 833 count++; 834 delay(1); 835 } 836 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 837 /* The interrupt bit was set, meaning the 838 * temperature was above the threshold 839 */ 840 threshold += 2 << i; 841 } else { 842 /* Temperature was below the threshold */ 843 threshold -= 2 << i; 844 } 845 } 846 threshold += 2; 847 848 /* Convert the temperature in degrees C to microkelvin */ 849 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 850 851 *tred = *sme->sme_sensor_data; 852 853 return 0; 854 } 855 856 int 857 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 858 { 859 860 /* There is nothing to set here. */ 861 return (EINVAL); 862 } 863 #endif /* NSYSMON_ENVSYS > 0 */ 864