1 /* $NetBSD: cpu_subr.c,v 1.59 2010/11/06 11:46:01 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.59 2010/11/06 11:46:01 uebayasi Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/malloc.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/spr.h> 55 #include <powerpc/oea/hid.h> 56 #include <powerpc/oea/hid_601.h> 57 #include <powerpc/oea/spr.h> 58 #include <powerpc/oea/cpufeat.h> 59 60 #include <dev/sysmon/sysmonvar.h> 61 62 static void cpu_enable_l2cr(register_t); 63 static void cpu_enable_l3cr(register_t); 64 static void cpu_config_l2cr(int); 65 static void cpu_config_l3cr(int); 66 static void cpu_probe_speed(struct cpu_info *); 67 static void cpu_idlespin(void); 68 static void cpu_set_dfs_xcall(void *, void *); 69 #if NSYSMON_ENVSYS > 0 70 static void cpu_tau_setup(struct cpu_info *); 71 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 72 #endif 73 74 int cpu; 75 int ncpus; 76 77 struct fmttab { 78 register_t fmt_mask; 79 register_t fmt_value; 80 const char *fmt_string; 81 }; 82 83 /* 84 * This should be one per CPU but since we only support it on 750 variants it 85 * doesn't realy matter since none of them supports SMP 86 */ 87 envsys_data_t sensor; 88 89 static const struct fmttab cpu_7450_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 256KB L2 cache" }, 95 { L2CR_L2PE, 0, " no parity" }, 96 { L2CR_L2PE, ~0, " parity enabled" }, 97 { 0, 0, NULL } 98 }; 99 100 static const struct fmttab cpu_7448_l2cr_formats[] = { 101 { L2CR_L2E, 0, " disabled" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 105 { L2CR_L2E, ~0, " 1MB L2 cache" }, 106 { L2CR_L2PE, 0, " no parity" }, 107 { L2CR_L2PE, ~0, " parity enabled" }, 108 { 0, 0, NULL } 109 }; 110 111 static const struct fmttab cpu_7457_l2cr_formats[] = { 112 { L2CR_L2E, 0, " disabled" }, 113 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 116 { L2CR_L2E, ~0, " 512KB L2 cache" }, 117 { L2CR_L2PE, 0, " no parity" }, 118 { L2CR_L2PE, ~0, " parity enabled" }, 119 { 0, 0, NULL } 120 }; 121 122 static const struct fmttab cpu_7450_l3cr_formats[] = { 123 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 126 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 127 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 128 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 131 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 132 { L3CR_L3SIZ, ~0, " L3 cache" }, 133 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 134 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 135 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 136 { L3CR_L3CLK, ~0, " at" }, 137 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 138 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 139 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 140 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 141 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 142 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 143 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 144 { L3CR_L3CLK, ~0, " ratio" }, 145 { 0, 0, NULL }, 146 }; 147 148 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 149 { L2CR_L2E, 0, " disabled" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 153 { 0, ~0, " 512KB" }, 154 { L2CR_L2WT, L2CR_L2WT, " WT" }, 155 { L2CR_L2WT, 0, " WB" }, 156 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 157 { 0, ~0, " L2 cache" }, 158 { 0, 0, NULL } 159 }; 160 161 static const struct fmttab cpu_l2cr_formats[] = { 162 { L2CR_L2E, 0, " disabled" }, 163 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 166 { L2CR_L2PE, L2CR_L2PE, " parity" }, 167 { L2CR_L2PE, 0, " no-parity" }, 168 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 169 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 170 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 171 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 172 { L2CR_L2WT, L2CR_L2WT, " WT" }, 173 { L2CR_L2WT, 0, " WB" }, 174 { L2CR_L2E, ~0, " L2 cache" }, 175 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 176 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 177 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 178 { L2CR_L2CLK, ~0, " at" }, 179 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 180 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 181 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 182 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 183 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 184 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 185 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 186 { L2CR_L2CLK, ~0, " ratio" }, 187 { 0, 0, NULL } 188 }; 189 190 static void cpu_fmttab_print(const struct fmttab *, register_t); 191 192 struct cputab { 193 const char name[8]; 194 uint16_t version; 195 uint16_t revfmt; 196 }; 197 #define REVFMT_MAJMIN 1 /* %u.%u */ 198 #define REVFMT_HEX 2 /* 0x%04x */ 199 #define REVFMT_DEC 3 /* %u */ 200 static const struct cputab models[] = { 201 { "601", MPC601, REVFMT_DEC }, 202 { "602", MPC602, REVFMT_DEC }, 203 { "603", MPC603, REVFMT_MAJMIN }, 204 { "603e", MPC603e, REVFMT_MAJMIN }, 205 { "603ev", MPC603ev, REVFMT_MAJMIN }, 206 { "G2", MPCG2, REVFMT_MAJMIN }, 207 { "604", MPC604, REVFMT_MAJMIN }, 208 { "604e", MPC604e, REVFMT_MAJMIN }, 209 { "604ev", MPC604ev, REVFMT_MAJMIN }, 210 { "620", MPC620, REVFMT_HEX }, 211 { "750", MPC750, REVFMT_MAJMIN }, 212 { "750FX", IBM750FX, REVFMT_MAJMIN }, 213 { "7400", MPC7400, REVFMT_MAJMIN }, 214 { "7410", MPC7410, REVFMT_MAJMIN }, 215 { "7450", MPC7450, REVFMT_MAJMIN }, 216 { "7455", MPC7455, REVFMT_MAJMIN }, 217 { "7457", MPC7457, REVFMT_MAJMIN }, 218 { "7447A", MPC7447A, REVFMT_MAJMIN }, 219 { "7448", MPC7448, REVFMT_MAJMIN }, 220 { "8240", MPC8240, REVFMT_MAJMIN }, 221 { "8245", MPC8245, REVFMT_MAJMIN }, 222 { "970", IBM970, REVFMT_MAJMIN }, 223 { "970FX", IBM970FX, REVFMT_MAJMIN }, 224 { "970MP", IBM970MP, REVFMT_MAJMIN }, 225 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 226 { "", 0, REVFMT_HEX } 227 }; 228 229 #ifdef MULTIPROCESSOR 230 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 231 volatile struct cpu_hatch_data *cpu_hatch_data; 232 volatile int cpu_hatch_stack; 233 extern int ticks_per_intr; 234 #include <powerpc/oea/bat.h> 235 #include <arch/powerpc/pic/picvar.h> 236 #include <arch/powerpc/pic/ipivar.h> 237 extern struct bat battable[]; 238 #else 239 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 240 #endif /*MULTIPROCESSOR*/ 241 242 int cpu_altivec; 243 int cpu_psluserset, cpu_pslusermod; 244 char cpu_model[80]; 245 246 /* This is to be called from locore.S, and nowhere else. */ 247 248 void 249 cpu_model_init(void) 250 { 251 u_int pvr, vers; 252 253 pvr = mfpvr(); 254 vers = pvr >> 16; 255 256 oeacpufeat = 0; 257 258 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 259 vers == IBMCELL || vers == IBMPOWER6P5) 260 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 261 262 else if (vers == MPC601) 263 oeacpufeat |= OEACPU_601; 264 265 else if (MPC745X_P(vers) && vers != MPC7450) 266 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 267 } 268 269 void 270 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 271 { 272 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 273 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 274 (data & fmt->fmt_mask) == fmt->fmt_value) 275 aprint_normal("%s", fmt->fmt_string); 276 } 277 } 278 279 void 280 cpu_idlespin(void) 281 { 282 register_t msr; 283 284 if (powersave <= 0) 285 return; 286 287 __asm volatile( 288 "sync;" 289 "mfmsr %0;" 290 "oris %0,%0,%1@h;" /* enter power saving mode */ 291 "mtmsr %0;" 292 "isync;" 293 : "=r"(msr) 294 : "J"(PSL_POW)); 295 } 296 297 void 298 cpu_probe_cache(void) 299 { 300 u_int assoc, pvr, vers; 301 302 pvr = mfpvr(); 303 vers = pvr >> 16; 304 305 306 /* Presently common across almost all implementations. */ 307 curcpu()->ci_ci.dcache_line_size = 32; 308 curcpu()->ci_ci.icache_line_size = 32; 309 310 311 switch (vers) { 312 #define K *1024 313 case IBM750FX: 314 case MPC601: 315 case MPC750: 316 case MPC7400: 317 case MPC7447A: 318 case MPC7448: 319 case MPC7450: 320 case MPC7455: 321 case MPC7457: 322 curcpu()->ci_ci.dcache_size = 32 K; 323 curcpu()->ci_ci.icache_size = 32 K; 324 assoc = 8; 325 break; 326 case MPC603: 327 curcpu()->ci_ci.dcache_size = 8 K; 328 curcpu()->ci_ci.icache_size = 8 K; 329 assoc = 2; 330 break; 331 case MPC603e: 332 case MPC603ev: 333 case MPC604: 334 case MPC8240: 335 case MPC8245: 336 case MPCG2: 337 curcpu()->ci_ci.dcache_size = 16 K; 338 curcpu()->ci_ci.icache_size = 16 K; 339 assoc = 4; 340 break; 341 case MPC604e: 342 case MPC604ev: 343 curcpu()->ci_ci.dcache_size = 32 K; 344 curcpu()->ci_ci.icache_size = 32 K; 345 assoc = 4; 346 break; 347 case IBMPOWER3II: 348 curcpu()->ci_ci.dcache_size = 64 K; 349 curcpu()->ci_ci.icache_size = 32 K; 350 curcpu()->ci_ci.dcache_line_size = 128; 351 curcpu()->ci_ci.icache_line_size = 128; 352 assoc = 128; /* not a typo */ 353 break; 354 case IBM970: 355 case IBM970FX: 356 case IBM970MP: 357 curcpu()->ci_ci.dcache_size = 32 K; 358 curcpu()->ci_ci.icache_size = 64 K; 359 curcpu()->ci_ci.dcache_line_size = 128; 360 curcpu()->ci_ci.icache_line_size = 128; 361 assoc = 2; 362 break; 363 364 default: 365 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 366 curcpu()->ci_ci.icache_size = PAGE_SIZE; 367 assoc = 1; 368 #undef K 369 } 370 371 /* 372 * Possibly recolor. 373 */ 374 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 375 } 376 377 struct cpu_info * 378 cpu_attach_common(struct device *self, int id) 379 { 380 struct cpu_info *ci; 381 u_int pvr, vers; 382 383 ci = &cpu_info[id]; 384 #ifndef MULTIPROCESSOR 385 /* 386 * If this isn't the primary CPU, print an error message 387 * and just bail out. 388 */ 389 if (id != 0) { 390 aprint_normal(": ID %d\n", id); 391 aprint_normal("%s: processor off-line; multiprocessor support " 392 "not present in kernel\n", self->dv_xname); 393 return (NULL); 394 } 395 #endif 396 397 ci->ci_cpuid = id; 398 ci->ci_intrdepth = -1; 399 ci->ci_dev = self; 400 ci->ci_idlespin = cpu_idlespin; 401 402 pvr = mfpvr(); 403 vers = (pvr >> 16) & 0xffff; 404 405 switch (id) { 406 case 0: 407 /* load my cpu_number to PIR */ 408 switch (vers) { 409 case MPC601: 410 case MPC604: 411 case MPC604e: 412 case MPC604ev: 413 case MPC7400: 414 case MPC7410: 415 case MPC7447A: 416 case MPC7448: 417 case MPC7450: 418 case MPC7455: 419 case MPC7457: 420 mtspr(SPR_PIR, id); 421 } 422 cpu_setup(self, ci); 423 break; 424 default: 425 if (id >= CPU_MAXNUM) { 426 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 427 panic("cpuattach"); 428 } 429 #ifndef MULTIPROCESSOR 430 aprint_normal(" not configured\n"); 431 return NULL; 432 #else 433 mi_cpu_attach(ci); 434 break; 435 #endif 436 } 437 return (ci); 438 } 439 440 void 441 cpu_setup(struct device *self, struct cpu_info *ci) 442 { 443 u_int hid0, hid0_save, pvr, vers; 444 const char *bitmask; 445 char hidbuf[128]; 446 char model[80]; 447 448 pvr = mfpvr(); 449 vers = (pvr >> 16) & 0xffff; 450 451 cpu_identify(model, sizeof(model)); 452 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 453 cpu_number() == 0 ? " (primary)" : ""); 454 455 /* set the cpu number */ 456 ci->ci_cpuid = cpu_number(); 457 hid0_save = hid0 = mfspr(SPR_HID0); 458 459 cpu_probe_cache(); 460 461 /* 462 * Configure power-saving mode. 463 */ 464 switch (vers) { 465 case MPC604: 466 case MPC604e: 467 case MPC604ev: 468 /* 469 * Do not have HID0 support settings, but can support 470 * MSR[POW] off 471 */ 472 powersave = 1; 473 break; 474 475 case MPC603: 476 case MPC603e: 477 case MPC603ev: 478 case MPC7400: 479 case MPC7410: 480 case MPC8240: 481 case MPC8245: 482 case MPCG2: 483 /* Select DOZE mode. */ 484 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 485 hid0 |= HID0_DOZE | HID0_DPM; 486 powersave = 1; 487 break; 488 489 case MPC750: 490 case IBM750FX: 491 /* Select NAP mode. */ 492 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 493 hid0 |= HID0_NAP | HID0_DPM; 494 powersave = 1; 495 break; 496 497 case MPC7447A: 498 case MPC7448: 499 case MPC7457: 500 case MPC7455: 501 case MPC7450: 502 /* Enable the 7450 branch caches */ 503 hid0 |= HID0_SGE | HID0_BTIC; 504 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 505 /* Enable more and larger BAT registers */ 506 if (oeacpufeat & OEACPU_XBSEN) 507 hid0 |= HID0_XBSEN; 508 if (oeacpufeat & OEACPU_HIGHBAT) 509 hid0 |= HID0_HIGH_BAT_EN; 510 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 511 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 512 hid0 &= ~HID0_BTIC; 513 /* Select NAP mode. */ 514 hid0 &= ~HID0_SLEEP; 515 hid0 |= HID0_NAP | HID0_DPM; 516 powersave = 1; 517 break; 518 519 case IBM970: 520 case IBM970FX: 521 case IBM970MP: 522 case IBMPOWER3II: 523 default: 524 /* No power-saving mode is available. */ ; 525 } 526 527 #ifdef NAPMODE 528 switch (vers) { 529 case IBM750FX: 530 case MPC750: 531 case MPC7400: 532 /* Select NAP mode. */ 533 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 534 hid0 |= HID0_NAP; 535 break; 536 } 537 #endif 538 539 switch (vers) { 540 case IBM750FX: 541 case MPC750: 542 hid0 &= ~HID0_DBP; /* XXX correct? */ 543 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 544 break; 545 546 case MPC7400: 547 case MPC7410: 548 hid0 &= ~HID0_SPD; 549 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 550 hid0 |= HID0_EIEC; 551 break; 552 } 553 554 if (hid0 != hid0_save) { 555 mtspr(SPR_HID0, hid0); 556 __asm volatile("sync;isync"); 557 } 558 559 560 switch (vers) { 561 case MPC601: 562 bitmask = HID0_601_BITMASK; 563 break; 564 case MPC7450: 565 case MPC7455: 566 case MPC7457: 567 bitmask = HID0_7450_BITMASK; 568 break; 569 case IBM970: 570 case IBM970FX: 571 case IBM970MP: 572 bitmask = 0; 573 break; 574 default: 575 bitmask = HID0_BITMASK; 576 break; 577 } 578 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 579 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 580 powersave); 581 582 ci->ci_khz = 0; 583 584 /* 585 * Display speed and cache configuration. 586 */ 587 switch (vers) { 588 case MPC604: 589 case MPC604e: 590 case MPC604ev: 591 case MPC750: 592 case IBM750FX: 593 case MPC7400: 594 case MPC7410: 595 case MPC7447A: 596 case MPC7448: 597 case MPC7450: 598 case MPC7455: 599 case MPC7457: 600 aprint_normal("%s: ", self->dv_xname); 601 cpu_probe_speed(ci); 602 aprint_normal("%u.%02u MHz", 603 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 604 switch (vers) { 605 case MPC7450: /* 7441 does not have L3! */ 606 case MPC7455: /* 7445 does not have L3! */ 607 case MPC7457: /* 7447 does not have L3! */ 608 cpu_config_l3cr(vers); 609 break; 610 case IBM750FX: 611 case MPC750: 612 case MPC7400: 613 case MPC7410: 614 case MPC7447A: 615 case MPC7448: 616 cpu_config_l2cr(pvr); 617 break; 618 default: 619 break; 620 } 621 aprint_normal("\n"); 622 break; 623 } 624 625 #if NSYSMON_ENVSYS > 0 626 /* 627 * Attach MPC750 temperature sensor to the envsys subsystem. 628 * XXX the 74xx series also has this sensor, but it is not 629 * XXX supported by Motorola and may return values that are off by 630 * XXX 35-55 degrees C. 631 */ 632 if (vers == MPC750 || vers == IBM750FX) 633 cpu_tau_setup(ci); 634 #endif 635 636 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 637 NULL, self->dv_xname, "clock"); 638 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 639 NULL, self->dv_xname, "soft clock"); 640 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 641 NULL, self->dv_xname, "soft net"); 642 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 643 NULL, self->dv_xname, "soft serial"); 644 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 645 NULL, self->dv_xname, "traps"); 646 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 647 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 648 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 649 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 650 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 651 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 652 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 653 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 654 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 655 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 656 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 657 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 658 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 659 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 660 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 661 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 662 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 663 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 664 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 665 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 666 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 667 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 668 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 669 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 670 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 671 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 672 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 673 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 674 #ifdef ALTIVEC 675 if (cpu_altivec) { 676 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 677 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 678 } 679 #endif 680 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 681 NULL, self->dv_xname, "IPIs"); 682 } 683 684 /* 685 * According to a document labeled "PVR Register Settings": 686 ** For integrated microprocessors the PVR register inside the device 687 ** will identify the version of the microprocessor core. You must also 688 ** read the Device ID, PCI register 02, to identify the part and the 689 ** Revision ID, PCI register 08, to identify the revision of the 690 ** integrated microprocessor. 691 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 692 */ 693 694 void 695 cpu_identify(char *str, size_t len) 696 { 697 u_int pvr, major, minor; 698 uint16_t vers, rev, revfmt; 699 const struct cputab *cp; 700 const char *name; 701 size_t n; 702 703 pvr = mfpvr(); 704 vers = pvr >> 16; 705 rev = pvr; 706 707 switch (vers) { 708 case MPC7410: 709 minor = (pvr >> 0) & 0xff; 710 major = minor <= 4 ? 1 : 2; 711 break; 712 case MPCG2: /*XXX see note above */ 713 major = (pvr >> 4) & 0xf; 714 minor = (pvr >> 0) & 0xf; 715 break; 716 default: 717 major = (pvr >> 8) & 0xf; 718 minor = (pvr >> 0) & 0xf; 719 } 720 721 for (cp = models; cp->name[0] != '\0'; cp++) { 722 if (cp->version == vers) 723 break; 724 } 725 726 if (str == NULL) { 727 str = cpu_model; 728 len = sizeof(cpu_model); 729 cpu = vers; 730 } 731 732 revfmt = cp->revfmt; 733 name = cp->name; 734 if (rev == MPC750 && pvr == 15) { 735 name = "755"; 736 revfmt = REVFMT_HEX; 737 } 738 739 if (cp->name[0] != '\0') { 740 n = snprintf(str, len, "%s (Revision ", cp->name); 741 } else { 742 n = snprintf(str, len, "Version %#x (Revision ", vers); 743 } 744 if (len > n) { 745 switch (revfmt) { 746 case REVFMT_MAJMIN: 747 snprintf(str + n, len - n, "%u.%u)", major, minor); 748 break; 749 case REVFMT_HEX: 750 snprintf(str + n, len - n, "0x%04x)", rev); 751 break; 752 case REVFMT_DEC: 753 snprintf(str + n, len - n, "%u)", rev); 754 break; 755 } 756 } 757 } 758 759 #ifdef L2CR_CONFIG 760 u_int l2cr_config = L2CR_CONFIG; 761 #else 762 u_int l2cr_config = 0; 763 #endif 764 765 #ifdef L3CR_CONFIG 766 u_int l3cr_config = L3CR_CONFIG; 767 #else 768 u_int l3cr_config = 0; 769 #endif 770 771 void 772 cpu_enable_l2cr(register_t l2cr) 773 { 774 register_t msr, x; 775 uint16_t vers; 776 777 vers = mfpvr() >> 16; 778 779 /* Disable interrupts and set the cache config bits. */ 780 msr = mfmsr(); 781 mtmsr(msr & ~PSL_EE); 782 #ifdef ALTIVEC 783 if (cpu_altivec) 784 __asm volatile("dssall"); 785 #endif 786 __asm volatile("sync"); 787 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 788 __asm volatile("sync"); 789 790 /* Wait for L2 clock to be stable (640 L2 clocks). */ 791 delay(100); 792 793 /* Invalidate all L2 contents. */ 794 if (MPC745X_P(vers)) { 795 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 796 do { 797 x = mfspr(SPR_L2CR); 798 } while (x & L2CR_L2I); 799 } else { 800 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 801 do { 802 x = mfspr(SPR_L2CR); 803 } while (x & L2CR_L2IP); 804 } 805 /* Enable L2 cache. */ 806 l2cr |= L2CR_L2E; 807 mtspr(SPR_L2CR, l2cr); 808 mtmsr(msr); 809 } 810 811 void 812 cpu_enable_l3cr(register_t l3cr) 813 { 814 register_t x; 815 816 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 817 818 /* 819 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 820 * L3CLKEN. (also mask off reserved bits in case they were included 821 * in L3CR_CONFIG) 822 */ 823 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 824 mtspr(SPR_L3CR, l3cr); 825 826 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 827 l3cr |= 0x04000000; 828 mtspr(SPR_L3CR, l3cr); 829 830 /* 3: Set L3CLKEN to 1*/ 831 l3cr |= L3CR_L3CLKEN; 832 mtspr(SPR_L3CR, l3cr); 833 834 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 835 __asm volatile("dssall;sync"); 836 /* L3 cache is already disabled, no need to clear L3E */ 837 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 838 do { 839 x = mfspr(SPR_L3CR); 840 } while (x & L3CR_L3I); 841 842 /* 6: Clear L3CLKEN to 0 */ 843 l3cr &= ~L3CR_L3CLKEN; 844 mtspr(SPR_L3CR, l3cr); 845 846 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 847 __asm volatile("sync"); 848 delay(100); 849 850 /* 8: Set L3E and L3CLKEN */ 851 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 852 mtspr(SPR_L3CR, l3cr); 853 854 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 855 __asm volatile("sync"); 856 delay(100); 857 } 858 859 void 860 cpu_config_l2cr(int pvr) 861 { 862 register_t l2cr; 863 u_int vers = (pvr >> 16) & 0xffff; 864 865 l2cr = mfspr(SPR_L2CR); 866 867 /* 868 * For MP systems, the firmware may only configure the L2 cache 869 * on the first CPU. In this case, assume that the other CPUs 870 * should use the same value for L2CR. 871 */ 872 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 873 l2cr_config = l2cr; 874 } 875 876 /* 877 * Configure L2 cache if not enabled. 878 */ 879 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 880 cpu_enable_l2cr(l2cr_config); 881 l2cr = mfspr(SPR_L2CR); 882 } 883 884 if ((l2cr & L2CR_L2E) == 0) { 885 aprint_normal(" L2 cache present but not enabled "); 886 return; 887 } 888 aprint_normal(","); 889 890 switch (vers) { 891 case IBM750FX: 892 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 893 break; 894 case MPC750: 895 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 896 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 897 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 898 else 899 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 900 break; 901 case MPC7447A: 902 case MPC7457: 903 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 904 return; 905 case MPC7448: 906 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 907 return; 908 case MPC7450: 909 case MPC7455: 910 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 911 break; 912 default: 913 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 914 break; 915 } 916 } 917 918 void 919 cpu_config_l3cr(int vers) 920 { 921 register_t l2cr; 922 register_t l3cr; 923 924 l2cr = mfspr(SPR_L2CR); 925 926 /* 927 * For MP systems, the firmware may only configure the L2 cache 928 * on the first CPU. In this case, assume that the other CPUs 929 * should use the same value for L2CR. 930 */ 931 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 932 l2cr_config = l2cr; 933 } 934 935 /* 936 * Configure L2 cache if not enabled. 937 */ 938 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 939 cpu_enable_l2cr(l2cr_config); 940 l2cr = mfspr(SPR_L2CR); 941 } 942 943 aprint_normal(","); 944 switch (vers) { 945 case MPC7447A: 946 case MPC7457: 947 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 948 return; 949 case MPC7448: 950 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 951 return; 952 default: 953 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 954 break; 955 } 956 957 l3cr = mfspr(SPR_L3CR); 958 959 /* 960 * For MP systems, the firmware may only configure the L3 cache 961 * on the first CPU. In this case, assume that the other CPUs 962 * should use the same value for L3CR. 963 */ 964 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 965 l3cr_config = l3cr; 966 } 967 968 /* 969 * Configure L3 cache if not enabled. 970 */ 971 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 972 cpu_enable_l3cr(l3cr_config); 973 l3cr = mfspr(SPR_L3CR); 974 } 975 976 if (l3cr & L3CR_L3E) { 977 aprint_normal(","); 978 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 979 } 980 } 981 982 void 983 cpu_probe_speed(struct cpu_info *ci) 984 { 985 uint64_t cps; 986 987 mtspr(SPR_MMCR0, MMCR0_FC); 988 mtspr(SPR_PMC1, 0); 989 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 990 delay(100000); 991 cps = (mfspr(SPR_PMC1) * 10) + 4999; 992 993 mtspr(SPR_MMCR0, MMCR0_FC); 994 995 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 996 } 997 998 /* 999 * Read the Dynamic Frequency Switching state and return a divisor for 1000 * the maximum frequency. 1001 */ 1002 int 1003 cpu_get_dfs(void) 1004 { 1005 u_int pvr, vers; 1006 1007 pvr = mfpvr(); 1008 vers = pvr >> 16; 1009 1010 switch (vers) { 1011 case MPC7448: 1012 if (mfspr(SPR_HID1) & HID1_DFS4) 1013 return 4; 1014 case MPC7447A: 1015 if (mfspr(SPR_HID1) & HID1_DFS2) 1016 return 2; 1017 } 1018 return 1; 1019 } 1020 1021 /* 1022 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1023 */ 1024 void 1025 cpu_set_dfs(int div) 1026 { 1027 uint64_t where; 1028 u_int dfs_mask, pvr, vers; 1029 1030 pvr = mfpvr(); 1031 vers = pvr >> 16; 1032 dfs_mask = 0; 1033 1034 switch (vers) { 1035 case MPC7448: 1036 dfs_mask |= HID1_DFS4; 1037 case MPC7447A: 1038 dfs_mask |= HID1_DFS2; 1039 break; 1040 default: 1041 printf("cpu_set_dfs: DFS not supported\n"); 1042 return; 1043 1044 } 1045 1046 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1047 xc_wait(where); 1048 } 1049 1050 static void 1051 cpu_set_dfs_xcall(void *arg1, void *arg2) 1052 { 1053 u_int dfs_mask, hid1, old_hid1; 1054 int *divisor, s; 1055 1056 divisor = arg1; 1057 dfs_mask = *(u_int *)arg2; 1058 1059 s = splhigh(); 1060 hid1 = old_hid1 = mfspr(SPR_HID1); 1061 1062 switch (*divisor) { 1063 case 1: 1064 hid1 &= ~dfs_mask; 1065 break; 1066 case 2: 1067 hid1 &= ~(dfs_mask & HID1_DFS4); 1068 hid1 |= dfs_mask & HID1_DFS2; 1069 break; 1070 case 4: 1071 hid1 &= ~(dfs_mask & HID1_DFS2); 1072 hid1 |= dfs_mask & HID1_DFS4; 1073 break; 1074 } 1075 1076 if (hid1 != old_hid1) { 1077 __asm volatile("sync"); 1078 mtspr(SPR_HID1, hid1); 1079 __asm volatile("sync;isync"); 1080 } 1081 1082 splx(s); 1083 } 1084 1085 #if NSYSMON_ENVSYS > 0 1086 void 1087 cpu_tau_setup(struct cpu_info *ci) 1088 { 1089 struct sysmon_envsys *sme; 1090 int error, therm_delay; 1091 1092 mtspr(SPR_THRM1, SPR_THRM_VALID); 1093 mtspr(SPR_THRM2, 0); 1094 1095 /* 1096 * we need to figure out how much 20+us in units of CPU clock cycles 1097 * are 1098 */ 1099 1100 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1101 1102 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1103 1104 sme = sysmon_envsys_create(); 1105 1106 sensor.units = ENVSYS_STEMP; 1107 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1108 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1109 sysmon_envsys_destroy(sme); 1110 return; 1111 } 1112 1113 sme->sme_name = ci->ci_dev->dv_xname; 1114 sme->sme_cookie = ci; 1115 sme->sme_refresh = cpu_tau_refresh; 1116 1117 if ((error = sysmon_envsys_register(sme)) != 0) { 1118 aprint_error("%s: unable to register with sysmon (%d)\n", 1119 ci->ci_dev->dv_xname, error); 1120 sysmon_envsys_destroy(sme); 1121 } 1122 } 1123 1124 1125 /* Find the temperature of the CPU. */ 1126 void 1127 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1128 { 1129 int i, threshold, count; 1130 1131 threshold = 64; /* Half of the 7-bit sensor range */ 1132 1133 /* Successive-approximation code adapted from Motorola 1134 * application note AN1800/D, "Programming the Thermal Assist 1135 * Unit in the MPC750 Microprocessor". 1136 */ 1137 for (i = 5; i >= 0 ; i--) { 1138 mtspr(SPR_THRM1, 1139 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1140 count = 0; 1141 while ((count < 100000) && 1142 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1143 count++; 1144 delay(1); 1145 } 1146 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1147 /* The interrupt bit was set, meaning the 1148 * temperature was above the threshold 1149 */ 1150 threshold += 1 << i; 1151 } else { 1152 /* Temperature was below the threshold */ 1153 threshold -= 1 << i; 1154 } 1155 1156 } 1157 threshold += 2; 1158 1159 /* Convert the temperature in degrees C to microkelvin */ 1160 edata->value_cur = (threshold * 1000000) + 273150000; 1161 edata->state = ENVSYS_SVALID; 1162 } 1163 #endif /* NSYSMON_ENVSYS > 0 */ 1164 1165 #ifdef MULTIPROCESSOR 1166 extern volatile u_int cpu_spinstart_ack; 1167 1168 int 1169 cpu_spinup(struct device *self, struct cpu_info *ci) 1170 { 1171 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1172 struct pglist mlist; 1173 int i, error, pvr, vers; 1174 char *cp, *hp; 1175 1176 pvr = mfpvr(); 1177 vers = pvr >> 16; 1178 KASSERT(ci != curcpu()); 1179 1180 /* 1181 * Allocate some contiguous pages for the intteup PCB and stack 1182 * from the lowest 256MB (because bat0 always maps it va == pa). 1183 * Must be 16 byte aligned. 1184 */ 1185 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1186 &mlist, 1, 1); 1187 if (error) { 1188 aprint_error(": unable to allocate idle stack\n"); 1189 return -1; 1190 } 1191 1192 KASSERT(ci != &cpu_info[0]); 1193 1194 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1195 memset(cp, 0, INTSTK); 1196 1197 ci->ci_intstk = cp; 1198 1199 /* Now allocate a hatch stack */ 1200 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1201 &mlist, 1, 1); 1202 if (error) { 1203 aprint_error(": unable to allocate hatch stack\n"); 1204 return -1; 1205 } 1206 1207 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1208 memset(hp, 0, 0x1000); 1209 1210 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1211 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1212 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1213 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1214 1215 cpu_hatch_data = h; 1216 h->running = 0; 1217 h->self = self; 1218 h->ci = ci; 1219 h->pir = ci->ci_cpuid; 1220 1221 cpu_hatch_stack = (uint32_t)hp; 1222 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1223 1224 /* copy special registers */ 1225 1226 h->hid0 = mfspr(SPR_HID0); 1227 1228 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1229 for (i = 0; i < 16; i++) { 1230 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1231 "r"(i << ADDR_SR_SHFT)); 1232 } 1233 if (oeacpufeat & OEACPU_64) 1234 h->asr = mfspr(SPR_ASR); 1235 else 1236 h->asr = 0; 1237 1238 /* copy the bat regs */ 1239 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1240 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1241 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1242 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1243 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1244 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1245 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1246 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1247 __asm volatile ("sync; isync"); 1248 1249 if (md_setup_trampoline(h, ci) == -1) 1250 return -1; 1251 md_presync_timebase(h); 1252 md_start_timebase(h); 1253 1254 /* wait for secondary printf */ 1255 1256 delay(200000); 1257 1258 if (h->running < 1) { 1259 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1260 ci->ci_cpuid, cpu_spinstart_ack); 1261 Debugger(); 1262 return -1; 1263 } 1264 1265 /* Register IPI Interrupt */ 1266 if (ipiops.ppc_establish_ipi) 1267 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1268 1269 return 0; 1270 } 1271 1272 static volatile int start_secondary_cpu; 1273 extern void tlbia(void); 1274 1275 register_t 1276 cpu_hatch(void) 1277 { 1278 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1279 struct cpu_info * const ci = h->ci; 1280 struct pcb *pcb; 1281 u_int msr; 1282 int i; 1283 1284 /* Initialize timebase. */ 1285 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1286 1287 /* 1288 * Set PIR (Processor Identification Register). i.e. whoami 1289 * Note that PIR is read-only on some CPU versions, so we write to it 1290 * only if it has a different value than we need. 1291 */ 1292 1293 msr = mfspr(SPR_PIR); 1294 if (msr != h->pir) 1295 mtspr(SPR_PIR, h->pir); 1296 1297 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1298 cpu_spinstart_ack = 0; 1299 1300 /* Initialize MMU. */ 1301 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1302 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1303 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1304 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1305 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1306 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1307 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1308 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1309 1310 mtspr(SPR_HID0, h->hid0); 1311 1312 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1313 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1314 1315 __asm volatile ("sync"); 1316 for (i = 0; i < 16; i++) 1317 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1318 __asm volatile ("sync; isync"); 1319 1320 if (oeacpufeat & OEACPU_64) 1321 mtspr(SPR_ASR, h->asr); 1322 1323 cpu_spinstart_ack = 1; 1324 __asm ("ptesync"); 1325 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1326 __asm volatile ("sync; isync"); 1327 1328 cpu_spinstart_ack = 5; 1329 for (i = 0; i < 16; i++) 1330 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1331 "r"(i << ADDR_SR_SHFT)); 1332 1333 /* Enable I/D address translations. */ 1334 msr = mfmsr(); 1335 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1336 mtmsr(msr); 1337 __asm volatile ("sync; isync"); 1338 cpu_spinstart_ack = 2; 1339 1340 md_sync_timebase(h); 1341 1342 cpu_setup(h->self, ci); 1343 1344 h->running = 1; 1345 __asm volatile ("sync; isync"); 1346 1347 while (start_secondary_cpu == 0) 1348 ; 1349 1350 __asm volatile ("sync; isync"); 1351 1352 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1353 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1354 1355 md_setup_interrupts(); 1356 1357 ci->ci_ipending = 0; 1358 ci->ci_cpl = 0; 1359 1360 mtmsr(mfmsr() | PSL_EE); 1361 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1362 return pcb->pcb_sp; 1363 } 1364 1365 void 1366 cpu_boot_secondary_processors(void) 1367 { 1368 start_secondary_cpu = 1; 1369 __asm volatile ("sync"); 1370 } 1371 1372 #endif /*MULTIPROCESSOR*/ 1373