1 /* $NetBSD: cpu_subr.c,v 1.51 2008/12/16 22:35:25 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.51 2008/12/16 22:35:25 christos Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/cpufeat.h> 58 59 #include <dev/sysmon/sysmonvar.h> 60 61 static void cpu_enable_l2cr(register_t); 62 static void cpu_enable_l3cr(register_t); 63 static void cpu_config_l2cr(int); 64 static void cpu_config_l3cr(int); 65 static void cpu_probe_speed(struct cpu_info *); 66 static void cpu_idlespin(void); 67 #if NSYSMON_ENVSYS > 0 68 static void cpu_tau_setup(struct cpu_info *); 69 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 70 #endif 71 72 int cpu; 73 int ncpus; 74 75 struct fmttab { 76 register_t fmt_mask; 77 register_t fmt_value; 78 const char *fmt_string; 79 }; 80 81 /* 82 * This should be one per CPU but since we only support it on 750 variants it 83 * doesn't realy matter since none of them supports SMP 84 */ 85 envsys_data_t sensor; 86 87 static const struct fmttab cpu_7450_l2cr_formats[] = { 88 { L2CR_L2E, 0, " disabled" }, 89 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 92 { L2CR_L2E, ~0, " 256KB L2 cache" }, 93 { L2CR_L2PE, 0, " no parity" }, 94 { L2CR_L2PE, ~0, " parity enabled" }, 95 { 0, 0, NULL } 96 }; 97 98 static const struct fmttab cpu_7448_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 1MB L2 cache" }, 104 { L2CR_L2PE, 0, " no parity" }, 105 { L2CR_L2PE, ~0, " parity enabled" }, 106 { 0, 0, NULL } 107 }; 108 109 static const struct fmttab cpu_7457_l2cr_formats[] = { 110 { L2CR_L2E, 0, " disabled" }, 111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 113 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 114 { L2CR_L2E, ~0, " 512KB L2 cache" }, 115 { L2CR_L2PE, 0, " no parity" }, 116 { L2CR_L2PE, ~0, " parity enabled" }, 117 { 0, 0, NULL } 118 }; 119 120 static const struct fmttab cpu_7450_l3cr_formats[] = { 121 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 122 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 123 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 124 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 125 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 126 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 127 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 128 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 129 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 130 { L3CR_L3SIZ, ~0, " L3 cache" }, 131 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 132 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 133 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 134 { L3CR_L3CLK, ~0, " at" }, 135 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 136 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 137 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 138 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 139 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 140 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 141 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 142 { L3CR_L3CLK, ~0, " ratio" }, 143 { 0, 0, NULL }, 144 }; 145 146 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { 0, ~0, " 512KB" }, 152 { L2CR_L2WT, L2CR_L2WT, " WT" }, 153 { L2CR_L2WT, 0, " WB" }, 154 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 155 { 0, ~0, " L2 cache" }, 156 { 0, 0, NULL } 157 }; 158 159 static const struct fmttab cpu_l2cr_formats[] = { 160 { L2CR_L2E, 0, " disabled" }, 161 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 162 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 163 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 164 { L2CR_L2PE, L2CR_L2PE, " parity" }, 165 { L2CR_L2PE, 0, " no-parity" }, 166 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 167 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 168 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 169 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 170 { L2CR_L2WT, L2CR_L2WT, " WT" }, 171 { L2CR_L2WT, 0, " WB" }, 172 { L2CR_L2E, ~0, " L2 cache" }, 173 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 174 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 175 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 176 { L2CR_L2CLK, ~0, " at" }, 177 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 178 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 179 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 180 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 181 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 182 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 183 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 184 { L2CR_L2CLK, ~0, " ratio" }, 185 { 0, 0, NULL } 186 }; 187 188 static void cpu_fmttab_print(const struct fmttab *, register_t); 189 190 struct cputab { 191 const char name[8]; 192 uint16_t version; 193 uint16_t revfmt; 194 }; 195 #define REVFMT_MAJMIN 1 /* %u.%u */ 196 #define REVFMT_HEX 2 /* 0x%04x */ 197 #define REVFMT_DEC 3 /* %u */ 198 static const struct cputab models[] = { 199 { "601", MPC601, REVFMT_DEC }, 200 { "602", MPC602, REVFMT_DEC }, 201 { "603", MPC603, REVFMT_MAJMIN }, 202 { "603e", MPC603e, REVFMT_MAJMIN }, 203 { "603ev", MPC603ev, REVFMT_MAJMIN }, 204 { "G2", MPCG2, REVFMT_MAJMIN }, 205 { "604", MPC604, REVFMT_MAJMIN }, 206 { "604e", MPC604e, REVFMT_MAJMIN }, 207 { "604ev", MPC604ev, REVFMT_MAJMIN }, 208 { "620", MPC620, REVFMT_HEX }, 209 { "750", MPC750, REVFMT_MAJMIN }, 210 { "750FX", IBM750FX, REVFMT_MAJMIN }, 211 { "7400", MPC7400, REVFMT_MAJMIN }, 212 { "7410", MPC7410, REVFMT_MAJMIN }, 213 { "7450", MPC7450, REVFMT_MAJMIN }, 214 { "7455", MPC7455, REVFMT_MAJMIN }, 215 { "7457", MPC7457, REVFMT_MAJMIN }, 216 { "7447A", MPC7447A, REVFMT_MAJMIN }, 217 { "7448", MPC7448, REVFMT_MAJMIN }, 218 { "8240", MPC8240, REVFMT_MAJMIN }, 219 { "8245", MPC8245, REVFMT_MAJMIN }, 220 { "970", IBM970, REVFMT_MAJMIN }, 221 { "970FX", IBM970FX, REVFMT_MAJMIN }, 222 { "970MP", IBM970MP, REVFMT_MAJMIN }, 223 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 224 { "", 0, REVFMT_HEX } 225 }; 226 227 #ifdef MULTIPROCESSOR 228 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 229 volatile struct cpu_hatch_data *cpu_hatch_data; 230 volatile int cpu_hatch_stack; 231 extern int ticks_per_intr; 232 #include <powerpc/oea/bat.h> 233 #include <arch/powerpc/pic/picvar.h> 234 #include <arch/powerpc/pic/ipivar.h> 235 extern struct bat battable[]; 236 #else 237 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 238 #endif /*MULTIPROCESSOR*/ 239 240 int cpu_altivec; 241 int cpu_psluserset, cpu_pslusermod; 242 char cpu_model[80]; 243 244 /* This is to be called from locore.S, and nowhere else. */ 245 246 void 247 cpu_model_init(void) 248 { 249 u_int pvr, vers; 250 251 pvr = mfpvr(); 252 vers = pvr >> 16; 253 254 oeacpufeat = 0; 255 256 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 257 vers == IBMCELL || vers == IBMPOWER6P5) 258 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 259 260 else if (vers == MPC601) 261 oeacpufeat |= OEACPU_601; 262 263 else if (MPC745X_P(vers) && vers != MPC7450) 264 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 265 } 266 267 void 268 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 269 { 270 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 271 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 272 (data & fmt->fmt_mask) == fmt->fmt_value) 273 aprint_normal("%s", fmt->fmt_string); 274 } 275 } 276 277 void 278 cpu_idlespin(void) 279 { 280 register_t msr; 281 282 if (powersave <= 0) 283 return; 284 285 __asm volatile( 286 "sync;" 287 "mfmsr %0;" 288 "oris %0,%0,%1@h;" /* enter power saving mode */ 289 "mtmsr %0;" 290 "isync;" 291 : "=r"(msr) 292 : "J"(PSL_POW)); 293 } 294 295 void 296 cpu_probe_cache(void) 297 { 298 u_int assoc, pvr, vers; 299 300 pvr = mfpvr(); 301 vers = pvr >> 16; 302 303 304 /* Presently common across almost all implementations. */ 305 curcpu()->ci_ci.dcache_line_size = 32; 306 curcpu()->ci_ci.icache_line_size = 32; 307 308 309 switch (vers) { 310 #define K *1024 311 case IBM750FX: 312 case MPC601: 313 case MPC750: 314 case MPC7400: 315 case MPC7447A: 316 case MPC7448: 317 case MPC7450: 318 case MPC7455: 319 case MPC7457: 320 curcpu()->ci_ci.dcache_size = 32 K; 321 curcpu()->ci_ci.icache_size = 32 K; 322 assoc = 8; 323 break; 324 case MPC603: 325 curcpu()->ci_ci.dcache_size = 8 K; 326 curcpu()->ci_ci.icache_size = 8 K; 327 assoc = 2; 328 break; 329 case MPC603e: 330 case MPC603ev: 331 case MPC604: 332 case MPC8240: 333 case MPC8245: 334 case MPCG2: 335 curcpu()->ci_ci.dcache_size = 16 K; 336 curcpu()->ci_ci.icache_size = 16 K; 337 assoc = 4; 338 break; 339 case MPC604e: 340 case MPC604ev: 341 curcpu()->ci_ci.dcache_size = 32 K; 342 curcpu()->ci_ci.icache_size = 32 K; 343 assoc = 4; 344 break; 345 case IBMPOWER3II: 346 curcpu()->ci_ci.dcache_size = 64 K; 347 curcpu()->ci_ci.icache_size = 32 K; 348 curcpu()->ci_ci.dcache_line_size = 128; 349 curcpu()->ci_ci.icache_line_size = 128; 350 assoc = 128; /* not a typo */ 351 break; 352 case IBM970: 353 case IBM970FX: 354 case IBM970MP: 355 curcpu()->ci_ci.dcache_size = 32 K; 356 curcpu()->ci_ci.icache_size = 64 K; 357 curcpu()->ci_ci.dcache_line_size = 128; 358 curcpu()->ci_ci.icache_line_size = 128; 359 assoc = 2; 360 break; 361 362 default: 363 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 364 curcpu()->ci_ci.icache_size = PAGE_SIZE; 365 assoc = 1; 366 #undef K 367 } 368 369 /* 370 * Possibly recolor. 371 */ 372 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 373 } 374 375 struct cpu_info * 376 cpu_attach_common(struct device *self, int id) 377 { 378 struct cpu_info *ci; 379 u_int pvr, vers; 380 381 ci = &cpu_info[id]; 382 #ifndef MULTIPROCESSOR 383 /* 384 * If this isn't the primary CPU, print an error message 385 * and just bail out. 386 */ 387 if (id != 0) { 388 aprint_normal(": ID %d\n", id); 389 aprint_normal("%s: processor off-line; multiprocessor support " 390 "not present in kernel\n", self->dv_xname); 391 return (NULL); 392 } 393 #endif 394 395 ci->ci_cpuid = id; 396 ci->ci_intrdepth = -1; 397 ci->ci_dev = self; 398 ci->ci_idlespin = cpu_idlespin; 399 400 pvr = mfpvr(); 401 vers = (pvr >> 16) & 0xffff; 402 403 switch (id) { 404 case 0: 405 /* load my cpu_number to PIR */ 406 switch (vers) { 407 case MPC601: 408 case MPC604: 409 case MPC604e: 410 case MPC604ev: 411 case MPC7400: 412 case MPC7410: 413 case MPC7447A: 414 case MPC7448: 415 case MPC7450: 416 case MPC7455: 417 case MPC7457: 418 mtspr(SPR_PIR, id); 419 } 420 cpu_setup(self, ci); 421 break; 422 default: 423 if (id >= CPU_MAXNUM) { 424 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 425 panic("cpuattach"); 426 } 427 #ifndef MULTIPROCESSOR 428 aprint_normal(" not configured\n"); 429 return NULL; 430 #else 431 mi_cpu_attach(ci); 432 break; 433 #endif 434 } 435 return (ci); 436 } 437 438 void 439 cpu_setup(self, ci) 440 struct device *self; 441 struct cpu_info *ci; 442 { 443 u_int hid0, hid0_save, pvr, vers; 444 const char *bitmask; 445 char hidbuf[128]; 446 char model[80]; 447 448 pvr = mfpvr(); 449 vers = (pvr >> 16) & 0xffff; 450 451 cpu_identify(model, sizeof(model)); 452 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 453 cpu_number() == 0 ? " (primary)" : ""); 454 455 /* set the cpu number */ 456 ci->ci_cpuid = cpu_number(); 457 hid0_save = hid0 = mfspr(SPR_HID0); 458 459 cpu_probe_cache(); 460 461 /* 462 * Configure power-saving mode. 463 */ 464 switch (vers) { 465 case MPC604: 466 case MPC604e: 467 case MPC604ev: 468 /* 469 * Do not have HID0 support settings, but can support 470 * MSR[POW] off 471 */ 472 powersave = 1; 473 break; 474 475 case MPC603: 476 case MPC603e: 477 case MPC603ev: 478 case MPC750: 479 case IBM750FX: 480 case MPC7400: 481 case MPC7410: 482 case MPC8240: 483 case MPC8245: 484 case MPCG2: 485 /* Select DOZE mode. */ 486 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 487 hid0 |= HID0_DOZE | HID0_DPM; 488 powersave = 1; 489 break; 490 491 case MPC7447A: 492 case MPC7448: 493 case MPC7457: 494 case MPC7455: 495 case MPC7450: 496 /* Enable the 7450 branch caches */ 497 hid0 |= HID0_SGE | HID0_BTIC; 498 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 499 /* Enable more and larger BAT registers */ 500 if (oeacpufeat & OEACPU_XBSEN) 501 hid0 |= HID0_XBSEN; 502 if (oeacpufeat & OEACPU_HIGHBAT) 503 hid0 |= HID0_HIGH_BAT_EN; 504 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 505 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 506 hid0 &= ~HID0_BTIC; 507 /* Select NAP mode. */ 508 hid0 &= ~HID0_SLEEP; 509 hid0 |= HID0_NAP | HID0_DPM; 510 powersave = 1; 511 break; 512 513 case IBM970: 514 case IBM970FX: 515 case IBM970MP: 516 case IBMPOWER3II: 517 default: 518 /* No power-saving mode is available. */ ; 519 } 520 521 #ifdef NAPMODE 522 switch (vers) { 523 case IBM750FX: 524 case MPC750: 525 case MPC7400: 526 /* Select NAP mode. */ 527 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 528 hid0 |= HID0_NAP; 529 break; 530 } 531 #endif 532 533 switch (vers) { 534 case IBM750FX: 535 case MPC750: 536 hid0 &= ~HID0_DBP; /* XXX correct? */ 537 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 538 break; 539 540 case MPC7400: 541 case MPC7410: 542 hid0 &= ~HID0_SPD; 543 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 544 hid0 |= HID0_EIEC; 545 break; 546 } 547 548 if (hid0 != hid0_save) { 549 mtspr(SPR_HID0, hid0); 550 __asm volatile("sync;isync"); 551 } 552 553 554 switch (vers) { 555 case MPC601: 556 bitmask = HID0_601_BITMASK; 557 break; 558 case MPC7450: 559 case MPC7455: 560 case MPC7457: 561 bitmask = HID0_7450_BITMASK; 562 break; 563 case IBM970: 564 case IBM970FX: 565 case IBM970MP: 566 bitmask = 0; 567 break; 568 default: 569 bitmask = HID0_BITMASK; 570 break; 571 } 572 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 573 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 574 powersave); 575 576 ci->ci_khz = 0; 577 578 /* 579 * Display speed and cache configuration. 580 */ 581 switch (vers) { 582 case MPC604: 583 case MPC604e: 584 case MPC604ev: 585 case MPC750: 586 case IBM750FX: 587 case MPC7400: 588 case MPC7410: 589 case MPC7447A: 590 case MPC7448: 591 case MPC7450: 592 case MPC7455: 593 case MPC7457: 594 aprint_normal("%s: ", self->dv_xname); 595 cpu_probe_speed(ci); 596 aprint_normal("%u.%02u MHz", 597 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 598 switch (vers) { 599 case MPC7450: /* 7441 does not have L3! */ 600 case MPC7455: /* 7445 does not have L3! */ 601 case MPC7457: /* 7447 does not have L3! */ 602 cpu_config_l3cr(vers); 603 break; 604 case IBM750FX: 605 case MPC750: 606 case MPC7400: 607 case MPC7410: 608 case MPC7447A: 609 case MPC7448: 610 cpu_config_l2cr(pvr); 611 break; 612 default: 613 break; 614 } 615 aprint_normal("\n"); 616 break; 617 } 618 619 #if NSYSMON_ENVSYS > 0 620 /* 621 * Attach MPC750 temperature sensor to the envsys subsystem. 622 * XXX the 74xx series also has this sensor, but it is not 623 * XXX supported by Motorola and may return values that are off by 624 * XXX 35-55 degrees C. 625 */ 626 if (vers == MPC750 || vers == IBM750FX) 627 cpu_tau_setup(ci); 628 #endif 629 630 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 631 NULL, self->dv_xname, "clock"); 632 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 633 NULL, self->dv_xname, "soft clock"); 634 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 635 NULL, self->dv_xname, "soft net"); 636 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 637 NULL, self->dv_xname, "soft serial"); 638 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 639 NULL, self->dv_xname, "traps"); 640 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 641 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 642 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 643 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 644 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 645 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 646 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 647 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 648 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 649 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 650 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 651 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 652 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 653 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 654 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 655 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 656 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 657 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 658 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 659 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 660 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 661 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 662 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 663 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 664 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 665 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 666 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 667 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 668 #ifdef ALTIVEC 669 if (cpu_altivec) { 670 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 671 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 672 } 673 #endif 674 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 675 NULL, self->dv_xname, "IPIs"); 676 } 677 678 /* 679 * According to a document labeled "PVR Register Settings": 680 ** For integrated microprocessors the PVR register inside the device 681 ** will identify the version of the microprocessor core. You must also 682 ** read the Device ID, PCI register 02, to identify the part and the 683 ** Revision ID, PCI register 08, to identify the revision of the 684 ** integrated microprocessor. 685 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 686 */ 687 688 void 689 cpu_identify(char *str, size_t len) 690 { 691 u_int pvr, major, minor; 692 uint16_t vers, rev, revfmt; 693 const struct cputab *cp; 694 const char *name; 695 size_t n; 696 697 pvr = mfpvr(); 698 vers = pvr >> 16; 699 rev = pvr; 700 701 switch (vers) { 702 case MPC7410: 703 minor = (pvr >> 0) & 0xff; 704 major = minor <= 4 ? 1 : 2; 705 break; 706 case MPCG2: /*XXX see note above */ 707 major = (pvr >> 4) & 0xf; 708 minor = (pvr >> 0) & 0xf; 709 break; 710 default: 711 major = (pvr >> 8) & 0xf; 712 minor = (pvr >> 0) & 0xf; 713 } 714 715 for (cp = models; cp->name[0] != '\0'; cp++) { 716 if (cp->version == vers) 717 break; 718 } 719 720 if (str == NULL) { 721 str = cpu_model; 722 len = sizeof(cpu_model); 723 cpu = vers; 724 } 725 726 revfmt = cp->revfmt; 727 name = cp->name; 728 if (rev == MPC750 && pvr == 15) { 729 name = "755"; 730 revfmt = REVFMT_HEX; 731 } 732 733 if (cp->name[0] != '\0') { 734 n = snprintf(str, len, "%s (Revision ", cp->name); 735 } else { 736 n = snprintf(str, len, "Version %#x (Revision ", vers); 737 } 738 if (len > n) { 739 switch (revfmt) { 740 case REVFMT_MAJMIN: 741 snprintf(str + n, len - n, "%u.%u)", major, minor); 742 break; 743 case REVFMT_HEX: 744 snprintf(str + n, len - n, "0x%04x)", rev); 745 break; 746 case REVFMT_DEC: 747 snprintf(str + n, len - n, "%u)", rev); 748 break; 749 } 750 } 751 } 752 753 #ifdef L2CR_CONFIG 754 u_int l2cr_config = L2CR_CONFIG; 755 #else 756 u_int l2cr_config = 0; 757 #endif 758 759 #ifdef L3CR_CONFIG 760 u_int l3cr_config = L3CR_CONFIG; 761 #else 762 u_int l3cr_config = 0; 763 #endif 764 765 void 766 cpu_enable_l2cr(register_t l2cr) 767 { 768 register_t msr, x; 769 uint16_t vers; 770 771 vers = mfpvr() >> 16; 772 773 /* Disable interrupts and set the cache config bits. */ 774 msr = mfmsr(); 775 mtmsr(msr & ~PSL_EE); 776 #ifdef ALTIVEC 777 if (cpu_altivec) 778 __asm volatile("dssall"); 779 #endif 780 __asm volatile("sync"); 781 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 782 __asm volatile("sync"); 783 784 /* Wait for L2 clock to be stable (640 L2 clocks). */ 785 delay(100); 786 787 /* Invalidate all L2 contents. */ 788 if (MPC745X_P(vers)) { 789 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 790 do { 791 x = mfspr(SPR_L2CR); 792 } while (x & L2CR_L2I); 793 } else { 794 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 795 do { 796 x = mfspr(SPR_L2CR); 797 } while (x & L2CR_L2IP); 798 } 799 /* Enable L2 cache. */ 800 l2cr |= L2CR_L2E; 801 mtspr(SPR_L2CR, l2cr); 802 mtmsr(msr); 803 } 804 805 void 806 cpu_enable_l3cr(register_t l3cr) 807 { 808 register_t x; 809 810 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 811 812 /* 813 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 814 * L3CLKEN. (also mask off reserved bits in case they were included 815 * in L3CR_CONFIG) 816 */ 817 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 818 mtspr(SPR_L3CR, l3cr); 819 820 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 821 l3cr |= 0x04000000; 822 mtspr(SPR_L3CR, l3cr); 823 824 /* 3: Set L3CLKEN to 1*/ 825 l3cr |= L3CR_L3CLKEN; 826 mtspr(SPR_L3CR, l3cr); 827 828 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 829 __asm volatile("dssall;sync"); 830 /* L3 cache is already disabled, no need to clear L3E */ 831 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 832 do { 833 x = mfspr(SPR_L3CR); 834 } while (x & L3CR_L3I); 835 836 /* 6: Clear L3CLKEN to 0 */ 837 l3cr &= ~L3CR_L3CLKEN; 838 mtspr(SPR_L3CR, l3cr); 839 840 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 841 __asm volatile("sync"); 842 delay(100); 843 844 /* 8: Set L3E and L3CLKEN */ 845 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 846 mtspr(SPR_L3CR, l3cr); 847 848 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 849 __asm volatile("sync"); 850 delay(100); 851 } 852 853 void 854 cpu_config_l2cr(int pvr) 855 { 856 register_t l2cr; 857 u_int vers = (pvr >> 16) & 0xffff; 858 859 l2cr = mfspr(SPR_L2CR); 860 861 /* 862 * For MP systems, the firmware may only configure the L2 cache 863 * on the first CPU. In this case, assume that the other CPUs 864 * should use the same value for L2CR. 865 */ 866 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 867 l2cr_config = l2cr; 868 } 869 870 /* 871 * Configure L2 cache if not enabled. 872 */ 873 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 874 cpu_enable_l2cr(l2cr_config); 875 l2cr = mfspr(SPR_L2CR); 876 } 877 878 if ((l2cr & L2CR_L2E) == 0) { 879 aprint_normal(" L2 cache present but not enabled "); 880 return; 881 } 882 aprint_normal(","); 883 884 switch (vers) { 885 case IBM750FX: 886 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 887 break; 888 case MPC750: 889 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 890 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 891 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 892 else 893 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 894 break; 895 case MPC7447A: 896 case MPC7457: 897 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 898 return; 899 case MPC7448: 900 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 901 return; 902 case MPC7450: 903 case MPC7455: 904 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 905 break; 906 default: 907 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 908 break; 909 } 910 } 911 912 void 913 cpu_config_l3cr(int vers) 914 { 915 register_t l2cr; 916 register_t l3cr; 917 918 l2cr = mfspr(SPR_L2CR); 919 920 /* 921 * For MP systems, the firmware may only configure the L2 cache 922 * on the first CPU. In this case, assume that the other CPUs 923 * should use the same value for L2CR. 924 */ 925 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 926 l2cr_config = l2cr; 927 } 928 929 /* 930 * Configure L2 cache if not enabled. 931 */ 932 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 933 cpu_enable_l2cr(l2cr_config); 934 l2cr = mfspr(SPR_L2CR); 935 } 936 937 aprint_normal(","); 938 switch (vers) { 939 case MPC7447A: 940 case MPC7457: 941 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 942 return; 943 case MPC7448: 944 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 945 return; 946 default: 947 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 948 break; 949 } 950 951 l3cr = mfspr(SPR_L3CR); 952 953 /* 954 * For MP systems, the firmware may only configure the L3 cache 955 * on the first CPU. In this case, assume that the other CPUs 956 * should use the same value for L3CR. 957 */ 958 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 959 l3cr_config = l3cr; 960 } 961 962 /* 963 * Configure L3 cache if not enabled. 964 */ 965 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 966 cpu_enable_l3cr(l3cr_config); 967 l3cr = mfspr(SPR_L3CR); 968 } 969 970 if (l3cr & L3CR_L3E) { 971 aprint_normal(","); 972 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 973 } 974 } 975 976 void 977 cpu_probe_speed(struct cpu_info *ci) 978 { 979 uint64_t cps; 980 981 mtspr(SPR_MMCR0, MMCR0_FC); 982 mtspr(SPR_PMC1, 0); 983 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 984 delay(100000); 985 cps = (mfspr(SPR_PMC1) * 10) + 4999; 986 987 mtspr(SPR_MMCR0, MMCR0_FC); 988 989 ci->ci_khz = cps / 1000; 990 } 991 992 #if NSYSMON_ENVSYS > 0 993 void 994 cpu_tau_setup(struct cpu_info *ci) 995 { 996 struct sysmon_envsys *sme; 997 int error, therm_delay; 998 999 mtspr(SPR_THRM1, SPR_THRM_VALID); 1000 mtspr(SPR_THRM2, 0); 1001 1002 /* 1003 * we need to figure out how much 20+us in units of CPU clock cycles 1004 * are 1005 */ 1006 1007 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1008 1009 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1010 1011 sme = sysmon_envsys_create(); 1012 1013 sensor.units = ENVSYS_STEMP; 1014 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1015 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1016 sysmon_envsys_destroy(sme); 1017 return; 1018 } 1019 1020 sme->sme_name = ci->ci_dev->dv_xname; 1021 sme->sme_cookie = ci; 1022 sme->sme_refresh = cpu_tau_refresh; 1023 1024 if ((error = sysmon_envsys_register(sme)) != 0) { 1025 aprint_error("%s: unable to register with sysmon (%d)\n", 1026 ci->ci_dev->dv_xname, error); 1027 sysmon_envsys_destroy(sme); 1028 } 1029 } 1030 1031 1032 /* Find the temperature of the CPU. */ 1033 void 1034 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1035 { 1036 int i, threshold, count; 1037 1038 threshold = 64; /* Half of the 7-bit sensor range */ 1039 1040 /* Successive-approximation code adapted from Motorola 1041 * application note AN1800/D, "Programming the Thermal Assist 1042 * Unit in the MPC750 Microprocessor". 1043 */ 1044 for (i = 5; i >= 0 ; i--) { 1045 mtspr(SPR_THRM1, 1046 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1047 count = 0; 1048 while ((count < 100000) && 1049 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1050 count++; 1051 delay(1); 1052 } 1053 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1054 /* The interrupt bit was set, meaning the 1055 * temperature was above the threshold 1056 */ 1057 threshold += 1 << i; 1058 } else { 1059 /* Temperature was below the threshold */ 1060 threshold -= 1 << i; 1061 } 1062 1063 } 1064 threshold += 2; 1065 1066 /* Convert the temperature in degrees C to microkelvin */ 1067 edata->value_cur = (threshold * 1000000) + 273150000; 1068 edata->state = ENVSYS_SVALID; 1069 } 1070 #endif /* NSYSMON_ENVSYS > 0 */ 1071 1072 #ifdef MULTIPROCESSOR 1073 extern volatile u_int cpu_spinstart_ack; 1074 1075 int 1076 cpu_spinup(struct device *self, struct cpu_info *ci) 1077 { 1078 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1079 struct pglist mlist; 1080 int i, error, pvr, vers; 1081 char *cp, *hp; 1082 1083 pvr = mfpvr(); 1084 vers = pvr >> 16; 1085 KASSERT(ci != curcpu()); 1086 1087 /* 1088 * Allocate some contiguous pages for the intteup PCB and stack 1089 * from the lowest 256MB (because bat0 always maps it va == pa). 1090 * Must be 16 byte aligned. 1091 */ 1092 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1093 &mlist, 1, 1); 1094 if (error) { 1095 aprint_error(": unable to allocate idle stack\n"); 1096 return -1; 1097 } 1098 1099 KASSERT(ci != &cpu_info[0]); 1100 1101 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1102 memset(cp, 0, INTSTK); 1103 1104 ci->ci_intstk = cp; 1105 1106 /* Now allocate a hatch stack */ 1107 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1108 &mlist, 1, 1); 1109 if (error) { 1110 aprint_error(": unable to allocate hatch stack\n"); 1111 return -1; 1112 } 1113 1114 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1115 memset(hp, 0, 0x1000); 1116 1117 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1118 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1119 ci->ci_curpcb = &ci->ci_curlwp->l_addr->u_pcb; 1120 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1121 1122 cpu_hatch_data = h; 1123 h->running = 0; 1124 h->self = self; 1125 h->ci = ci; 1126 h->pir = ci->ci_cpuid; 1127 1128 cpu_hatch_stack = (uint32_t)hp; 1129 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1130 1131 /* copy special registers */ 1132 1133 h->hid0 = mfspr(SPR_HID0); 1134 1135 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1136 for (i = 0; i < 16; i++) { 1137 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1138 "r"(i << ADDR_SR_SHFT)); 1139 } 1140 if (oeacpufeat & OEACPU_64) 1141 h->asr = mfspr(SPR_ASR); 1142 else 1143 h->asr = 0; 1144 1145 /* copy the bat regs */ 1146 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1147 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1148 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1149 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1150 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1151 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1152 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1153 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1154 __asm volatile ("sync; isync"); 1155 1156 if (md_setup_trampoline(h, ci) == -1) 1157 return -1; 1158 md_presync_timebase(h); 1159 md_start_timebase(h); 1160 1161 /* wait for secondary printf */ 1162 1163 delay(200000); 1164 1165 if (h->running < 1) { 1166 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1167 ci->ci_cpuid, cpu_spinstart_ack); 1168 Debugger(); 1169 return -1; 1170 } 1171 1172 /* Register IPI Interrupt */ 1173 if (ipiops.ppc_establish_ipi) 1174 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1175 1176 return 0; 1177 } 1178 1179 static volatile int start_secondary_cpu; 1180 extern void tlbia(void); 1181 1182 register_t 1183 cpu_hatch(void) 1184 { 1185 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1186 struct cpu_info * const ci = h->ci; 1187 u_int msr; 1188 int i; 1189 1190 /* Initialize timebase. */ 1191 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1192 1193 /* 1194 * Set PIR (Processor Identification Register). i.e. whoami 1195 * Note that PIR is read-only on some CPU versions, so we write to it 1196 * only if it has a different value than we need. 1197 */ 1198 1199 msr = mfspr(SPR_PIR); 1200 if (msr != h->pir) 1201 mtspr(SPR_PIR, h->pir); 1202 1203 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1204 cpu_spinstart_ack = 0; 1205 1206 /* Initialize MMU. */ 1207 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1208 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1209 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1210 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1211 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1212 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1213 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1214 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1215 1216 mtspr(SPR_HID0, h->hid0); 1217 1218 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1219 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1220 1221 __asm volatile ("sync"); 1222 for (i = 0; i < 16; i++) 1223 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1224 __asm volatile ("sync; isync"); 1225 1226 if (oeacpufeat & OEACPU_64) 1227 mtspr(SPR_ASR, h->asr); 1228 1229 cpu_spinstart_ack = 1; 1230 __asm ("ptesync"); 1231 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1232 __asm volatile ("sync; isync"); 1233 1234 cpu_spinstart_ack = 5; 1235 for (i = 0; i < 16; i++) 1236 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1237 "r"(i << ADDR_SR_SHFT)); 1238 1239 /* Enable I/D address translations. */ 1240 msr = mfmsr(); 1241 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1242 mtmsr(msr); 1243 __asm volatile ("sync; isync"); 1244 cpu_spinstart_ack = 2; 1245 1246 md_sync_timebase(h); 1247 1248 cpu_setup(h->self, ci); 1249 1250 h->running = 1; 1251 __asm volatile ("sync; isync"); 1252 1253 while (start_secondary_cpu == 0) 1254 ; 1255 1256 __asm volatile ("sync; isync"); 1257 1258 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1259 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1260 1261 md_setup_interrupts(); 1262 1263 ci->ci_ipending = 0; 1264 ci->ci_cpl = 0; 1265 1266 mtmsr(mfmsr() | PSL_EE); 1267 return ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp; 1268 } 1269 1270 void 1271 cpu_boot_secondary_processors() 1272 { 1273 start_secondary_cpu = 1; 1274 __asm volatile ("sync"); 1275 } 1276 1277 #endif /*MULTIPROCESSOR*/ 1278