1 /* $NetBSD: cpu_subr.c,v 1.104 2020/07/06 10:31:23 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.104 2020/07/06 10:31:23 rin Exp $"); 38 39 #include "sysmon_envsys.h" 40 41 #ifdef _KERNEL_OPT 42 #include "opt_altivec.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_ppcarch.h" 45 #include "opt_ppccache.h" 46 #include "opt_ppcparam.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/types.h> 53 #include <sys/lwp.h> 54 #include <sys/xcall.h> 55 56 #include <uvm/uvm.h> 57 58 #include <powerpc/pcb.h> 59 #include <powerpc/psl.h> 60 #include <powerpc/spr.h> 61 #include <powerpc/oea/hid.h> 62 #include <powerpc/oea/hid_601.h> 63 #include <powerpc/oea/spr.h> 64 #include <powerpc/oea/cpufeat.h> 65 66 #include <dev/sysmon/sysmonvar.h> 67 68 static void cpu_enable_l2cr(register_t); 69 static void cpu_enable_l3cr(register_t); 70 static void cpu_config_l2cr(int); 71 static void cpu_config_l3cr(int); 72 static void cpu_probe_speed(struct cpu_info *); 73 static void cpu_idlespin(void); 74 static void cpu_set_dfs_xcall(void *, void *); 75 #if NSYSMON_ENVSYS > 0 76 static void cpu_tau_setup(struct cpu_info *); 77 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 78 #endif 79 80 extern void init_scom_speedctl(void); 81 82 int cpu = -1; 83 int ncpus; 84 85 struct fmttab { 86 register_t fmt_mask; 87 register_t fmt_value; 88 const char *fmt_string; 89 }; 90 91 /* 92 * This should be one per CPU but since we only support it on 750 variants it 93 * doesn't really matter since none of them support SMP 94 */ 95 envsys_data_t sensor; 96 97 static const struct fmttab cpu_7450_l2cr_formats[] = { 98 { L2CR_L2E, 0, " disabled" }, 99 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 102 { L2CR_L2E, ~0, " 256KB L2 cache" }, 103 { L2CR_L2PE, 0, " no parity" }, 104 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 105 { 0, 0, NULL } 106 }; 107 108 static const struct fmttab cpu_7448_l2cr_formats[] = { 109 { L2CR_L2E, 0, " disabled" }, 110 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 113 { L2CR_L2E, ~0, " 1MB L2 cache" }, 114 { L2CR_L2PE, 0, " no parity" }, 115 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 116 { 0, 0, NULL } 117 }; 118 119 static const struct fmttab cpu_7457_l2cr_formats[] = { 120 { L2CR_L2E, 0, " disabled" }, 121 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 122 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 123 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 124 { L2CR_L2E, ~0, " 512KB L2 cache" }, 125 { L2CR_L2PE, 0, " no parity" }, 126 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 127 { 0, 0, NULL } 128 }; 129 130 static const struct fmttab cpu_7450_l3cr_formats[] = { 131 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 132 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 133 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 134 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 135 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 136 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 137 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 138 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 139 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 140 { L3CR_L3SIZ, ~0, " L3 cache" }, 141 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 142 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 143 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 144 { L3CR_L3CLK, ~0, " at" }, 145 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 146 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 147 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 148 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 149 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 150 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 151 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 152 { L3CR_L3CLK, ~0, " ratio" }, 153 { 0, 0, NULL }, 154 }; 155 156 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 157 { L2CR_L2E, 0, " disabled" }, 158 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 159 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 160 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 161 { 0, ~0, " 512KB" }, 162 { L2CR_L2WT, L2CR_L2WT, " WT" }, 163 { L2CR_L2WT, 0, " WB" }, 164 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 165 { 0, ~0, " L2 cache" }, 166 { 0, 0, NULL } 167 }; 168 169 static const struct fmttab cpu_l2cr_formats[] = { 170 { L2CR_L2E, 0, " disabled" }, 171 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 172 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 173 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 174 { L2CR_L2PE, L2CR_L2PE, " parity" }, 175 { L2CR_L2PE, 0, " no-parity" }, 176 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 177 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 178 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 179 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 180 { L2CR_L2WT, L2CR_L2WT, " WT" }, 181 { L2CR_L2WT, 0, " WB" }, 182 { L2CR_L2E, ~0, " L2 cache" }, 183 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 184 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 185 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 186 { L2CR_L2CLK, ~0, " at" }, 187 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 188 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 189 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 190 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 191 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 192 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 193 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 194 { L2CR_L2CLK, ~0, " ratio" }, 195 { 0, 0, NULL } 196 }; 197 198 static void cpu_fmttab_print(const struct fmttab *, register_t); 199 200 struct cputab { 201 const char name[8]; 202 uint16_t version; 203 uint16_t revfmt; 204 }; 205 #define REVFMT_MAJMIN 1 /* %u.%u */ 206 #define REVFMT_HEX 2 /* 0x%04x */ 207 #define REVFMT_DEC 3 /* %u */ 208 static const struct cputab models[] = { 209 { "601", MPC601, REVFMT_DEC }, 210 { "602", MPC602, REVFMT_DEC }, 211 { "603", MPC603, REVFMT_MAJMIN }, 212 { "603e", MPC603e, REVFMT_MAJMIN }, 213 { "603ev", MPC603ev, REVFMT_MAJMIN }, 214 { "G2", MPCG2, REVFMT_MAJMIN }, 215 { "604", MPC604, REVFMT_MAJMIN }, 216 { "604e", MPC604e, REVFMT_MAJMIN }, 217 { "604ev", MPC604ev, REVFMT_MAJMIN }, 218 { "620", MPC620, REVFMT_HEX }, 219 { "750", MPC750, REVFMT_MAJMIN }, 220 { "750FX", IBM750FX, REVFMT_MAJMIN }, 221 { "750GX", IBM750GX, REVFMT_MAJMIN }, 222 { "7400", MPC7400, REVFMT_MAJMIN }, 223 { "7410", MPC7410, REVFMT_MAJMIN }, 224 { "7450", MPC7450, REVFMT_MAJMIN }, 225 { "7455", MPC7455, REVFMT_MAJMIN }, 226 { "7457", MPC7457, REVFMT_MAJMIN }, 227 { "7447A", MPC7447A, REVFMT_MAJMIN }, 228 { "7448", MPC7448, REVFMT_MAJMIN }, 229 { "8240", MPC8240, REVFMT_MAJMIN }, 230 { "8245", MPC8245, REVFMT_MAJMIN }, 231 { "970", IBM970, REVFMT_MAJMIN }, 232 { "970FX", IBM970FX, REVFMT_MAJMIN }, 233 { "970MP", IBM970MP, REVFMT_MAJMIN }, 234 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 235 { "", 0, REVFMT_HEX } 236 }; 237 238 #ifdef MULTIPROCESSOR 239 struct cpu_info cpu_info[CPU_MAXNUM] = { 240 [0] = { 241 .ci_curlwp = &lwp0, 242 }, 243 }; 244 volatile struct cpu_hatch_data *cpu_hatch_data; 245 volatile int cpu_hatch_stack; 246 #define HATCH_STACK_SIZE 0x1000 247 extern int ticks_per_intr; 248 #include <powerpc/oea/bat.h> 249 #include <powerpc/pic/picvar.h> 250 #include <powerpc/pic/ipivar.h> 251 extern struct bat battable[]; 252 #else 253 struct cpu_info cpu_info[1] = { 254 [0] = { 255 .ci_curlwp = &lwp0, 256 }, 257 }; 258 #endif /*MULTIPROCESSOR*/ 259 260 int cpu_altivec; 261 register_t cpu_psluserset; 262 register_t cpu_pslusermod; 263 register_t cpu_pslusermask = 0xffff; 264 265 /* This is to be called from locore.S, and nowhere else. */ 266 267 void 268 cpu_model_init(void) 269 { 270 u_int pvr, vers; 271 272 pvr = mfpvr(); 273 vers = pvr >> 16; 274 275 oeacpufeat = 0; 276 277 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 278 vers == IBMCELL || vers == IBMPOWER6P5) { 279 oeacpufeat |= OEACPU_64; 280 oeacpufeat |= OEACPU_64_BRIDGE; 281 oeacpufeat |= OEACPU_NOBAT; 282 283 } else if (vers == MPC601) { 284 oeacpufeat |= OEACPU_601; 285 286 } else if (MPC745X_P(vers)) { 287 register_t hid1 = mfspr(SPR_HID1); 288 289 if (vers != MPC7450) { 290 register_t hid0 = mfspr(SPR_HID0); 291 292 /* Enable more SPRG registers */ 293 oeacpufeat |= OEACPU_HIGHSPRG; 294 295 /* Enable more BAT registers */ 296 oeacpufeat |= OEACPU_HIGHBAT; 297 hid0 |= HID0_HIGH_BAT_EN; 298 299 /* Enable larger BAT registers */ 300 oeacpufeat |= OEACPU_XBSEN; 301 hid0 |= HID0_XBSEN; 302 303 mtspr(SPR_HID0, hid0); 304 __asm volatile("sync;isync"); 305 } 306 307 /* Enable address broadcasting for MP systems */ 308 hid1 |= HID1_SYNCBE | HID1_ABE; 309 310 mtspr(SPR_HID1, hid1); 311 __asm volatile("sync;isync"); 312 313 } else if (vers == IBM750FX || vers == IBM750GX) { 314 oeacpufeat |= OEACPU_HIGHBAT; 315 } 316 } 317 318 void 319 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 320 { 321 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 322 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 323 (data & fmt->fmt_mask) == fmt->fmt_value) 324 aprint_normal("%s", fmt->fmt_string); 325 } 326 } 327 328 void 329 cpu_idlespin(void) 330 { 331 register_t msr; 332 333 if (powersave <= 0) 334 return; 335 336 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 337 if (cpu_altivec) 338 __asm volatile("dssall"); 339 #endif 340 341 __asm volatile( 342 "sync;" 343 "mfmsr %0;" 344 "oris %0,%0,%1@h;" /* enter power saving mode */ 345 "mtmsr %0;" 346 "isync;" 347 : "=r"(msr) 348 : "J"(PSL_POW)); 349 } 350 351 void 352 cpu_probe_cache(void) 353 { 354 u_int assoc, pvr, vers; 355 356 pvr = mfpvr(); 357 vers = pvr >> 16; 358 359 360 /* Presently common across almost all implementations. */ 361 curcpu()->ci_ci.dcache_line_size = 32; 362 curcpu()->ci_ci.icache_line_size = 32; 363 364 365 switch (vers) { 366 #define K *1024 367 case IBM750FX: 368 case IBM750GX: 369 case MPC601: 370 case MPC750: 371 case MPC7400: 372 case MPC7447A: 373 case MPC7448: 374 case MPC7450: 375 case MPC7455: 376 case MPC7457: 377 curcpu()->ci_ci.dcache_size = 32 K; 378 curcpu()->ci_ci.icache_size = 32 K; 379 assoc = 8; 380 break; 381 case MPC603: 382 curcpu()->ci_ci.dcache_size = 8 K; 383 curcpu()->ci_ci.icache_size = 8 K; 384 assoc = 2; 385 break; 386 case MPC603e: 387 case MPC603ev: 388 case MPC604: 389 case MPC8240: 390 case MPC8245: 391 case MPCG2: 392 curcpu()->ci_ci.dcache_size = 16 K; 393 curcpu()->ci_ci.icache_size = 16 K; 394 assoc = 4; 395 break; 396 case MPC604e: 397 case MPC604ev: 398 curcpu()->ci_ci.dcache_size = 32 K; 399 curcpu()->ci_ci.icache_size = 32 K; 400 assoc = 4; 401 break; 402 case IBMPOWER3II: 403 curcpu()->ci_ci.dcache_size = 64 K; 404 curcpu()->ci_ci.icache_size = 32 K; 405 curcpu()->ci_ci.dcache_line_size = 128; 406 curcpu()->ci_ci.icache_line_size = 128; 407 assoc = 128; /* not a typo */ 408 break; 409 case IBM970: 410 case IBM970FX: 411 case IBM970MP: 412 curcpu()->ci_ci.dcache_size = 32 K; 413 curcpu()->ci_ci.icache_size = 64 K; 414 curcpu()->ci_ci.dcache_line_size = 128; 415 curcpu()->ci_ci.icache_line_size = 128; 416 assoc = 2; 417 break; 418 419 default: 420 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 421 curcpu()->ci_ci.icache_size = PAGE_SIZE; 422 assoc = 1; 423 #undef K 424 } 425 426 /* 427 * Possibly recolor. 428 */ 429 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 430 } 431 432 struct cpu_info * 433 cpu_attach_common(device_t self, int id) 434 { 435 struct cpu_info *ci; 436 u_int pvr, vers; 437 438 ci = &cpu_info[id]; 439 #ifndef MULTIPROCESSOR 440 /* 441 * If this isn't the primary CPU, print an error message 442 * and just bail out. 443 */ 444 if (id != 0) { 445 aprint_naive("\n"); 446 aprint_normal(": ID %d\n", id); 447 aprint_normal_dev(self, 448 "processor off-line; " 449 "multiprocessor support not present in kernel\n"); 450 return (NULL); 451 } 452 #endif 453 454 ci->ci_cpuid = id; 455 ci->ci_idepth = -1; 456 ci->ci_dev = self; 457 ci->ci_idlespin = cpu_idlespin; 458 459 #ifdef MULTIPROCESSOR 460 /* Register IPI Interrupt */ 461 if ((ipiops.ppc_establish_ipi) && (id == 0)) 462 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 463 #endif 464 465 pvr = mfpvr(); 466 vers = (pvr >> 16) & 0xffff; 467 468 switch (id) { 469 case 0: 470 /* load my cpu_number to PIR */ 471 switch (vers) { 472 case MPC601: 473 case MPC604: 474 case MPC604e: 475 case MPC604ev: 476 case MPC7400: 477 case MPC7410: 478 case MPC7447A: 479 case MPC7448: 480 case MPC7450: 481 case MPC7455: 482 case MPC7457: 483 mtspr(SPR_PIR, id); 484 } 485 cpu_setup(self, ci); 486 break; 487 default: 488 aprint_naive("\n"); 489 if (id >= CPU_MAXNUM) { 490 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 491 panic("cpuattach"); 492 } 493 #ifndef MULTIPROCESSOR 494 aprint_normal(" not configured\n"); 495 return NULL; 496 #else 497 mi_cpu_attach(ci); 498 break; 499 #endif 500 } 501 return (ci); 502 } 503 504 void 505 cpu_setup(device_t self, struct cpu_info *ci) 506 { 507 u_int pvr, vers; 508 const char * const xname = device_xname(self); 509 const char *bitmask; 510 char hidbuf[128]; 511 char model[80]; 512 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 513 char hidbuf_u[128]; 514 const char *bitmasku = NULL; 515 volatile uint64_t hid64_0, hid64_0_save; 516 #endif 517 #if !defined(_ARCH_PPC64) 518 register_t hid0 = 0, hid0_save = 0; 519 #endif 520 521 pvr = mfpvr(); 522 vers = (pvr >> 16) & 0xffff; 523 524 cpu_identify(model, sizeof(model)); 525 aprint_naive("\n"); 526 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 527 cpu_number() == 0 ? " (primary)" : ""); 528 529 /* set the cpu number */ 530 ci->ci_cpuid = cpu_number(); 531 #if defined(_ARCH_PPC64) 532 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 533 hid64_0_save = hid64_0; 534 #else 535 #if defined(PPC_OEA64_BRIDGE) 536 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 537 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 538 else 539 #endif 540 hid0_save = hid0 = mfspr(SPR_HID0); 541 #endif 542 543 544 cpu_probe_cache(); 545 546 /* 547 * Configure power-saving mode. 548 */ 549 switch (vers) { 550 #if !defined(_ARCH_PPC64) 551 case MPC604: 552 case MPC604e: 553 case MPC604ev: 554 /* 555 * Do not have HID0 support settings, but can support 556 * MSR[POW] off 557 */ 558 powersave = 1; 559 break; 560 561 case MPC603: 562 case MPC603e: 563 case MPC603ev: 564 case MPC7400: 565 case MPC7410: 566 case MPC8240: 567 case MPC8245: 568 case MPCG2: 569 /* Select DOZE mode. */ 570 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 571 hid0 |= HID0_DOZE | HID0_DPM; 572 powersave = 1; 573 break; 574 575 case MPC750: 576 case IBM750FX: 577 case IBM750GX: 578 /* Select NAP mode. */ 579 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 580 hid0 |= HID0_NAP | HID0_DPM; 581 powersave = 1; 582 break; 583 584 case MPC7447A: 585 case MPC7448: 586 case MPC7457: 587 case MPC7455: 588 case MPC7450: 589 /* Enable the 7450 branch caches */ 590 hid0 |= HID0_SGE | HID0_BTIC; 591 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 592 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 593 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 594 hid0 &= ~HID0_BTIC; 595 /* Select NAP mode. */ 596 hid0 &= ~HID0_SLEEP; 597 /* XXX my quicksilver hangs if nap is enabled */ 598 if (vers != MPC7450) { 599 hid0 |= HID0_NAP | HID0_DPM; 600 powersave = 1; 601 } 602 break; 603 #endif 604 605 case IBM970: 606 case IBM970FX: 607 case IBM970MP: 608 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 609 #if !defined(_ARCH_PPC64) 610 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 611 #endif 612 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 613 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 614 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 615 powersave = 1; 616 break; 617 #endif 618 case IBMPOWER3II: 619 default: 620 /* No power-saving mode is available. */ ; 621 } 622 623 #ifdef NAPMODE 624 switch (vers) { 625 case IBM750FX: 626 case IBM750GX: 627 case MPC750: 628 case MPC7400: 629 /* Select NAP mode. */ 630 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 631 hid0 |= HID0_NAP; 632 break; 633 } 634 #endif 635 636 switch (vers) { 637 case IBM750FX: 638 case IBM750GX: 639 case MPC750: 640 hid0 &= ~HID0_DBP; /* XXX correct? */ 641 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 642 break; 643 644 case MPC7400: 645 case MPC7410: 646 hid0 &= ~HID0_SPD; 647 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 648 hid0 |= HID0_EIEC; 649 break; 650 } 651 652 /* 653 * according to the 603e manual this is necessary for an external L2 654 * cache to work properly 655 */ 656 switch (vers) { 657 case MPC603e: 658 hid0 |= HID0_ABE; 659 } 660 661 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 662 #if defined(PPC_OEA64_BRIDGE) 663 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 664 #endif 665 if (hid64_0 != hid64_0_save) { 666 mtspr64(SPR_HID0, hid64_0); 667 } 668 #if defined(PPC_OEA64_BRIDGE) 669 } else { 670 #endif 671 #endif 672 673 #if !defined(_ARCH_PPC64) 674 if (hid0 != hid0_save) { 675 mtspr(SPR_HID0, hid0); 676 __asm volatile("sync;isync"); 677 } 678 #endif 679 #if defined(PPC_OEA64_BRIDGE) 680 } 681 #endif 682 683 switch (vers) { 684 case MPC601: 685 bitmask = HID0_601_BITMASK; 686 break; 687 case MPC7447A: 688 case MPC7448: 689 case MPC7450: 690 case MPC7455: 691 case MPC7457: 692 bitmask = HID0_7450_BITMASK; 693 break; 694 case IBM970: 695 case IBM970FX: 696 case IBM970MP: 697 bitmask = HID0_970_BITMASK; 698 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 699 bitmasku = HID0_970_BITMASK_U; 700 #endif 701 break; 702 default: 703 bitmask = HID0_BITMASK; 704 break; 705 } 706 707 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 708 if (bitmasku != NULL) { 709 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 710 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 711 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 712 hidbuf_u, hidbuf, powersave); 713 } else 714 #endif 715 { 716 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 717 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 718 hidbuf, powersave); 719 } 720 721 ci->ci_khz = 0; 722 723 /* 724 * Display speed and cache configuration. 725 */ 726 switch (vers) { 727 case MPC604: 728 case MPC604e: 729 case MPC604ev: 730 case MPC750: 731 case IBM750FX: 732 case IBM750GX: 733 case MPC7400: 734 case MPC7410: 735 case MPC7447A: 736 case MPC7448: 737 case MPC7450: 738 case MPC7455: 739 case MPC7457: 740 aprint_normal_dev(self, ""); 741 cpu_probe_speed(ci); 742 aprint_normal("%u.%02u MHz", 743 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 744 switch (vers) { 745 case MPC7450: /* 7441 does not have L3! */ 746 case MPC7455: /* 7445 does not have L3! */ 747 case MPC7457: /* 7447 does not have L3! */ 748 cpu_config_l3cr(vers); 749 break; 750 case IBM750FX: 751 case IBM750GX: 752 case MPC750: 753 case MPC7400: 754 case MPC7410: 755 case MPC7447A: 756 case MPC7448: 757 cpu_config_l2cr(pvr); 758 break; 759 default: 760 break; 761 } 762 aprint_normal("\n"); 763 break; 764 } 765 766 #if NSYSMON_ENVSYS > 0 767 /* 768 * Attach MPC750 temperature sensor to the envsys subsystem. 769 * XXX the 74xx series also has this sensor, but it is not 770 * XXX supported by Motorola and may return values that are off by 771 * XXX 35-55 degrees C. 772 */ 773 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 774 cpu_tau_setup(ci); 775 #endif 776 777 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 778 if (vers == IBM970MP) 779 init_scom_speedctl(); 780 #endif 781 782 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 783 NULL, xname, "clock"); 784 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 785 NULL, xname, "traps"); 786 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 787 &ci->ci_ev_traps, xname, "kernel DSI traps"); 788 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 789 &ci->ci_ev_traps, xname, "user DSI traps"); 790 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 791 &ci->ci_ev_udsi, xname, "user DSI failures"); 792 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 793 &ci->ci_ev_traps, xname, "kernel ISI traps"); 794 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 795 &ci->ci_ev_traps, xname, "user ISI traps"); 796 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 797 &ci->ci_ev_isi, xname, "user ISI failures"); 798 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 799 &ci->ci_ev_traps, xname, "system call traps"); 800 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 801 &ci->ci_ev_traps, xname, "PGM traps"); 802 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 803 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 804 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 805 &ci->ci_ev_fpu, xname, "FPU context switches"); 806 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 807 &ci->ci_ev_traps, xname, "user alignment traps"); 808 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 809 &ci->ci_ev_ali, xname, "user alignment traps"); 810 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 811 &ci->ci_ev_umchk, xname, "user MCHK failures"); 812 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 813 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 814 #ifdef ALTIVEC 815 if (cpu_altivec) { 816 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 817 &ci->ci_ev_vec, xname, "AltiVec context switches"); 818 } 819 #endif 820 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 821 NULL, xname, "IPIs"); 822 } 823 824 /* 825 * According to a document labeled "PVR Register Settings": 826 ** For integrated microprocessors the PVR register inside the device 827 ** will identify the version of the microprocessor core. You must also 828 ** read the Device ID, PCI register 02, to identify the part and the 829 ** Revision ID, PCI register 08, to identify the revision of the 830 ** integrated microprocessor. 831 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 832 */ 833 834 void 835 cpu_identify(char *str, size_t len) 836 { 837 u_int pvr, major, minor; 838 uint16_t vers, rev, revfmt; 839 const struct cputab *cp; 840 size_t n; 841 842 pvr = mfpvr(); 843 vers = pvr >> 16; 844 rev = pvr; 845 846 switch (vers) { 847 case MPC7410: 848 minor = (pvr >> 0) & 0xff; 849 major = minor <= 4 ? 1 : 2; 850 break; 851 case MPCG2: /*XXX see note above */ 852 major = (pvr >> 4) & 0xf; 853 minor = (pvr >> 0) & 0xf; 854 break; 855 default: 856 major = (pvr >> 8) & 0xf; 857 minor = (pvr >> 0) & 0xf; 858 } 859 860 for (cp = models; cp->name[0] != '\0'; cp++) { 861 if (cp->version == vers) 862 break; 863 } 864 865 if (cpu == -1) 866 cpu = vers; 867 868 revfmt = cp->revfmt; 869 if (rev == MPC750 && pvr == 15) { 870 revfmt = REVFMT_HEX; 871 } 872 873 if (cp->name[0] != '\0') { 874 n = snprintf(str, len, "%s (Revision ", cp->name); 875 } else { 876 n = snprintf(str, len, "Version %#x (Revision ", vers); 877 } 878 if (len > n) { 879 switch (revfmt) { 880 case REVFMT_MAJMIN: 881 snprintf(str + n, len - n, "%u.%u)", major, minor); 882 break; 883 case REVFMT_HEX: 884 snprintf(str + n, len - n, "0x%04x)", rev); 885 break; 886 case REVFMT_DEC: 887 snprintf(str + n, len - n, "%u)", rev); 888 break; 889 } 890 } 891 } 892 893 #ifdef L2CR_CONFIG 894 u_int l2cr_config = L2CR_CONFIG; 895 #else 896 u_int l2cr_config = 0; 897 #endif 898 899 #ifdef L3CR_CONFIG 900 u_int l3cr_config = L3CR_CONFIG; 901 #else 902 u_int l3cr_config = 0; 903 #endif 904 905 void 906 cpu_enable_l2cr(register_t l2cr) 907 { 908 register_t msr, x; 909 uint16_t vers; 910 911 vers = mfpvr() >> 16; 912 913 /* Disable interrupts and set the cache config bits. */ 914 msr = mfmsr(); 915 mtmsr(msr & ~PSL_EE); 916 #ifdef ALTIVEC 917 if (cpu_altivec) 918 __asm volatile("dssall"); 919 #endif 920 __asm volatile("sync"); 921 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 922 __asm volatile("sync"); 923 924 /* Wait for L2 clock to be stable (640 L2 clocks). */ 925 delay(100); 926 927 /* Invalidate all L2 contents. */ 928 if (MPC745X_P(vers)) { 929 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 930 do { 931 x = mfspr(SPR_L2CR); 932 } while (x & L2CR_L2I); 933 } else { 934 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 935 do { 936 x = mfspr(SPR_L2CR); 937 } while (x & L2CR_L2IP); 938 } 939 /* Enable L2 cache. */ 940 l2cr |= L2CR_L2E; 941 mtspr(SPR_L2CR, l2cr); 942 mtmsr(msr); 943 } 944 945 void 946 cpu_enable_l3cr(register_t l3cr) 947 { 948 register_t x; 949 950 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 951 952 /* 953 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 954 * L3CLKEN. (also mask off reserved bits in case they were included 955 * in L3CR_CONFIG) 956 */ 957 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 958 mtspr(SPR_L3CR, l3cr); 959 960 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 961 l3cr |= 0x04000000; 962 mtspr(SPR_L3CR, l3cr); 963 964 /* 3: Set L3CLKEN to 1*/ 965 l3cr |= L3CR_L3CLKEN; 966 mtspr(SPR_L3CR, l3cr); 967 968 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 969 __asm volatile("dssall;sync"); 970 /* L3 cache is already disabled, no need to clear L3E */ 971 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 972 do { 973 x = mfspr(SPR_L3CR); 974 } while (x & L3CR_L3I); 975 976 /* 6: Clear L3CLKEN to 0 */ 977 l3cr &= ~L3CR_L3CLKEN; 978 mtspr(SPR_L3CR, l3cr); 979 980 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 981 __asm volatile("sync"); 982 delay(100); 983 984 /* 8: Set L3E and L3CLKEN */ 985 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 986 mtspr(SPR_L3CR, l3cr); 987 988 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 989 __asm volatile("sync"); 990 delay(100); 991 } 992 993 void 994 cpu_config_l2cr(int pvr) 995 { 996 register_t l2cr; 997 u_int vers = (pvr >> 16) & 0xffff; 998 999 l2cr = mfspr(SPR_L2CR); 1000 1001 /* 1002 * For MP systems, the firmware may only configure the L2 cache 1003 * on the first CPU. In this case, assume that the other CPUs 1004 * should use the same value for L2CR. 1005 */ 1006 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1007 l2cr_config = l2cr; 1008 } 1009 1010 /* 1011 * Configure L2 cache if not enabled. 1012 */ 1013 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1014 cpu_enable_l2cr(l2cr_config); 1015 l2cr = mfspr(SPR_L2CR); 1016 } 1017 1018 if ((l2cr & L2CR_L2E) == 0) { 1019 aprint_normal(" L2 cache present but not enabled "); 1020 return; 1021 } 1022 aprint_normal(","); 1023 1024 switch (vers) { 1025 case IBM750FX: 1026 case IBM750GX: 1027 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1028 break; 1029 case MPC750: 1030 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1031 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1032 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1033 else 1034 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1035 break; 1036 case MPC7447A: 1037 case MPC7457: 1038 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1039 return; 1040 case MPC7448: 1041 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1042 return; 1043 case MPC7450: 1044 case MPC7455: 1045 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1046 break; 1047 default: 1048 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1049 break; 1050 } 1051 } 1052 1053 void 1054 cpu_config_l3cr(int vers) 1055 { 1056 register_t l2cr; 1057 register_t l3cr; 1058 1059 l2cr = mfspr(SPR_L2CR); 1060 1061 /* 1062 * For MP systems, the firmware may only configure the L2 cache 1063 * on the first CPU. In this case, assume that the other CPUs 1064 * should use the same value for L2CR. 1065 */ 1066 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1067 l2cr_config = l2cr; 1068 } 1069 1070 /* 1071 * Configure L2 cache if not enabled. 1072 */ 1073 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1074 cpu_enable_l2cr(l2cr_config); 1075 l2cr = mfspr(SPR_L2CR); 1076 } 1077 1078 aprint_normal(","); 1079 switch (vers) { 1080 case MPC7447A: 1081 case MPC7457: 1082 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1083 return; 1084 case MPC7448: 1085 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1086 return; 1087 default: 1088 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1089 break; 1090 } 1091 1092 l3cr = mfspr(SPR_L3CR); 1093 1094 /* 1095 * For MP systems, the firmware may only configure the L3 cache 1096 * on the first CPU. In this case, assume that the other CPUs 1097 * should use the same value for L3CR. 1098 */ 1099 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1100 l3cr_config = l3cr; 1101 } 1102 1103 /* 1104 * Configure L3 cache if not enabled. 1105 */ 1106 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1107 cpu_enable_l3cr(l3cr_config); 1108 l3cr = mfspr(SPR_L3CR); 1109 } 1110 1111 if (l3cr & L3CR_L3E) { 1112 aprint_normal(","); 1113 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1114 } 1115 } 1116 1117 void 1118 cpu_probe_speed(struct cpu_info *ci) 1119 { 1120 uint64_t cps; 1121 1122 mtspr(SPR_MMCR0, MMCR0_FC); 1123 mtspr(SPR_PMC1, 0); 1124 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1125 delay(100000); 1126 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1127 1128 mtspr(SPR_MMCR0, MMCR0_FC); 1129 1130 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1131 } 1132 1133 /* 1134 * Read the Dynamic Frequency Switching state and return a divisor for 1135 * the maximum frequency. 1136 */ 1137 int 1138 cpu_get_dfs(void) 1139 { 1140 u_int pvr, vers; 1141 1142 pvr = mfpvr(); 1143 vers = pvr >> 16; 1144 1145 switch (vers) { 1146 case MPC7448: 1147 if (mfspr(SPR_HID1) & HID1_DFS4) 1148 return 4; 1149 /* FALLTHROUGH */ 1150 case MPC7447A: 1151 if (mfspr(SPR_HID1) & HID1_DFS2) 1152 return 2; 1153 } 1154 return 1; 1155 } 1156 1157 /* 1158 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1159 */ 1160 void 1161 cpu_set_dfs(int div) 1162 { 1163 u_int dfs_mask, pvr, vers; 1164 1165 pvr = mfpvr(); 1166 vers = pvr >> 16; 1167 dfs_mask = 0; 1168 1169 switch (vers) { 1170 case MPC7448: 1171 dfs_mask |= HID1_DFS4; 1172 /* FALLTHROUGH */ 1173 case MPC7447A: 1174 dfs_mask |= HID1_DFS2; 1175 break; 1176 default: 1177 printf("cpu_set_dfs: DFS not supported\n"); 1178 return; 1179 1180 } 1181 #ifdef MULTIPROCESSOR 1182 uint64_t where; 1183 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1184 xc_wait(where); 1185 #else 1186 cpu_set_dfs_xcall(&div, &dfs_mask); 1187 #endif 1188 } 1189 1190 static void 1191 cpu_set_dfs_xcall(void *arg1, void *arg2) 1192 { 1193 u_int dfs_mask, hid1, old_hid1; 1194 int *divisor, s; 1195 1196 divisor = arg1; 1197 dfs_mask = *(u_int *)arg2; 1198 1199 s = splhigh(); 1200 hid1 = old_hid1 = mfspr(SPR_HID1); 1201 1202 switch (*divisor) { 1203 case 1: 1204 hid1 &= ~dfs_mask; 1205 break; 1206 case 2: 1207 hid1 &= ~(dfs_mask & HID1_DFS4); 1208 hid1 |= dfs_mask & HID1_DFS2; 1209 break; 1210 case 4: 1211 hid1 &= ~(dfs_mask & HID1_DFS2); 1212 hid1 |= dfs_mask & HID1_DFS4; 1213 break; 1214 } 1215 1216 if (hid1 != old_hid1) { 1217 __asm volatile("sync"); 1218 mtspr(SPR_HID1, hid1); 1219 __asm volatile("sync;isync"); 1220 } 1221 1222 splx(s); 1223 } 1224 1225 #if NSYSMON_ENVSYS > 0 1226 void 1227 cpu_tau_setup(struct cpu_info *ci) 1228 { 1229 struct sysmon_envsys *sme; 1230 int error, therm_delay; 1231 1232 mtspr(SPR_THRM1, SPR_THRM_VALID); 1233 mtspr(SPR_THRM2, 0); 1234 1235 /* 1236 * we need to figure out how much 20+us in units of CPU clock cycles 1237 * are 1238 */ 1239 1240 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1241 1242 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1243 1244 sme = sysmon_envsys_create(); 1245 1246 sensor.units = ENVSYS_STEMP; 1247 sensor.state = ENVSYS_SINVALID; 1248 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1249 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1250 sysmon_envsys_destroy(sme); 1251 return; 1252 } 1253 1254 sme->sme_name = device_xname(ci->ci_dev); 1255 sme->sme_cookie = ci; 1256 sme->sme_refresh = cpu_tau_refresh; 1257 1258 if ((error = sysmon_envsys_register(sme)) != 0) { 1259 aprint_error_dev(ci->ci_dev, 1260 " unable to register with sysmon (%d)\n", error); 1261 sysmon_envsys_destroy(sme); 1262 } 1263 } 1264 1265 /* Find the temperature of the CPU. */ 1266 void 1267 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1268 { 1269 int i, threshold, count; 1270 1271 threshold = 64; /* Half of the 7-bit sensor range */ 1272 1273 /* Successive-approximation code adapted from Motorola 1274 * application note AN1800/D, "Programming the Thermal Assist 1275 * Unit in the MPC750 Microprocessor". 1276 */ 1277 for (i = 5; i >= 0 ; i--) { 1278 mtspr(SPR_THRM1, 1279 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1280 count = 0; 1281 while ((count < 100000) && 1282 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1283 count++; 1284 delay(1); 1285 } 1286 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1287 /* The interrupt bit was set, meaning the 1288 * temperature was above the threshold 1289 */ 1290 threshold += 1 << i; 1291 } else { 1292 /* Temperature was below the threshold */ 1293 threshold -= 1 << i; 1294 } 1295 } 1296 threshold += 2; 1297 1298 /* Convert the temperature in degrees C to microkelvin */ 1299 edata->value_cur = (threshold * 1000000) + 273150000; 1300 edata->state = ENVSYS_SVALID; 1301 } 1302 #endif /* NSYSMON_ENVSYS > 0 */ 1303 1304 #ifdef MULTIPROCESSOR 1305 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1306 1307 int 1308 cpu_spinup(device_t self, struct cpu_info *ci) 1309 { 1310 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1311 struct pglist mlist; 1312 int i, error; 1313 char *hp; 1314 1315 KASSERT(ci != curcpu()); 1316 1317 /* Now allocate a hatch stack */ 1318 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1319 &mlist, 1, 1); 1320 if (error) { 1321 aprint_error(": unable to allocate hatch stack\n"); 1322 return -1; 1323 } 1324 1325 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1326 memset(hp, 0, HATCH_STACK_SIZE); 1327 1328 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1329 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1330 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1331 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1332 1333 cpu_hatch_data = h; 1334 h->hatch_running = 0; 1335 h->hatch_self = self; 1336 h->hatch_ci = ci; 1337 h->hatch_pir = ci->ci_cpuid; 1338 1339 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1340 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1341 1342 /* copy special registers */ 1343 1344 h->hatch_hid0 = mfspr(SPR_HID0); 1345 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1346 h->hatch_hid1 = mfspr(SPR_HID1); 1347 h->hatch_hid4 = mfspr(SPR_HID4); 1348 h->hatch_hid5 = mfspr(SPR_HID5); 1349 #endif 1350 1351 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1352 for (i = 0; i < 16; i++) { 1353 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1354 "r"(i << ADDR_SR_SHFT)); 1355 } 1356 if (oeacpufeat & OEACPU_64) 1357 h->hatch_asr = mfspr(SPR_ASR); 1358 else 1359 h->hatch_asr = 0; 1360 1361 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1362 /* copy the bat regs */ 1363 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1364 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1365 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1366 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1367 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1368 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1369 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1370 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1371 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1372 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1373 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1374 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1375 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1376 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1377 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1378 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1379 __asm volatile ("sync; isync"); 1380 } 1381 1382 if (md_setup_trampoline(h, ci) == -1) 1383 return -1; 1384 md_presync_timebase(h); 1385 md_start_timebase(h); 1386 1387 /* wait for secondary printf */ 1388 1389 delay(200000); 1390 1391 #ifdef CACHE_PROTO_MEI 1392 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1393 __asm volatile ("sync; isync"); 1394 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1395 __asm volatile ("sync; isync"); 1396 #endif 1397 int hatch_bail = 0; 1398 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1399 delay(1); 1400 hatch_bail++; 1401 #ifdef CACHE_PROTO_MEI 1402 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1403 __asm volatile ("sync; isync"); 1404 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1405 __asm volatile ("sync; isync"); 1406 #endif 1407 } 1408 if (h->hatch_running < 1) { 1409 #ifdef CACHE_PROTO_MEI 1410 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1411 __asm volatile ("sync; isync"); 1412 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1413 __asm volatile ("sync; isync"); 1414 #endif 1415 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1416 ci->ci_cpuid, cpu_spinstart_ack); 1417 Debugger(); 1418 return -1; 1419 } 1420 1421 return 0; 1422 } 1423 1424 static volatile int start_secondary_cpu; 1425 1426 register_t 1427 cpu_hatch(void) 1428 { 1429 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1430 struct cpu_info * const ci = h->hatch_ci; 1431 struct pcb *pcb; 1432 u_int msr; 1433 int i; 1434 1435 /* Initialize timebase. */ 1436 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1437 1438 /* 1439 * Set PIR (Processor Identification Register). i.e. whoami 1440 * Note that PIR is read-only on some CPU versions, so we write to it 1441 * only if it has a different value than we need. 1442 */ 1443 1444 msr = mfspr(SPR_PIR); 1445 if (msr != h->hatch_pir) 1446 mtspr(SPR_PIR, h->hatch_pir); 1447 1448 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1449 curlwp = ci->ci_curlwp; 1450 cpu_spinstart_ack = 0; 1451 1452 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1453 /* Initialize MMU. */ 1454 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1455 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1456 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1457 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1458 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1459 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1460 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1461 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1462 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1463 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1464 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1465 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1466 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1467 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1468 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1469 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1470 } 1471 1472 #ifdef PPC_OEA64_BRIDGE 1473 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1474 1475 mtspr64(SPR_HID0, h->hatch_hid0); 1476 mtspr64(SPR_HID1, h->hatch_hid1); 1477 mtspr64(SPR_HID4, h->hatch_hid4); 1478 mtspr64(SPR_HID5, h->hatch_hid5); 1479 mtspr64(SPR_HIOR, 0); 1480 } else 1481 #endif 1482 mtspr(SPR_HID0, h->hatch_hid0); 1483 1484 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1485 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1486 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1487 } 1488 1489 __asm volatile ("sync"); 1490 for (i = 0; i < 16; i++) 1491 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1492 __asm volatile ("sync; isync"); 1493 1494 if (oeacpufeat & OEACPU_64) 1495 mtspr(SPR_ASR, h->hatch_asr); 1496 1497 cpu_spinstart_ack = 1; 1498 __asm ("ptesync"); 1499 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1500 __asm volatile ("sync; isync"); 1501 1502 cpu_spinstart_ack = 5; 1503 for (i = 0; i < 16; i++) 1504 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1505 "r"(i << ADDR_SR_SHFT)); 1506 1507 /* Enable I/D address translations. */ 1508 msr = mfmsr(); 1509 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1510 mtmsr(msr); 1511 __asm volatile ("sync; isync"); 1512 cpu_spinstart_ack = 2; 1513 1514 md_sync_timebase(h); 1515 1516 cpu_setup(h->hatch_self, ci); 1517 1518 h->hatch_running = 1; 1519 __asm volatile ("sync; isync"); 1520 1521 while (start_secondary_cpu == 0) 1522 ; 1523 1524 __asm volatile ("sync; isync"); 1525 1526 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1527 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1528 1529 md_setup_interrupts(); 1530 1531 ci->ci_ipending = 0; 1532 ci->ci_cpl = 0; 1533 1534 mtmsr(mfmsr() | PSL_EE); 1535 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1536 return pcb->pcb_sp; 1537 } 1538 1539 void 1540 cpu_boot_secondary_processors(void) 1541 { 1542 start_secondary_cpu = 1; 1543 __asm volatile ("sync"); 1544 } 1545 1546 #endif /*MULTIPROCESSOR*/ 1547