xref: /netbsd-src/sys/arch/powerpc/include/userret.h (revision 16031f7d46f56c21335839c17974dddd9f9800b4)
1*16031f7dSrin /*	$NetBSD: userret.h,v 1.31 2020/07/06 09:34:17 rin Exp $	*/
2810cde53Schs 
3810cde53Schs /*
4810cde53Schs  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5810cde53Schs  * Copyright (C) 1995, 1996 TooLs GmbH.
6810cde53Schs  * All rights reserved.
7810cde53Schs  *
8810cde53Schs  * Redistribution and use in source and binary forms, with or without
9810cde53Schs  * modification, are permitted provided that the following conditions
10810cde53Schs  * are met:
11810cde53Schs  * 1. Redistributions of source code must retain the above copyright
12810cde53Schs  *    notice, this list of conditions and the following disclaimer.
13810cde53Schs  * 2. Redistributions in binary form must reproduce the above copyright
14810cde53Schs  *    notice, this list of conditions and the following disclaimer in the
15810cde53Schs  *    documentation and/or other materials provided with the distribution.
16810cde53Schs  * 3. All advertising materials mentioning features or use of this software
17810cde53Schs  *    must display the following acknowledgement:
18810cde53Schs  *	This product includes software developed by TooLs GmbH.
19810cde53Schs  * 4. The name of TooLs GmbH may not be used to endorse or promote products
20810cde53Schs  *    derived from this software without specific prior written permission.
21810cde53Schs  *
22810cde53Schs  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23810cde53Schs  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24810cde53Schs  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25810cde53Schs  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26810cde53Schs  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27810cde53Schs  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28810cde53Schs  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29810cde53Schs  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30810cde53Schs  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31810cde53Schs  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32810cde53Schs  */
33810cde53Schs 
34*16031f7dSrin #ifdef _KERNEL_OPT
350a97a311Schs #include "opt_altivec.h"
36*16031f7dSrin #include "opt_ppcarch.h"
37*16031f7dSrin #endif
380a97a311Schs 
39ef56cc40Scl #include <sys/userret.h>
40283eda5aSmatt #include <sys/ras.h>
41ef56cc40Scl 
420a97a311Schs #include <powerpc/fpu.h>
4337ea7f52Smatt #include <powerpc/psl.h>
440a97a311Schs 
45cdbc87faSmatt #ifdef PPC_BOOKE
46cdbc87faSmatt #include <powerpc/spr.h>
47cdbc87faSmatt #include <powerpc/booke/spr.h>
48cdbc87faSmatt #endif
49cdbc87faSmatt 
50810cde53Schs /*
51810cde53Schs  * Define the code needed before returning to user mode, for
52810cde53Schs  * trap and syscall.
53810cde53Schs  */
54fbae48b9Sperry static __inline void
userret(struct lwp * l,struct trapframe * tf)55b8ea2c8cSmatt userret(struct lwp *l, struct trapframe *tf)
56810cde53Schs {
57b8ea2c8cSmatt 	KASSERTMSG((tf == trapframe(curlwp)),
58325494feSjym 	   "tf=%p, trapframe(curlwp)=%p\n", tf, trapframe(curlwp));
59810cde53Schs 
60ef56cc40Scl 	/* Invoke MI userret code */
61ef56cc40Scl 	mi_userret(l);
62f91b0bb3Sthorpej 
6394a2d5c8Smatt 	KASSERTMSG((tf->tf_srr1 & PSL_PR) != 0,
6494a2d5c8Smatt 	    "tf=%p: srr1 (%#lx): PSL_PR isn't set!",
6594a2d5c8Smatt 	    tf, tf->tf_srr1);
660b2dfc73Smatt 	KASSERTMSG((tf->tf_srr1 & PSL_FP) == 0
670b2dfc73Smatt 	    || l->l_cpu->ci_data.cpu_pcu_curlwp[PCU_FPU] == l,
680b2dfc73Smatt 	    "tf=%p: srr1 (%#lx): PSL_FP set but FPU curlwp %p is not curlwp %p!",
690b2dfc73Smatt 	    tf, tf->tf_srr1, l->l_cpu->ci_data.cpu_pcu_curlwp[PCU_FPU], l);
7094a2d5c8Smatt 
7139f57203Smatt 	/* clear SRR1 status bits */
7239f57203Smatt 	tf->tf_srr1 &= (PSL_USERSRR1|PSL_FP|PSL_VEC);
73810cde53Schs 
74810cde53Schs #ifdef ALTIVEC
75ee00feaaSmatt 	/*
76ee00feaaSmatt 	 * We need to manually restore PSL_VEC each time we return
77f36a02e8Smatt 	 * to user mode since PSL_VEC isn't always preserved in SRR1.
78f36a02e8Smatt 	 * We keep a copy of it in md_flags to make restoring easier.
79ee00feaaSmatt 	 */
80f36a02e8Smatt 	tf->tf_srr1 |= l->l_md.md_flags & PSL_VEC;
81810cde53Schs #endif
82cdbc87faSmatt #ifdef PPC_BOOKE
83cdbc87faSmatt 	/*
84e267b088Smatt 	 * BookE doesn't have PSL_SE but it does have a debug instruction
8553dc2650Smatt 	 * completion exception but it needs PSL_DE to fire.  Instead we
8653dc2650Smatt 	 * use IAC1/IAC2 to match the next PC.
87cdbc87faSmatt 	 */
8849aac98bSmatt 	if (__predict_false(tf->tf_srr1 & PSL_SE)) {
899f9d956cSmatt 		tf->tf_srr1 &= ~PSL_SE;
90cdbc87faSmatt 		extern void booke_sstep(struct trapframe *); /* ugly */
91cdbc87faSmatt 		booke_sstep(tf);
92cdbc87faSmatt 	}
93cdbc87faSmatt #endif
94283eda5aSmatt 
95283eda5aSmatt #ifdef __HAVE_RAS
96283eda5aSmatt 	/*
97283eda5aSmatt 	 * Check to see if a RAS was interrupted and restart it if it was.
98283eda5aSmatt 	 */
99283eda5aSmatt 	struct proc * const p = l->l_proc;
100283eda5aSmatt 	if (__predict_false(p->p_raslist != NULL)) {
101283eda5aSmatt 		void * const ras_pc = ras_lookup(p, (void *) tf->tf_srr0);
102283eda5aSmatt 		if (ras_pc != (void *) -1)
103283eda5aSmatt 			tf->tf_srr0 = (vaddr_t) ras_pc;
104283eda5aSmatt 	}
105283eda5aSmatt #endif
106810cde53Schs }
107