xref: /netbsd-src/sys/arch/powerpc/include/psl.h (revision 76dfffe33547c37f8bdd446e3e4ab0f3c16cea4b)
1 /*	$NetBSD: psl.h,v 1.1 1996/09/30 16:34:32 ws Exp $	*/
2 
3 /*
4  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5  * Copyright (C) 1995, 1996 TooLs GmbH.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by TooLs GmbH.
19  * 4. The name of TooLs GmbH may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 #ifndef	_MACHINE_PSL_H_
34 #define	_MACHINE_PSL_H_
35 
36 /*
37  * Flags in MSR:
38  */
39 #define	PSL_POW		0x00040000
40 #define	PSL_ILE		0x00010000
41 #define	PSL_EE		0x00008000
42 #define	PSL_PR		0x00004000
43 #define	PSL_FP		0x00002000
44 #define	PSL_ME		0x00001000
45 #define	PSL_FE0		0x00000800
46 #define	PSL_SE		0x00000400
47 #define	PSL_BE		0x00000200
48 #define	PSL_FE1		0x00000100
49 #define	PSL_IP		0x00000040
50 #define	PSL_IR		0x00000020
51 #define	PSL_DR		0x00000010
52 #define	PSL_RI		0x00000002
53 #define	PSL_LE		0x00000001
54 
55 /*
56  * Floating-point exception modes:
57  */
58 #define	PSL_FE_DIS	0
59 #define	PSL_FE_NONREC	PSL_FE1
60 #define	PSL_FE_REC	PSL_FE0
61 #define	PSL_FE_PREC	(PSL_FE0 | PSL_FE1)
62 #define	PSL_FE_DFLT	PSL_FE_DIS
63 
64 /*
65  * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
66  */
67 #define	PSL_MBO		0
68 #define	PSL_MBZ		0
69 
70 #define	PSL_USERSET	(PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
71 
72 #define	PSL_USERSTATIC	(PSL_USERSET | PSL_IP | 0x87c0008c)
73 
74 
75 #ifdef	_KERNEL
76 /*
77  * Current processor level.
78  */
79 #ifndef	_LOCORE
80 extern int cpl;
81 extern int clockpending, softclockpending, softnetpending;
82 #endif
83 #define	SPLBIO		0x01
84 #define	SPLNET		0x02
85 #define	SPLTTY		0x04
86 #define	SPLIMP		0x08
87 #define	SPLSOFTCLOCK	0x10
88 #define	SPLSOFTNET	0x20
89 #define	SPLCLOCK	0x80
90 #define	SPLMACHINE	0x0f	/* levels handled by machine interface */
91 
92 #ifndef	_LOCORE
93 extern int splx __P((int));
94 
95 extern int splraise __P((int));
96 
97 extern __inline int
98 splhigh()
99 {
100 	return splraise(-1);
101 }
102 
103 extern __inline int
104 spl0()
105 {
106 	return splx(0);
107 }
108 
109 extern __inline int
110 splbio()
111 {
112 	return splraise(SPLBIO | SPLSOFTCLOCK | SPLSOFTNET);
113 }
114 
115 extern __inline int
116 splnet()
117 {
118 	return splraise(SPLNET | SPLSOFTCLOCK | SPLSOFTNET);
119 }
120 
121 extern __inline int
122 spltty()
123 {
124 	return splraise(SPLTTY | SPLSOFTCLOCK | SPLSOFTNET);
125 }
126 
127 extern __inline int
128 splimp()
129 {
130 	return splraise(SPLIMP | SPLSOFTCLOCK | SPLSOFTNET);
131 }
132 extern __inline int
133 splclock()
134 {
135 	return splraise(SPLCLOCK | SPLSOFTCLOCK | SPLSOFTNET);
136 }
137 
138 extern __inline int
139 splsoftclock()
140 {
141 	return splraise(SPLSOFTCLOCK);
142 }
143 
144 extern __inline int
145 splsoftnet()
146 {
147 	return splraise(SPLSOFTNET);
148 }
149 
150 extern __inline void
151 setsoftclock()
152 {
153 	softclockpending = 1;
154 	if (!(cpl & SPLSOFTCLOCK))
155 		splx(cpl);
156 }
157 
158 extern __inline void
159 setsoftnet()
160 {
161 	softnetpending = 1;
162 	if (!(cpl & SPLSOFTNET))
163 		splx(cpl);
164 }
165 
166 #endif	/* !_LOCORE */
167 
168 #define	splstatclock()		splclock()
169 
170 #endif	/* _KERNEL */
171 #endif	/* _MACHINE_PSL_H_ */
172