1*80a83a2bSgarbled /* $NetBSD: openpicreg.h,v 1.8 2008/01/17 23:42:58 garbled Exp $ */ 2044caccfSbriggs 3044caccfSbriggs /*- 4044caccfSbriggs * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5044caccfSbriggs * 6044caccfSbriggs * Redistribution and use in source and binary forms, with or without 7044caccfSbriggs * modification, are permitted provided that the following conditions 8044caccfSbriggs * are met: 9044caccfSbriggs * 1. Redistributions of source code must retain the above copyright 10044caccfSbriggs * notice, this list of conditions and the following disclaimer. 11044caccfSbriggs * 2. Redistributions in binary form must reproduce the above copyright 12044caccfSbriggs * notice, this list of conditions and the following disclaimer in the 13044caccfSbriggs * documentation and/or other materials provided with the distribution. 14044caccfSbriggs * 3. The name of the author may not be used to endorse or promote products 15044caccfSbriggs * derived from this software without specific prior written permission. 16044caccfSbriggs * 17044caccfSbriggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18044caccfSbriggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19044caccfSbriggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20044caccfSbriggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21044caccfSbriggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22044caccfSbriggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23044caccfSbriggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24044caccfSbriggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25044caccfSbriggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26044caccfSbriggs * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27044caccfSbriggs */ 28044caccfSbriggs 29044caccfSbriggs /* 30044caccfSbriggs * GLOBAL/TIMER register (IDU base + 0x1000) 31044caccfSbriggs */ 32044caccfSbriggs 33044caccfSbriggs /* feature reporting reg 0 */ 34044caccfSbriggs #define OPENPIC_FEATURE 0x1000 35044caccfSbriggs 36044caccfSbriggs /* global config reg 0 */ 37044caccfSbriggs #define OPENPIC_CONFIG 0x1020 38044caccfSbriggs #define OPENPIC_CONFIG_RESET 0x80000000 39044caccfSbriggs #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 40044caccfSbriggs 4189829e48Sbriggs /* interrupt configuration mode (direct or serial) */ 4289829e48Sbriggs #define OPENPIC_ICR 0x1030 4389829e48Sbriggs #define OPENPIC_ICR_SERIAL_MODE (1 << 27) 4489829e48Sbriggs #define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 4589829e48Sbriggs #define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 4689829e48Sbriggs 47044caccfSbriggs /* vendor ID */ 48044caccfSbriggs #define OPENPIC_VENDOR_ID 0x1080 49044caccfSbriggs 50044caccfSbriggs /* processor initialization reg */ 51044caccfSbriggs #define OPENPIC_PROC_INIT 0x1090 52044caccfSbriggs 53044caccfSbriggs /* IPI vector/priority reg */ 54044caccfSbriggs #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 55044caccfSbriggs 56044caccfSbriggs /* spurious intr. vector */ 57044caccfSbriggs #define OPENPIC_SPURIOUS_VECTOR 0x10e0 58d974db0aSgarbled /* Timer frequency register */ 59d974db0aSgarbled #define OPENPIC_TIMER_FREQ 0x10f0 60044caccfSbriggs 61d974db0aSgarbled /* Timer current count register */ 62d974db0aSgarbled #define OPENPIC_TIMER_CC(timer) (0x1100 + (timer) * 0x40) 63d974db0aSgarbled /* Timer basecount register */ 64d974db0aSgarbled #define OPENPIC_TIMER_BC(timer) (0x1110 + (timer) * 0x40) 65d974db0aSgarbled /* Timer Vector/Priority register (uses imask,activity,priority and vector)*/ 66d974db0aSgarbled #define OPENPIC_TIMER_VECTOR(timer) (0x1120 + (timer) * 0x40) 67d974db0aSgarbled /* Timer destination register */ 68d974db0aSgarbled #define OPENPIC_TIMER_DEST(timer) (0x1130 + (timer) * 0x40) 69044caccfSbriggs 70044caccfSbriggs /* 71044caccfSbriggs * INTERRUPT SOURCE register (IDU base + 0x10000) 72*80a83a2bSgarbled * ABOVE ONLY TRUE FOR NON-DISTRIBUTED OPENPICS!! 73044caccfSbriggs */ 74044caccfSbriggs 75*80a83a2bSgarbled #define OPENPIC_DSRC_VECTOR_OFFSET(irq) ((irq) * 0x20) 76*80a83a2bSgarbled #define OPENPIC_DSRC_IDEST_OFFSET(irq) ((irq) * 0x20 + 0x10) 77*80a83a2bSgarbled 78*80a83a2bSgarbled 79044caccfSbriggs /* interrupt vector/priority reg */ 80044caccfSbriggs #ifndef OPENPIC_SRC_VECTOR 81044caccfSbriggs #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 82044caccfSbriggs #endif 83044caccfSbriggs #define OPENPIC_SENSE_LEVEL 0x00400000 84044caccfSbriggs #define OPENPIC_SENSE_EDGE 0x00000000 85044caccfSbriggs #define OPENPIC_POLARITY_POSITIVE 0x00800000 86044caccfSbriggs #define OPENPIC_POLARITY_NEGATIVE 0x00000000 87044caccfSbriggs #define OPENPIC_IMASK 0x80000000 88044caccfSbriggs #define OPENPIC_ACTIVITY 0x40000000 89044caccfSbriggs #define OPENPIC_PRIORITY_MASK 0x000f0000 90044caccfSbriggs #define OPENPIC_PRIORITY_SHIFT 16 91044caccfSbriggs #define OPENPIC_VECTOR_MASK 0x000000ff 92044caccfSbriggs 93d20841bbSwiz /* interrupt destination CPU */ 94044caccfSbriggs #ifndef OPENPIC_IDEST 95044caccfSbriggs #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 96044caccfSbriggs #endif 97044caccfSbriggs 98044caccfSbriggs /* 99044caccfSbriggs * PROCESSOR register (IDU base + 0x20000) 100044caccfSbriggs */ 101044caccfSbriggs 102044caccfSbriggs /* IPI command reg */ 103461184c6Schs #define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + \ 104461184c6Schs (ipi) * 0x10) 105044caccfSbriggs 106044caccfSbriggs /* current task priority reg */ 107044caccfSbriggs #define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 108044caccfSbriggs #define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 109044caccfSbriggs 110044caccfSbriggs /* interrupt acknowledge reg */ 111044caccfSbriggs #define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 112044caccfSbriggs 113044caccfSbriggs /* end of interrupt reg */ 114044caccfSbriggs #define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 115