1 /* $NetBSD: hid.h,v 1.12 2018/02/16 18:04:06 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _POWERPC_OEA_HID_H_ 30 #define _POWERPC_OEA_HID_H_ 31 32 /* Hardware Implementation Dependent registers for the PowerPC */ 33 34 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 35 /* this way we can use the same bit numbers as IBM's PowerPC manuals */ 36 #define HIDBIT(x) (0x8000000000000000LL >> x) 37 #define HID0_64_ONE_PPC HIDBIT(0) /* one instruction per dispatch group */ 38 #define HID0_64_DO_SNGL HIDBIT(1) /* single group completion mode */ 39 #define HID0_64_ISYNCSC HIDBIT(2) /* Disable isync scoreboard optimization */ 40 #define HID0_64_SER_GP HIDBIT(3) /* Serialize group dispatch */ 41 #define HID0_64_DEEPNAP HIDBIT(7) /* Enable deep nap mode (970) */ 42 #define HID0_64_DOZE HIDBIT(8) /* Enable doze mode */ 43 #define HID0_64_NAP HIDBIT(9) /* Enable nap mode */ 44 #define HID0_64_DPM HIDBIT(11) /* Enable Dynamic power management */ 45 #define HID0_64_TG HIDBIT(13) /* Perfmon threshold granularity control */ 46 #define HID0_64_HNG_DIS HIDBIT(14) /* Disable processor hang-detection */ 47 #define HID0_64_NHR HIDBIT(15) /* No Hard Reset */ 48 #define HID0_64_INORDER HIDBIT(16) /* Serialized group issue mode */ 49 #define HID0_64_TB_CTRL HIDBIT(18) /* TB keeps running if CPU stopped */ 50 #define HID0_64_EX_TBEN HIDBIT(19) /* timebase runs at external clock */ 51 #define HID0_64_CIABREN HIDBIT(22) /* enable CIABR register */ 52 #define HID0_64_HDICEEN HIDBIT(23) /* hypervisor decrementer enable */ 53 #define HID0_64_EN_ATTN HIDBIT(31) /* support processor attention inst. */ 54 #define HID0_64_EN_MCHK HIDBIT(32) /* ext. mchk interrupts */ 55 #endif 56 #define HID0_EMCP 0x80000000 /* Enable MCP */ 57 #define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 58 #define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 59 #define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 60 #define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 61 #define HID0_EICE 0x04000000 /* Enable ICE output */ 62 #define HID0_TBEN 0x04000000 /* Time base enable (7450) */ 63 #define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 64 #define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 65 #define HID0_STEN 0x01000000 /* Software table search enable (7450) */ 66 #define HID0_DOZE 0x00800000 /* Enable doze mode */ 67 #define HID0_HIGH_BAT_EN 0x00800000 /* Enable additional BATs (74[45][578]) */ 68 #define HID0_NAP 0x00400000 /* Enable nap mode */ 69 #define HID0_SLEEP 0x00200000 /* Enable sleep mode */ 70 #define HID0_DPM 0x00100000 /* Enable Dynamic power management */ 71 #define HID0_RISEG 0x00080000 /* Read I-SEG */ 72 #define HID0_BHTCLR 0x00040000 /* Clear branch history table (7450) */ 73 #define HID0_EIEC 0x00040000 /* Enable internal error checking */ 74 #define HID0_XAEN 0x00020000 /* Enable eXtended Addressing (7450) */ 75 #define HID0_NHR 0x00010000 /* Not hard reset */ 76 #define HID0_ICE 0x00008000 /* Enable i-cache */ 77 #define HID0_DCE 0x00004000 /* Enable d-cache */ 78 #define HID0_ILOCK 0x00002000 /* i-cache lock */ 79 #define HID0_DLOCK 0x00001000 /* d-cache lock */ 80 #define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ 81 #define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ 82 #define HID0_SPD 0x00000200 /* Disable speculative cache access */ 83 #define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ 84 #define HID0_XBSEN 0x00000100 /* Extended BAT block size enable (7455+) */ 85 #define HID0_SGE 0x00000080 /* Enable store gathering */ 86 #define HID0_DCFA 0x00000040 /* Data cache flush assist */ 87 #define HID0_BTIC 0x00000020 /* Enable BTIC */ 88 #define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */ 89 #define HID0_ABE 0x00000008 /* Enable address broadcast */ 90 #define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */ 91 #define HID0_BHT 0x00000004 /* Enable branch history table */ 92 #define HID0_BTCD 0x00000002 /* Branch target addr cache disable (604) */ 93 #define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ 94 95 #define HID0_BITMASK "\020" \ 96 "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ 97 "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ 98 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ 99 "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI" 100 101 #define HID0_7450_BITMASK "\020" \ 102 "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \ 103 "\030HIGH_BAT_EN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \ 104 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \ 105 "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI" 106 107 #define HID0_970_BITMASK "\020" \ 108 "\040EMCP" 109 110 #define HID0_970_BITMASK_U "\020" \ 111 "\040ONEPPC\036DOSNGL\036ISYNCSC\035SERGP\034res\033res\032res\031DEEPNAP" \ 112 "\030DOZE\027NAP\026res\025DPM\024res\023TG\022HNGDIS\021NHR" \ 113 "\020INORDER\017res\016TBCTRL\015EXTBEN\014res\013res\012CIABREN\011HDICEEN" \ 114 "\001ENATTN" 115 /* 116 * HID0 bit definitions per CPU model 117 * 118 * bit 603 604 750 7400 7410 7450 119 * 0 EMCP EMCP EMCP EMCP EMCP - 120 * 1 - ECP DBP - - - 121 * 2 EBA EBA EBA EBA EDA - 122 * 3 EBD EBD EBD EBD EBD - 123 * 4 SBCLK - BCLK BCKL BCLK - 124 * 5 EICE - - - - TBEN 125 * 6 ECLK - ECLK ECLK ECLK - 126 * 7 PAR PAR PAR PAR PAR STEN 127 * 8 DOZE - DOZE DOZE DOZE HIGH_BAT_EN 128 * 9 NAP - NAP NAP NAP NAP 129 * 10 SLEEP - SLEEP SLEEP SLEEP SLEEP 130 * 11 DPM - DPM DPM DPM DPM 131 * 12 RISEG - - RISEG - - 132 * 13 - - - EIEC EIEC BHTCLR 133 * 14 - - - - - XAEN 134 * 15 - NHR NHR NHR NHR NHR 135 * 16 ICE ICE ICE ICE ICE ICE 136 * 17 DCE DCE DCE DCE DCE DCE 137 * 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK 138 * 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK 139 * 20 ICFI ICFI ICFI ICFI ICFI ICFI 140 * 21 DCFI DCFI DCFI DCFI DCFI DCFI 141 * 22 - - SPD SPD SPG SPD 142 * 23 - - IFEM IFTT IFTT XBSEN 143 * 24 - SIE SGE SGE SGE SGE 144 * 25 - - DCFA DCFA DCFA - 145 * 26 - - BTIC BTIC BTIC BTIC 146 * 27 FBIOB - - - - LRSTK 147 * 28 - - ABE - - FOLD 148 * 29 - BHT BHT BHT BHT BHT 149 * 30 - BTCD - NOPDST NOPDST NOPDST 150 * 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI 151 * 152 * 604: ECP = Enable cache parity checking 153 * 604: SIE = Serial instruction execution disable 154 * 604: BTCD = Branch target address cache disable 155 * 7450: TBEN = Time Base Enable 156 * 7450: STEN = Software table lookup enable 157 * 7450: BHTCLR = Branch history clear 158 * 7450: LRSTK = Link Register Stack Enable 159 * 7450: FOLD = Branch folding enable 160 */ 161 162 #define HID1_EMCP 0x80000000 /* Machine Check Signal Enable */ 163 #define HID1_EBA 0x20000000 /* Enable/Disable 60x/MPX Bus Address 164 Parity Checking */ 165 #define HID1_EBD 0x10000000 /* Enable/Disable 60x/MPX Bus Data 166 Parity Checking */ 167 #define HID1_BCLK 0x08000000 /* CLK_OUT */ 168 #define HID1_ECLK 0x02000000 /* CLK_OUT */ 169 #define HID1_PAR 0x01000000 /* Disable Precharge for ... */ 170 #define HID1_DFS4 0x00800000 /* Dynamic Freq Switch / 4 (7448) */ 171 #define HID1_DFS2 0x00400000 /* Dynamic Freq Switch / 2 (7447A) */ 172 #define HID1_SYNCBE 0x00000800 /* Enable sync/eieio broadcast */ 173 #define HID1_ABE 0x00000400 /* Enable address broadcast */ 174 175 /* PPC970 HID4 */ 176 #define HID4_RMLR0 0x0000000000000020 /* real mode limit bit 0 */ 177 #define HID4_RMLR1 0x4000000000000000 /* real mode limit bit 1 */ 178 #define HID4_RMLR2 0x2000000000000000 /* real mode limit bit 2 */ 179 /* 180 * real mode limit bits 012 181 * 011 - 64MB 182 * 111 - 128MB 183 * 100 - 256MB 184 * x10 - 1GB 185 * x01 - 16GB 186 * 000 - 256GB 187 */ 188 189 #endif /* _POWERPC_OEA_HID_H_ */ 190