xref: /netbsd-src/sys/arch/powerpc/include/mcontext.h (revision 16543c49052c820334cffc5c69b2afde18f02458)
1*16543c49Schristos /*	$NetBSD: mcontext.h,v 1.26 2024/11/30 01:04:13 christos Exp $	*/
2f91b0bb3Sthorpej 
3f91b0bb3Sthorpej /*-
4f91b0bb3Sthorpej  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5f91b0bb3Sthorpej  * All rights reserved.
6f91b0bb3Sthorpej  *
7f91b0bb3Sthorpej  * This code is derived from software contributed to The NetBSD Foundation
8f91b0bb3Sthorpej  * by Klaus Klein.
9f91b0bb3Sthorpej  *
10f91b0bb3Sthorpej  * Redistribution and use in source and binary forms, with or without
11f91b0bb3Sthorpej  * modification, are permitted provided that the following conditions
12f91b0bb3Sthorpej  * are met:
13f91b0bb3Sthorpej  * 1. Redistributions of source code must retain the above copyright
14f91b0bb3Sthorpej  *    notice, this list of conditions and the following disclaimer.
15f91b0bb3Sthorpej  * 2. Redistributions in binary form must reproduce the above copyright
16f91b0bb3Sthorpej  *    notice, this list of conditions and the following disclaimer in the
17f91b0bb3Sthorpej  *    documentation and/or other materials provided with the distribution.
18f91b0bb3Sthorpej  *
19f91b0bb3Sthorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20f91b0bb3Sthorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21f91b0bb3Sthorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22f91b0bb3Sthorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23f91b0bb3Sthorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24f91b0bb3Sthorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25f91b0bb3Sthorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26f91b0bb3Sthorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27f91b0bb3Sthorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28f91b0bb3Sthorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29f91b0bb3Sthorpej  * POSSIBILITY OF SUCH DAMAGE.
30f91b0bb3Sthorpej  */
31f91b0bb3Sthorpej 
32f91b0bb3Sthorpej #ifndef _POWERPC_MCONTEXT_H_
33f91b0bb3Sthorpej #define _POWERPC_MCONTEXT_H_
34f91b0bb3Sthorpej 
35f91b0bb3Sthorpej /*
36f91b0bb3Sthorpej  * Layout of mcontext_t based on the System V Application Binary Interface,
37f91b0bb3Sthorpej  * Edition 4.1, PowerPC Processor ABI Supplement - September 1995, and
38f91b0bb3Sthorpej  * extended for the AltiVec Register File.  Note that due to the increased
39f91b0bb3Sthorpej  * alignment requirements of the latter, the offset of mcontext_t within
40f91b0bb3Sthorpej  * an ucontext_t is different from System V.
41f91b0bb3Sthorpej  */
42f91b0bb3Sthorpej 
43f91b0bb3Sthorpej #define	_NGREG	39		/* GR0-31, CR, LR, SRR0, SRR1, CTR, XER, MQ */
44f91b0bb3Sthorpej 
4582fd269fSmatt typedef	long		__greg_t;
46f91b0bb3Sthorpej typedef	__greg_t	__gregset_t[_NGREG];
47f91b0bb3Sthorpej 
48fb891b41Smatt #define	_REG_R0		0
49fb891b41Smatt #define	_REG_R1		1
50fb891b41Smatt #define	_REG_R2		2
51fb891b41Smatt #define	_REG_R3		3
52fb891b41Smatt #define	_REG_R4		4
53fb891b41Smatt #define	_REG_R5		5
54fb891b41Smatt #define	_REG_R6		6
55fb891b41Smatt #define	_REG_R7		7
56fb891b41Smatt #define	_REG_R8		8
57fb891b41Smatt #define	_REG_R9		9
58fb891b41Smatt #define	_REG_R10	10
59fb891b41Smatt #define	_REG_R11	11
60fb891b41Smatt #define	_REG_R12	12
61fb891b41Smatt #define	_REG_R13	13
62fb891b41Smatt #define	_REG_R14	14
63fb891b41Smatt #define	_REG_R15	15
64fb891b41Smatt #define	_REG_R16	16
65fb891b41Smatt #define	_REG_R17	17
66fb891b41Smatt #define	_REG_R18	18
67fb891b41Smatt #define	_REG_R19	19
68fb891b41Smatt #define	_REG_R20	20
69fb891b41Smatt #define	_REG_R21	21
70fb891b41Smatt #define	_REG_R22	22
71fb891b41Smatt #define	_REG_R23	23
72fb891b41Smatt #define	_REG_R24	24
73fb891b41Smatt #define	_REG_R25	25
74fb891b41Smatt #define	_REG_R26	26
75fb891b41Smatt #define	_REG_R27	27
76fb891b41Smatt #define	_REG_R28	28
77fb891b41Smatt #define	_REG_R29	29
78fb891b41Smatt #define	_REG_R30	30
79fb891b41Smatt #define	_REG_R31	31
80fb891b41Smatt #define	_REG_CR		32		/* Condition Register */
81fb891b41Smatt #define	_REG_LR		33		/* Link Register */
82fb891b41Smatt #define	_REG_PC		34		/* PC (copy of SRR0) */
83fb891b41Smatt #define	_REG_MSR	35		/* MSR (copy of SRR1) */
84fb891b41Smatt #define	_REG_CTR	36		/* Count Register */
85c8ecf09cSmatt #define	_REG_XER	37		/* Integer Exception Register */
86fb891b41Smatt #define	_REG_MQ		38		/* MQ Register (POWER only) */
87f91b0bb3Sthorpej 
88f91b0bb3Sthorpej typedef struct {
89691c3170Sjoerg #ifdef _KERNEL
90691c3170Sjoerg 	unsigned long long	__fpu_regs[32];	/* FP0-31 */
91691c3170Sjoerg #else
92f91b0bb3Sthorpej 	double		__fpu_regs[32];	/* FP0-31 */
93691c3170Sjoerg #endif
94f91b0bb3Sthorpej 	unsigned int	__fpu_fpscr;	/* FP Status and Control Register */
95f91b0bb3Sthorpej 	unsigned int	__fpu_valid;	/* Set together with _UC_FPU */
96f91b0bb3Sthorpej } __fpregset_t;
97f91b0bb3Sthorpej 
98f91b0bb3Sthorpej #define	_NVR	32			/* Number of Vector registers */
99f91b0bb3Sthorpej 
100f91b0bb3Sthorpej typedef struct {
101f91b0bb3Sthorpej 	union __vr {
102f91b0bb3Sthorpej 		unsigned char	__vr8[16];
103f91b0bb3Sthorpej 		unsigned short	__vr16[8];
104f91b0bb3Sthorpej 		unsigned int	__vr32[4];
105c8ecf09cSmatt 		unsigned char	__spe8[8];
106c8ecf09cSmatt 		unsigned short	__spe16[4];
107c8ecf09cSmatt 		unsigned int	__spe32[2];
108c8ecf09cSmatt 	} 		__vrs[_NVR] __aligned(16);
109f91b0bb3Sthorpej 	unsigned int	__vscr;		/* VSCR */
110f91b0bb3Sthorpej 	unsigned int	__vrsave;	/* VRSAVE */
111f91b0bb3Sthorpej } __vrf_t;
112f91b0bb3Sthorpej 
113f91b0bb3Sthorpej typedef struct {
114f91b0bb3Sthorpej 	__gregset_t	__gregs;	/* General Purpose Register set */
115f91b0bb3Sthorpej 	__fpregset_t	__fpregs;	/* Floating Point Register set */
116f91b0bb3Sthorpej 	__vrf_t		__vrf;		/* Vector Register File */
117f91b0bb3Sthorpej } mcontext_t;
118f91b0bb3Sthorpej 
1192568724eSmatt #if defined(_LP64)
1202568724eSmatt typedef	int		__greg32_t;
1212568724eSmatt typedef	__greg32_t	__gregset32_t[_NGREG];
1222568724eSmatt 
1232568724eSmatt typedef struct {
1242568724eSmatt 	__gregset32_t	__gregs;	/* General Purpose Register set */
1252568724eSmatt 	__fpregset_t	__fpregs;	/* Floating Point Register set */
1262568724eSmatt 	__vrf_t		__vrf;		/* Vector Register File */
1272568724eSmatt } mcontext32_t;
1282568724eSmatt #endif
1292568724eSmatt 
130f91b0bb3Sthorpej /* Machine-dependent uc_flags */
1311853c81aSthorpej #define	_UC_POWERPC_VEC	_UC_MD_BIT16	/* Vector Register File valid */
1321853c81aSthorpej #define	_UC_POWERPC_SPE	_UC_MD_BIT17	/* Vector Register File valid */
1331853c81aSthorpej #define	_UC_TLSBASE	_UC_MD_BIT19	/* thread context valid in R2 */
1341853c81aSthorpej #define	_UC_SETSTACK	_UC_MD_BIT20
1351853c81aSthorpej #define	_UC_CLRSTACK	_UC_MD_BIT21
136f91b0bb3Sthorpej 
137901da40cSthorpej #define _UC_MACHINE_SP(uc)	((uc)->uc_mcontext.__gregs[_REG_R1])
13884799695Skamil #define _UC_MACHINE_FP(uc)	((uc)->uc_mcontext.__gregs[_REG_R31])
139901da40cSthorpej #define _UC_MACHINE_PC(uc)	((uc)->uc_mcontext.__gregs[_REG_PC])
140901da40cSthorpej #define _UC_MACHINE_INTRV(uc)	((uc)->uc_mcontext.__gregs[_REG_R3])
141901da40cSthorpej 
142901da40cSthorpej #define	_UC_MACHINE_SET_PC(uc, pc)	_UC_MACHINE_PC(uc) = (pc)
143f91b0bb3Sthorpej 
144f91b0bb3Sthorpej #endif	/* !_POWERPC_MCONTEXT_H_ */
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