1*18b2f7e6Ssimonb #ifndef _IBM4XX_MAL405GP_H_ 2*18b2f7e6Ssimonb #define _IBM4XX_MAL405GP_H_ 3*18b2f7e6Ssimonb 4*18b2f7e6Ssimonb /* Memory Access Layer buffer descriptor */ 5*18b2f7e6Ssimonb struct mal_descriptor { 6*18b2f7e6Ssimonb volatile u_int16_t md_stat_ctrl; /* Status/Control */ 7*18b2f7e6Ssimonb volatile u_int16_t md_data_len; /* Data Len (low 12 bits only) */ 8*18b2f7e6Ssimonb volatile u_int32_t md_data; /* Data pointer */ 9*18b2f7e6Ssimonb }; 10*18b2f7e6Ssimonb 11*18b2f7e6Ssimonb /* MAL transmit status/control definitions */ 12*18b2f7e6Ssimonb #define MAL_TX_READY 0x8000 13*18b2f7e6Ssimonb #define MAL_TX_WRAP 0x4000 14*18b2f7e6Ssimonb #define MAL_TX_CONTINUOUS_MODE 0x2000 15*18b2f7e6Ssimonb #define MAL_TX_LAST 0x1000 16*18b2f7e6Ssimonb #define MAL_TX_INTERRUPT 0x0400 17*18b2f7e6Ssimonb 18*18b2f7e6Ssimonb /* MAL receive status/control definitions */ 19*18b2f7e6Ssimonb #define MAL_RX_EMPTY 0x8000 20*18b2f7e6Ssimonb #define MAL_RX_WRAP 0x4000 21*18b2f7e6Ssimonb #define MAL_RX_CONTINUOUS_MODE 0x2000 22*18b2f7e6Ssimonb #define MAL_RX_LAST 0x1000 23*18b2f7e6Ssimonb #define MAL_RX_FIRST 0x0800 24*18b2f7e6Ssimonb #define MAL_RX_INTERRUPT 0x0400 25*18b2f7e6Ssimonb 26*18b2f7e6Ssimonb #endif /* _IBM4XX_MAL405GP_H_ */ 27