1*ce099b40Smartin /* $NetBSD: dcr403cgx.h,v 1.4 2008/04/28 20:23:32 martin Exp $ */ 244b1e07eShannken 344b1e07eShannken /*- 444b1e07eShannken * Copyright (c) 2003 The NetBSD Foundation, Inc. 544b1e07eShannken * All rights reserved. 644b1e07eShannken * 744b1e07eShannken * This code is derived from software contributed to The NetBSD Foundation 844b1e07eShannken * by Juergen Hannken-Illjes. 944b1e07eShannken * 1044b1e07eShannken * Redistribution and use in source and binary forms, with or without 1144b1e07eShannken * modification, are permitted provided that the following conditions 1244b1e07eShannken * are met: 1344b1e07eShannken * 1. Redistributions of source code must retain the above copyright 1444b1e07eShannken * notice, this list of conditions and the following disclaimer. 1544b1e07eShannken * 2. Redistributions in binary form must reproduce the above copyright 1644b1e07eShannken * notice, this list of conditions and the following disclaimer in the 1744b1e07eShannken * documentation and/or other materials provided with the distribution. 1844b1e07eShannken * 1944b1e07eShannken * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2044b1e07eShannken * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2144b1e07eShannken * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2244b1e07eShannken * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2344b1e07eShannken * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2444b1e07eShannken * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2544b1e07eShannken * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2644b1e07eShannken * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2744b1e07eShannken * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2844b1e07eShannken * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2944b1e07eShannken * POSSIBILITY OF SUCH DAMAGE. 3044b1e07eShannken */ 3144b1e07eShannken 3244b1e07eShannken #ifndef _DCR403GCXP_H_ 3344b1e07eShannken #define _DCR403GCXP_H_ 3444b1e07eShannken 3544b1e07eShannken /* Device Control Register declarations */ 3644b1e07eShannken 3744b1e07eShannken #define DCR_EXISR 0x040 /* External Interrupt Status Register */ 3844b1e07eShannken #define DCR_EXIER 0x042 /* External Interrupt Enable Register */ 3944b1e07eShannken #define DCR_BRH0 0x070 /* Bank Register High 0 */ 4044b1e07eShannken #define DCR_BRH1 0x071 /* Bank Register High 1 */ 4144b1e07eShannken #define DCR_BRH2 0x072 /* Bank Register High 2 */ 4244b1e07eShannken #define DCR_BRH3 0x073 /* Bank Register High 3 */ 4344b1e07eShannken #define DCR_BRH4 0x074 /* Bank Register High 4 */ 4444b1e07eShannken #define DCR_BRH5 0x075 /* Bank Register High 5 */ 4544b1e07eShannken #define DCR_BRH6 0x076 /* Bank Register High 6 */ 4644b1e07eShannken #define DCR_BRH7 0x077 /* Bank Register High 7 */ 4744b1e07eShannken #define DCR_BR0 0x080 /* Bank Register 0 */ 4844b1e07eShannken #define DCR_BR1 0x081 /* Bank Register 1 */ 4944b1e07eShannken #define DCR_BR2 0x082 /* Bank Register 2 */ 5044b1e07eShannken #define DCR_BR3 0x083 /* Bank Register 3 */ 5144b1e07eShannken #define DCR_BR4 0x084 /* Bank Register 4 */ 5244b1e07eShannken #define DCR_BR5 0x085 /* Bank Register 5 */ 5344b1e07eShannken #define DCR_BR6 0x086 /* Bank Register 6 */ 5444b1e07eShannken #define DCR_BR7 0x087 /* Bank Register 7 */ 5544b1e07eShannken #define DCR_BEAR 0x090 /* Bus Error Address Register */ 5644b1e07eShannken #define DCR_BESR 0x091 /* Bus Error Syndrome Register */ 5744b1e07eShannken #define DCR_IOCR 0x0a0 /* I/O Configuration Register */ 5844b1e07eShannken #define DCR_DMACR0 0x0c0 /* DMA Channel Control Register 0 */ 5944b1e07eShannken #define DCR_DMACT0 0x0c1 /* DMA Count Register 0 */ 6044b1e07eShannken #define DCR_DMADA0 0x0c2 /* DMA Destination Address Reg. 0 */ 6144b1e07eShannken #define DCR_DMASA0 0x0c3 /* DMA Source Address Register 0 */ 6244b1e07eShannken #define DCR_DMACC0 0x0c4 /* DMA Chained Count 0 */ 6344b1e07eShannken #define DCR_DMACR1 0x0c8 /* DMA Channel Control Register 1 */ 6444b1e07eShannken #define DCR_DMACT1 0x0c9 /* DMA Count Register 1 */ 6544b1e07eShannken #define DCR_DMADA1 0x0cA /* DMA Destination Address Reg. 1 */ 6644b1e07eShannken #define DCR_DMACC1 0x0cC /* DMA Chained Count 1 */ 6744b1e07eShannken #define DCR_DMASA1 0x0cb /* DMA Source Address Register 1 */ 6844b1e07eShannken #define DCR_DMACR2 0x0d0 /* DMA Channel Control Register 2 */ 6944b1e07eShannken #define DCR_DMACT2 0x0d1 /* DMA Count Register 2 */ 7044b1e07eShannken #define DCR_DMADA2 0x0d2 /* DMA Destination Address Reg. 2 */ 7144b1e07eShannken #define DCR_DMASA2 0x0d3 /* DMA Source Address Register 2 */ 7244b1e07eShannken #define DCR_DMACC2 0x0d4 /* DMA Chained Count 2 */ 7344b1e07eShannken #define DCR_DMACR3 0x0d8 /* DMA Channel Control Register 3 */ 7444b1e07eShannken #define DCR_DMACT3 0x0d9 /* DMA Count Register 3 */ 7544b1e07eShannken #define DCR_DMADA3 0x0da /* DMA Destination Address Reg. 3 */ 7644b1e07eShannken #define DCR_DMASA3 0x0db /* DMA Source Address Register 3 */ 7744b1e07eShannken #define DCR_DMACC3 0x0dc /* DMA Chained Count 3 */ 7844b1e07eShannken #define DCR_DMASR 0x0e0 /* DMA Status Register */ 7944b1e07eShannken 8044b1e07eShannken #endif /* _DCR403GCXP_H_ */ 81