1 /* $NetBSD: fenv.h,v 1.7 2022/09/13 01:22:12 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $ 29 */ 30 31 #ifndef _POWERPC_FENV_H_ 32 #define _POWERPC_FENV_H_ 33 34 #include <sys/stdint.h> 35 36 /* Exception flags */ 37 #define FE_INEXACT 0x02000000 38 #define FE_DIVBYZERO 0x04000000 39 #define FE_UNDERFLOW 0x08000000 40 #define FE_OVERFLOW 0x10000000 41 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 42 43 /* 44 * The PowerPC architecture has extra invalid flags that indicate the 45 * specific type of invalid operation occurred. These flags may be 46 * tested, set, and cleared---but not masked---separately. All of 47 * these bits are cleared when FE_INVALID is cleared, but only 48 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 49 */ 50 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 51 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 52 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 53 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 54 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 55 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 56 #define FE_VXIDI 0x00400000 /* inf / inf */ 57 #define FE_VXISI 0x00800000 /* inf - inf */ 58 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 59 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 60 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 61 FE_VXSNAN | FE_INVALID) 62 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 63 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 64 65 /* Rounding modes */ 66 #define FE_TONEAREST 0x0000 67 #define FE_TOWARDZERO 0x0001 68 #define FE_UPWARD 0x0002 69 #define FE_DOWNWARD 0x0003 70 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 71 FE_UPWARD | FE_TOWARDZERO) 72 73 #ifndef _SOFT_FLOAT 74 75 #ifndef __fenv_static 76 #define __fenv_static static 77 #endif 78 79 typedef uint32_t fenv_t; 80 typedef uint32_t fexcept_t; 81 82 #ifndef _KERNEL 83 __BEGIN_DECLS 84 85 /* Default floating-point environment */ 86 extern const fenv_t __fe_dfl_env; 87 #define FE_DFL_ENV (&__fe_dfl_env) 88 89 /* We need to be able to map status flag positions to mask flag positions */ 90 #define _FPUSW_SHIFT 22 91 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 92 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 93 94 #ifndef _SOFT_FLOAT 95 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 96 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 97 98 static __inline uint32_t 99 __mfmsr(void) 100 { 101 uint32_t __msr; 102 103 __asm volatile ("mfmsr %0" : "=r"(__msr)); 104 return __msr; 105 } 106 107 static __inline void 108 __mtmsr(uint32_t __msr) 109 { 110 111 __asm volatile ("mtmsr %0" : : "r"(__msr)); 112 } 113 114 #define __MSR_FE_MASK (0x00000800 | 0x00000100) 115 #define __MSR_FE_DIS (0) 116 #define __MSR_FE_PREC (0x00000800 | 0x00000100) 117 118 static __inline void 119 __updatemsr(uint32_t __reg) 120 { 121 uint32_t __msr; 122 123 __msr = __mfmsr() & ~__MSR_FE_MASK; 124 if (__reg != 0) { 125 __msr |= __MSR_FE_PREC; 126 } else { 127 __msr |= __MSR_FE_DIS; 128 } 129 __mtmsr(__msr); 130 } 131 132 #else 133 #define __mffs(__env) 134 #define __mtfsf(__env) 135 #define __updatemsr(__reg) 136 #endif 137 138 union __fpscr { 139 double __d; 140 struct { 141 uint32_t __junk; 142 fenv_t __reg; 143 } __bits; 144 }; 145 146 #if __GNUC_PREREQ__(8, 0) 147 #pragma GCC diagnostic push 148 #pragma GCC diagnostic ignored "-Wshadow" 149 #endif 150 151 __fenv_static __inline int 152 feclearexcept(int __excepts) 153 { 154 union __fpscr __r; 155 156 if (__excepts & FE_INVALID) 157 __excepts |= FE_ALL_INVALID; 158 __mffs(&__r.__d); 159 __r.__bits.__reg &= ~__excepts; 160 __mtfsf(__r.__d); 161 return (0); 162 } 163 164 __fenv_static __inline int 165 fegetexceptflag(fexcept_t *__flagp, int __excepts) 166 { 167 union __fpscr __r; 168 169 __mffs(&__r.__d); 170 *__flagp = __r.__bits.__reg & __excepts; 171 return (0); 172 } 173 174 __fenv_static __inline int 175 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 176 { 177 union __fpscr __r; 178 179 if (__excepts & FE_INVALID) 180 __excepts |= FE_ALL_INVALID; 181 __mffs(&__r.__d); 182 __r.__bits.__reg &= ~__excepts; 183 __r.__bits.__reg |= *__flagp & __excepts; 184 __mtfsf(__r.__d); 185 return (0); 186 } 187 188 __fenv_static __inline int 189 feraiseexcept(int __excepts) 190 { 191 union __fpscr __r; 192 193 if (__excepts & FE_INVALID) 194 __excepts |= FE_VXSOFT; 195 __mffs(&__r.__d); 196 __r.__bits.__reg |= __excepts; 197 __mtfsf(__r.__d); 198 return (0); 199 } 200 201 __fenv_static __inline int 202 fetestexcept(int __excepts) 203 { 204 union __fpscr __r; 205 206 __mffs(&__r.__d); 207 return (__r.__bits.__reg & __excepts); 208 } 209 210 __fenv_static __inline int 211 fegetround(void) 212 { 213 union __fpscr __r; 214 215 __mffs(&__r.__d); 216 return (__r.__bits.__reg & _ROUND_MASK); 217 } 218 219 __fenv_static __inline int 220 fesetround(int __round) 221 { 222 union __fpscr __r; 223 224 if (__round & ~_ROUND_MASK) 225 return (-1); 226 __mffs(&__r.__d); 227 __r.__bits.__reg &= ~_ROUND_MASK; 228 __r.__bits.__reg |= __round; 229 __mtfsf(__r.__d); 230 return (0); 231 } 232 233 __fenv_static __inline int 234 fegetenv(fenv_t *__envp) 235 { 236 union __fpscr __r; 237 238 __mffs(&__r.__d); 239 *__envp = __r.__bits.__reg; 240 return (0); 241 } 242 243 __fenv_static __inline int 244 feholdexcept(fenv_t *__envp) 245 { 246 union __fpscr __r; 247 uint32_t msr; 248 249 __mffs(&__r.__d); 250 *__envp = __r.__bits.__reg; 251 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 252 __mtfsf(__r.__d); 253 __updatemsr(__r.__bits.__reg); 254 return (0); 255 } 256 257 __fenv_static __inline int 258 fesetenv(const fenv_t *__envp) 259 { 260 union __fpscr __r; 261 262 __r.__bits.__reg = *__envp; 263 __mtfsf(__r.__d); 264 __updatemsr(__r.__bits.__reg); 265 return (0); 266 } 267 268 __fenv_static __inline int 269 feupdateenv(const fenv_t *__envp) 270 { 271 union __fpscr __r; 272 273 __mffs(&__r.__d); 274 __r.__bits.__reg &= FE_ALL_EXCEPT; 275 __r.__bits.__reg |= *__envp; 276 __mtfsf(__r.__d); 277 __updatemsr(__r.__bits.__reg); 278 return (0); 279 } 280 281 #if __GNUC_PREREQ__(8, 0) 282 #pragma GCC diagnostic pop 283 #endif 284 285 #if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE) 286 287 __fenv_static __inline int 288 feenableexcept(int __mask) 289 { 290 union __fpscr __r; 291 fenv_t __oldmask; 292 293 __mffs(&__r.__d); 294 __oldmask = __r.__bits.__reg; 295 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 296 __mtfsf(__r.__d); 297 __updatemsr(__r.__bits.__reg); 298 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 299 } 300 301 __fenv_static __inline int 302 fedisableexcept(int __mask) 303 { 304 union __fpscr __r; 305 fenv_t __oldmask; 306 307 __mffs(&__r.__d); 308 __oldmask = __r.__bits.__reg; 309 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 310 __mtfsf(__r.__d); 311 __updatemsr(__r.__bits.__reg); 312 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 313 } 314 315 __fenv_static __inline int 316 fegetexcept(void) 317 { 318 union __fpscr __r; 319 320 __mffs(&__r.__d); 321 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 322 } 323 324 #endif /* _NETBSD_SOURCE || _GNU_SOURCE */ 325 326 __END_DECLS 327 328 #endif 329 #endif /* _SOFT_FLOAT */ 330 331 #endif /* !_POWERPC_FENV_H_ */ 332