1 /* $NetBSD: fenv.h,v 1.4 2017/09/18 23:21:15 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $ 29 */ 30 31 #ifndef _POWERPC_FENV_H_ 32 #define _POWERPC_FENV_H_ 33 34 #include <sys/stdint.h> 35 36 /* Exception flags */ 37 #define FE_INEXACT 0x02000000 38 #define FE_DIVBYZERO 0x04000000 39 #define FE_UNDERFLOW 0x08000000 40 #define FE_OVERFLOW 0x10000000 41 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 42 43 /* 44 * The PowerPC architecture has extra invalid flags that indicate the 45 * specific type of invalid operation occurred. These flags may be 46 * tested, set, and cleared---but not masked---separately. All of 47 * these bits are cleared when FE_INVALID is cleared, but only 48 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 49 */ 50 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 51 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 52 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 53 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 54 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 55 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 56 #define FE_VXIDI 0x00400000 /* inf / inf */ 57 #define FE_VXISI 0x00800000 /* inf - inf */ 58 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 59 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 60 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 61 FE_VXSNAN | FE_INVALID) 62 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 63 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 64 65 /* Rounding modes */ 66 #define FE_TONEAREST 0x0000 67 #define FE_TOWARDZERO 0x0001 68 #define FE_UPWARD 0x0002 69 #define FE_DOWNWARD 0x0003 70 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 71 FE_UPWARD | FE_TOWARDZERO) 72 73 #ifndef _SOFT_FLOAT 74 75 #ifndef __fenv_static 76 #define __fenv_static static 77 #endif 78 79 typedef uint32_t fenv_t; 80 typedef uint32_t fexcept_t; 81 82 #ifndef _KERNEL 83 __BEGIN_DECLS 84 85 /* Default floating-point environment */ 86 extern const fenv_t __fe_dfl_env; 87 #define FE_DFL_ENV (&__fe_dfl_env) 88 89 /* We need to be able to map status flag positions to mask flag positions */ 90 #define _FPUSW_SHIFT 22 91 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 92 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 93 94 #ifndef _SOFT_FLOAT 95 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 96 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 97 98 static inline uint32_t 99 __mfmsr(void) 100 { 101 uint32_t __msr; 102 103 __asm volatile ("mfmsr %0" : "=r"(__msr)); 104 return __msr; 105 } 106 107 static inline void 108 __mtmsr(uint32_t __msr) 109 { 110 111 __asm volatile ("mtmsr %0" : : "r"(__msr)); 112 } 113 114 #define __MSR_FE_MASK (0x00000800 | 0x00000100) 115 #define __MSR_FE_DIS (0) 116 #define __MSR_FE_PREC (0x00000800 | 0x00000100) 117 118 static inline void 119 __updatemsr(uint32_t __reg) 120 { 121 uint32_t __msr; 122 123 __msr = __mfmsr() & ~__MSR_FE_MASK; 124 if (__reg != 0) { 125 __msr |= __MSR_FE_PREC; 126 } else { 127 __msr |= __MSR_FE_DIS; 128 } 129 __mtmsr(__msr); 130 } 131 132 #else 133 #define __mffs(__env) 134 #define __mtfsf(__env) 135 #define __updatemsr(__reg) 136 #endif 137 138 union __fpscr { 139 double __d; 140 struct { 141 uint32_t __junk; 142 fenv_t __reg; 143 } __bits; 144 }; 145 146 __fenv_static inline int 147 feclearexcept(int __excepts) 148 { 149 union __fpscr __r; 150 151 if (__excepts & FE_INVALID) 152 __excepts |= FE_ALL_INVALID; 153 __mffs(&__r.__d); 154 __r.__bits.__reg &= ~__excepts; 155 __mtfsf(__r.__d); 156 return (0); 157 } 158 159 __fenv_static inline int 160 fegetexceptflag(fexcept_t *__flagp, int __excepts) 161 { 162 union __fpscr __r; 163 164 __mffs(&__r.__d); 165 *__flagp = __r.__bits.__reg & __excepts; 166 return (0); 167 } 168 169 __fenv_static inline int 170 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 171 { 172 union __fpscr __r; 173 174 if (__excepts & FE_INVALID) 175 __excepts |= FE_ALL_EXCEPT; 176 __mffs(&__r.__d); 177 __r.__bits.__reg &= ~__excepts; 178 __r.__bits.__reg |= *__flagp & __excepts; 179 __mtfsf(__r.__d); 180 return (0); 181 } 182 183 __fenv_static inline int 184 feraiseexcept(int __excepts) 185 { 186 union __fpscr __r; 187 188 if (__excepts & FE_INVALID) 189 __excepts |= FE_VXSOFT; 190 __mffs(&__r.__d); 191 __r.__bits.__reg |= __excepts; 192 __mtfsf(__r.__d); 193 return (0); 194 } 195 196 __fenv_static inline int 197 fetestexcept(int __excepts) 198 { 199 union __fpscr __r; 200 201 __mffs(&__r.__d); 202 return (__r.__bits.__reg & __excepts); 203 } 204 205 __fenv_static inline int 206 fegetround(void) 207 { 208 union __fpscr __r; 209 210 __mffs(&__r.__d); 211 return (__r.__bits.__reg & _ROUND_MASK); 212 } 213 214 __fenv_static inline int 215 fesetround(int __round) 216 { 217 union __fpscr __r; 218 219 if (__round & ~_ROUND_MASK) 220 return (-1); 221 __mffs(&__r.__d); 222 __r.__bits.__reg &= ~_ROUND_MASK; 223 __r.__bits.__reg |= __round; 224 __mtfsf(__r.__d); 225 return (0); 226 } 227 228 __fenv_static inline int 229 fegetenv(fenv_t *__envp) 230 { 231 union __fpscr __r; 232 233 __mffs(&__r.__d); 234 *__envp = __r.__bits.__reg; 235 return (0); 236 } 237 238 __fenv_static inline int 239 feholdexcept(fenv_t *__envp) 240 { 241 union __fpscr __r; 242 uint32_t msr; 243 244 __mffs(&__r.__d); 245 *__envp = __r.__bits.__reg; 246 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 247 __mtfsf(__r.__d); 248 __updatemsr(__r.__bits.__reg); 249 return (0); 250 } 251 252 __fenv_static inline int 253 fesetenv(const fenv_t *__envp) 254 { 255 union __fpscr __r; 256 257 __r.__bits.__reg = *__envp; 258 __mtfsf(__r.__d); 259 __updatemsr(__r.__bits.__reg); 260 return (0); 261 } 262 263 __fenv_static inline int 264 feupdateenv(const fenv_t *__envp) 265 { 266 union __fpscr __r; 267 268 __mffs(&__r.__d); 269 __r.__bits.__reg &= FE_ALL_EXCEPT; 270 __r.__bits.__reg |= *__envp; 271 __mtfsf(__r.__d); 272 __updatemsr(__r.__bits.__reg); 273 return (0); 274 } 275 276 #if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE) 277 278 __fenv_static inline int 279 feenableexcept(int __mask) 280 { 281 union __fpscr __r; 282 fenv_t __oldmask; 283 284 __mffs(&__r.__d); 285 __oldmask = __r.__bits.__reg; 286 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 287 __mtfsf(__r.__d); 288 __updatemsr(__r.__bits.__reg); 289 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 290 } 291 292 __fenv_static inline int 293 fedisableexcept(int __mask) 294 { 295 union __fpscr __r; 296 fenv_t __oldmask; 297 298 __mffs(&__r.__d); 299 __oldmask = __r.__bits.__reg; 300 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 301 __mtfsf(__r.__d); 302 __updatemsr(__r.__bits.__reg); 303 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 304 } 305 306 __fenv_static inline int 307 fegetexcept(void) 308 { 309 union __fpscr __r; 310 311 __mffs(&__r.__d); 312 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 313 } 314 315 #endif /* _NETBSD_SOURCE || _GNU_SOURCE */ 316 317 __END_DECLS 318 319 #endif 320 #endif /* _SOFT_FLOAT */ 321 322 #endif /* !_POWERPC_FENV_H_ */ 323